blob: ee8cb2336cfef34d985766d397bbdf567f9ca421 [file] [log] [blame]
Shaohui Xie02b5d2e2015-11-11 17:58:37 +08001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043AQDS_H__
8#define __LS1043AQDS_H__
9
10#include "ls1043a_common.h"
11
12#define CONFIG_DISPLAY_CPUINFO
13#define CONFIG_DISPLAY_BOARDINFO
14
15#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
16#define CONFIG_SYS_TEXT_BASE 0x82000000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +080017#elif defined(CONFIG_QSPI_BOOT)
18#define CONFIG_SYS_TEXT_BASE 0x40010000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080019#else
20#define CONFIG_SYS_TEXT_BASE 0x60100000
21#endif
22
23#ifndef __ASSEMBLY__
24unsigned long get_board_sys_clk(void);
25unsigned long get_board_ddr_clk(void);
26#endif
27
Qianyu Gong581ff002016-06-13 11:20:31 +080028#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
29#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080030
31#define CONFIG_SKIP_LOWLEVEL_INIT
32
33#define CONFIG_LAYERSCAPE_NS_ACCESS
34
35#define CONFIG_DIMM_SLOTS_PER_CTLR 1
36/* Physical Memory Map */
37#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Shaohui Xie58e4ad12016-01-04 11:03:44 +080038#define CONFIG_NR_DRAM_BANKS 2
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080039
40#define CONFIG_DDR_SPD
41#define SPD_EEPROM_ADDRESS 0x51
42#define CONFIG_SYS_SPD_BUS_NUM 0
43
44#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
45#ifndef CONFIG_SYS_FSL_DDR4
46#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
47#endif
48
49#define CONFIG_DDR_ECC
50#ifdef CONFIG_DDR_ECC
51#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
53#endif
54
55#define CONFIG_SYS_HAS_SERDES
56
57#ifdef CONFIG_SYS_DPAA_FMAN
58#define CONFIG_FMAN_ENET
59#define CONFIG_PHYLIB
60#define CONFIG_PHY_VITESSE
61#define CONFIG_PHY_REALTEK
62#define CONFIG_PHYLIB_10G
63#define RGMII_PHY1_ADDR 0x1
64#define RGMII_PHY2_ADDR 0x2
65#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
66#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
67#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
68#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
69/* PHY address on QSGMII riser card on slot 1 */
70#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
71#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
72#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
73#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
74/* PHY address on QSGMII riser card on slot 2 */
75#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
76#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
77#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
78#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
79#endif
80
81#ifdef CONFIG_RAMBOOT_PBL
82#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
83#endif
84
85#ifdef CONFIG_NAND_BOOT
86#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
87#endif
88
89#ifdef CONFIG_SD_BOOT
Gong Qianyu166ef1e2016-01-25 15:16:06 +080090#ifdef CONFIG_SD_BOOT_QSPI
91#define CONFIG_SYS_FSL_PBL_RCW \
92 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
93#else
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080094#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
95#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +080096#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +080097
Wenbin Song2970e142016-01-21 17:14:55 +080098/* LPUART */
99#ifdef CONFIG_LPUART
100#define CONFIG_LPUART_32B_REG
101#endif
102
Tang Yuantian989c5f02015-12-09 15:32:18 +0800103/* SATA */
104#define CONFIG_LIBATA
105#define CONFIG_SCSI_AHCI
106#define CONFIG_SCSI_AHCI_PLAT
Simon Glassc649e3c2016-05-01 11:36:02 -0600107#define CONFIG_SCSI
Tang Yuantian989c5f02015-12-09 15:32:18 +0800108#define CONFIG_DOS_PARTITION
109#define CONFIG_BOARD_LATE_INIT
110
Wenbin Songceded372016-03-09 13:38:25 +0800111/* EEPROM */
112#define CONFIG_ID_EEPROM
113#define CONFIG_SYS_I2C_EEPROM_NXID
114#define CONFIG_SYS_EEPROM_BUS_NUM 0
115#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
116#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
117#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
118#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
119
Tang Yuantian989c5f02015-12-09 15:32:18 +0800120#define CONFIG_SYS_SATA AHCI_BASE_ADDR
121
122#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
123#define CONFIG_SYS_SCSI_MAX_LUN 1
124#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
125 CONFIG_SYS_SCSI_MAX_LUN)
126
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800127/*
128 * IFC Definitions
129 */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800130#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800131#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
132#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
133 CSPR_PORT_SIZE_16 | \
134 CSPR_MSEL_NOR | \
135 CSPR_V)
136#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
137#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
138 + 0x8000000) | \
139 CSPR_PORT_SIZE_16 | \
140 CSPR_MSEL_NOR | \
141 CSPR_V)
142#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
143
144#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
145 CSOR_NOR_TRHZ_80)
146#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
147 FTIM0_NOR_TEADC(0x5) | \
148 FTIM0_NOR_TEAHC(0x5))
149#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
150 FTIM1_NOR_TRAD_NOR(0x1a) | \
151 FTIM1_NOR_TSEQRAD_NOR(0x13))
152#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
153 FTIM2_NOR_TCH(0x4) | \
154 FTIM2_NOR_TWPH(0xe) | \
155 FTIM2_NOR_TWP(0x1c))
156#define CONFIG_SYS_NOR_FTIM3 0
157
Wenbin Song1b245d92016-04-01 17:28:41 +0800158#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800159#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
160#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
161#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
162
163#define CONFIG_SYS_FLASH_EMPTY_INFO
164#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
165 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
166
167#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
168#define CONFIG_SYS_WRITE_SWAPPED_DATA
169
170/*
171 * NAND Flash Definitions
172 */
173#define CONFIG_NAND_FSL_IFC
174
175#define CONFIG_SYS_NAND_BASE 0x7e800000
176#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
177
178#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
179
180#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
181 | CSPR_PORT_SIZE_8 \
182 | CSPR_MSEL_NAND \
183 | CSPR_V)
184#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
185#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
186 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
187 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
188 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
189 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
190 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
191 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
192
193#define CONFIG_SYS_NAND_ONFI_DETECTION
194
195#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
196 FTIM0_NAND_TWP(0x18) | \
197 FTIM0_NAND_TWCHT(0x7) | \
198 FTIM0_NAND_TWH(0xa))
199#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
200 FTIM1_NAND_TWBE(0x39) | \
201 FTIM1_NAND_TRR(0xe) | \
202 FTIM1_NAND_TRP(0x18))
203#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
204 FTIM2_NAND_TREH(0xa) | \
205 FTIM2_NAND_TWHRE(0x1e))
206#define CONFIG_SYS_NAND_FTIM3 0x0
207
208#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
209#define CONFIG_SYS_MAX_NAND_DEVICE 1
210#define CONFIG_MTD_NAND_VERIFY_WRITE
211#define CONFIG_CMD_NAND
212
213#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800214#endif
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800215
216#ifdef CONFIG_NAND_BOOT
217#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
218#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
219#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
220#endif
221
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800222#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800223#define CONFIG_QIXIS_I2C_ACCESS
Qianyu Gong581ff002016-06-13 11:20:31 +0800224#define CONFIG_SYS_I2C_EARLY_INIT
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800225#define CONFIG_SYS_NO_FLASH
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800226#endif
227
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800228/*
229 * QIXIS Definitions
230 */
231#define CONFIG_FSL_QIXIS
232
233#ifdef CONFIG_FSL_QIXIS
234#define QIXIS_BASE 0x7fb00000
235#define QIXIS_BASE_PHYS QIXIS_BASE
236#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
237#define QIXIS_LBMAP_SWITCH 6
238#define QIXIS_LBMAP_MASK 0x0f
239#define QIXIS_LBMAP_SHIFT 0
240#define QIXIS_LBMAP_DFLTBANK 0x00
241#define QIXIS_LBMAP_ALTBANK 0x04
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800242#define QIXIS_LBMAP_NAND 0x09
243#define QIXIS_LBMAP_SD 0x00
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800244#define QIXIS_LBMAP_SD_QSPI 0xff
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800245#define QIXIS_LBMAP_QSPI 0xff
Gong Qianyuee2a4ee2015-12-31 18:29:04 +0800246#define QIXIS_RCW_SRC_NAND 0x106
247#define QIXIS_RCW_SRC_SD 0x040
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800248#define QIXIS_RCW_SRC_QSPI 0x045
Gong Qianyua4b7d682015-12-31 18:29:03 +0800249#define QIXIS_RST_CTL_RESET 0x41
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800250#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
251#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
252#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
253
254#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
255#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
256 CSPR_PORT_SIZE_8 | \
257 CSPR_MSEL_GPCM | \
258 CSPR_V)
259#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
260#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
261 CSOR_NOR_NOR_MODE_AVD_NOR | \
262 CSOR_NOR_TRHZ_80)
263
264/*
265 * QIXIS Timing parameters for IFC GPCM
266 */
267#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
268 FTIM0_GPCM_TEADC(0x20) | \
269 FTIM0_GPCM_TEAHC(0x10))
270#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
271 FTIM1_GPCM_TRAD(0x1f))
272#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
273 FTIM2_GPCM_TCH(0x8) | \
274 FTIM2_GPCM_TWP(0xf0))
275#define CONFIG_SYS_FPGA_FTIM3 0x0
276#endif
277
278#ifdef CONFIG_NAND_BOOT
279#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
280#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
281#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
282#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
283#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
284#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
285#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
286#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
287#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
288#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
289#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
290#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
291#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
292#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
293#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
294#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
295#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
296#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
297#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
298#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
299#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
300#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
301#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
302#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
303#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
304#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
305#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
306#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
307#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
308#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
309#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
310#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
311#else
312#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
313#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
314#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
315#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
316#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
317#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
318#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
319#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
320#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
321#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
322#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
323#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
324#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
325#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
326#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
327#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
328#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
329#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
330#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
331#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
332#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
333#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
334#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
335#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
336#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
337#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
338#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
339#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
340#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
341#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
342#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
343#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
344#endif
345
346/*
347 * I2C bus multiplexer
348 */
349#define I2C_MUX_PCA_ADDR_PRI 0x77
350#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
351#define I2C_RETIMER_ADDR 0x18
352#define I2C_MUX_CH_DEFAULT 0x8
353#define I2C_MUX_CH_CH7301 0xC
354#define I2C_MUX_CH5 0xD
355#define I2C_MUX_CH7 0xF
356
357#define I2C_MUX_CH_VOL_MONITOR 0xa
358
359/* Voltage monitor on channel 2*/
360#define I2C_VOL_MONITOR_ADDR 0x40
361#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
362#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
363#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
364
365#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
366#ifndef CONFIG_SPL_BUILD
367#define CONFIG_VID
368#endif
369#define CONFIG_VOL_MONITOR_IR36021_SET
370#define CONFIG_VOL_MONITOR_INA220
371/* The lowest and highest voltage allowed for LS1043AQDS */
372#define VDD_MV_MIN 819
373#define VDD_MV_MAX 1212
374
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800375/* QSPI device */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800376#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800377#define CONFIG_FSL_QSPI
378#ifdef CONFIG_FSL_QSPI
379#define CONFIG_SPI_FLASH_SPANSION
380#define FSL_QSPI_FLASH_SIZE (1 << 24)
381#define FSL_QSPI_FLASH_NUM 2
382#endif
383#endif
384
Qianyu Gong5a7c40b2016-02-16 13:12:53 +0800385/* USB */
386#define CONFIG_HAS_FSL_XHCI_USB
387#ifdef CONFIG_HAS_FSL_XHCI_USB
Qianyu Gong5a7c40b2016-02-16 13:12:53 +0800388#define CONFIG_USB_XHCI_FSL
Qianyu Gong5a7c40b2016-02-16 13:12:53 +0800389#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
390#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
Qianyu Gong5a7c40b2016-02-16 13:12:53 +0800391#define CONFIG_USB_STORAGE
Qianyu Gong5a7c40b2016-02-16 13:12:53 +0800392#endif
393
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800394/*
395 * Miscellaneous configurable options
396 */
397#define CONFIG_MISC_INIT_R
398#define CONFIG_SYS_LONGHELP /* undef to save memory */
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800399#define CONFIG_AUTO_COMPLETE
400#define CONFIG_SYS_PBSIZE \
401 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
402#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
403
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800404#define CONFIG_SYS_MEMTEST_START 0x80000000
405#define CONFIG_SYS_MEMTEST_END 0x9fffffff
406
407#define CONFIG_SYS_HZ 1000
408
409/*
410 * Stack sizes
411 * The stack sizes are set up in start.S using the settings below
412 */
413#define CONFIG_STACKSIZE (30 * 1024)
414
415#define CONFIG_SYS_INIT_SP_OFFSET \
416 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
417
418#ifdef CONFIG_SPL_BUILD
419#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
420#else
421#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
422#endif
423
424/*
425 * Environment
426 */
427#define CONFIG_ENV_OVERWRITE
428
429#ifdef CONFIG_NAND_BOOT
430#define CONFIG_ENV_IS_IN_NAND
431#define CONFIG_ENV_SIZE 0x2000
432#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
433#elif defined(CONFIG_SD_BOOT)
434#define CONFIG_ENV_OFFSET (1024 * 1024)
435#define CONFIG_ENV_IS_IN_MMC
436#define CONFIG_SYS_MMC_ENV_DEV 0
437#define CONFIG_ENV_SIZE 0x2000
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800438#elif defined(CONFIG_QSPI_BOOT)
439#define CONFIG_ENV_IS_IN_SPI_FLASH
440#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
441#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
442#define CONFIG_ENV_SECT_SIZE 0x10000
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800443#else
444#define CONFIG_ENV_IS_IN_FLASH
445#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
446#define CONFIG_ENV_SECT_SIZE 0x20000
447#define CONFIG_ENV_SIZE 0x20000
448#endif
449
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800450#define CONFIG_CMDLINE_TAG
451
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530452#include <asm/fsl_secure_boot.h>
453
Shaohui Xie02b5d2e2015-11-11 17:58:37 +0800454#endif /* __LS1043AQDS_H__ */