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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Rixcd782632009-06-28 12:52:29 -05002/*
3 * Copyright (c) 2009 Wind River Systems, Inc.
4 * Tom Rix <Tom.Rix at windriver.com>
5 *
Tom Rix2c155132009-06-28 12:52:30 -05006 * twl4030_power_reset_init is derived from code on omapzoom,
7 * git://git.omapzoom.com/repo/u-boot.git
Tom Rixcd782632009-06-28 12:52:29 -05008 *
9 * Copyright (C) 2007-2009 Texas Instruments, Inc.
Tom Rix2c155132009-06-28 12:52:30 -050010 *
11 * twl4030_power_init is from cpu/omap3/common.c, power_init_r
12 *
13 * (C) Copyright 2004-2008
14 * Texas Instruments, <www.ti.com>
15 *
16 * Author :
17 * Sunil Kumar <sunilsaini05 at gmail.com>
18 * Shashi Ranjan <shashiranjanmca05 at gmail.com>
19 *
20 * Derived from Beagle Board and 3430 SDP code by
21 * Richard Woodruff <r-woodruff2 at ti.com>
22 * Syed Mohammed Khasim <khasim at ti.com>
Tom Rixcd782632009-06-28 12:52:29 -050023 */
24
25#include <twl4030.h>
26
27/*
28 * Power Reset
29 */
30void twl4030_power_reset_init(void)
31{
32 u8 val = 0;
Nishanth Menonb29c2f02013-03-26 05:20:50 +000033 if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
34 TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) {
Tom Rixcd782632009-06-28 12:52:29 -050035 printf("Error:TWL4030: failed to read the power register\n");
36 printf("Could not initialize hardware reset\n");
37 } else {
38 val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
Nishanth Menon0208aaf2013-03-26 05:20:49 +000039 if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
40 TWL4030_PM_MASTER_P1_SW_EVENTS, val)) {
Tom Rixcd782632009-06-28 12:52:29 -050041 printf("Error:TWL4030: failed to write the power register\n");
42 printf("Could not initialize hardware reset\n");
43 }
44 }
45}
46
Tom Rix2c155132009-06-28 12:52:30 -050047/*
Paul Kocialkowski6dc443e2015-07-20 15:17:07 +020048 * Power off
49 */
50void twl4030_power_off(void)
51{
52 u8 data;
53
54 /* PM master unlock (CFG and TST keys) */
55
56 data = 0xCE;
57 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
58 TWL4030_PM_MASTER_PROTECT_KEY, data);
59 data = 0xEC;
60 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
61 TWL4030_PM_MASTER_PROTECT_KEY, data);
62
63 /* VBAT start disable */
64
65 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
66 TWL4030_PM_MASTER_CFG_P1_TRANSITION, &data);
67 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
68 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
69 TWL4030_PM_MASTER_CFG_P1_TRANSITION, data);
70
71 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
72 TWL4030_PM_MASTER_CFG_P2_TRANSITION, &data);
73 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
74 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
75 TWL4030_PM_MASTER_CFG_P2_TRANSITION, data);
76
77 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
78 TWL4030_PM_MASTER_CFG_P3_TRANSITION, &data);
79 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
80 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
81 TWL4030_PM_MASTER_CFG_P3_TRANSITION, data);
82
83 /* High jitter for PWRANA2 */
84
85 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
86 TWL4030_PM_MASTER_CFG_PWRANA2, &data);
87 data &= ~(TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV |
88 TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV);
89 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
90 TWL4030_PM_MASTER_CFG_PWRANA2, data);
91
92 /* PM master lock */
93
94 data = 0xFF;
95 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
96 TWL4030_PM_MASTER_PROTECT_KEY, data);
97
98 /* Power off */
99
100 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
101 TWL4030_PM_MASTER_P1_SW_EVENTS, &data);
102 data |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
103 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
104 TWL4030_PM_MASTER_P1_SW_EVENTS, data);
105}
106
107/*
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700108 * Set Device Group and Voltage
Tom Rix2c155132009-06-28 12:52:30 -0500109 */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700110void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
111 u8 dev_grp, u8 dev_grp_sel)
112{
Grazvydas Ignotas61712bc2012-03-19 03:37:40 +0000113 int ret;
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700114
115 /* Select the Voltage */
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000116 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg,
117 vsel_val);
Grazvydas Ignotas61712bc2012-03-19 03:37:40 +0000118 if (ret != 0) {
Peter Meerwalddfe36102012-11-19 23:13:04 +0000119 printf("Could not write vsel to reg %02x (%d)\n",
Grazvydas Ignotas61712bc2012-03-19 03:37:40 +0000120 vsel_reg, ret);
121 return;
122 }
123
124 /* Select the Device Group (enable the supply if dev_grp_sel != 0) */
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000125 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp,
126 dev_grp_sel);
Grazvydas Ignotas61712bc2012-03-19 03:37:40 +0000127 if (ret != 0)
Peter Meerwalddfe36102012-11-19 23:13:04 +0000128 printf("Could not write grp_sel to reg %02x (%d)\n",
Grazvydas Ignotas61712bc2012-03-19 03:37:40 +0000129 dev_grp, ret);
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700130}
Tom Rix2c155132009-06-28 12:52:30 -0500131
132void twl4030_power_init(void)
133{
Tom Rix2c155132009-06-28 12:52:30 -0500134 /* set VAUX3 to 2.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700135 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
136 TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
137 TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
138 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix2c155132009-06-28 12:52:30 -0500139
140 /* set VPLL2 to 1.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700141 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
142 TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
143 TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
144 TWL4030_PM_RECEIVER_DEV_GRP_ALL);
Tom Rix2c155132009-06-28 12:52:30 -0500145
146 /* set VDAC to 1.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700147 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
148 TWL4030_PM_RECEIVER_VDAC_VSEL_18,
149 TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
150 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix2c155132009-06-28 12:52:30 -0500151}
152
Paul Kocialkowskif3e85e42014-11-08 20:55:46 +0100153void twl4030_power_mmc_init(int dev_index)
Tom Rixfccc0fc2009-06-28 12:52:31 -0500154{
Paul Kocialkowskif3e85e42014-11-08 20:55:46 +0100155 if (dev_index == 0) {
156 /* Set VMMC1 to 3.15 Volts */
157 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
158 TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
159 TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
160 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Paul Kocialkowski2ed8c872014-10-28 18:14:23 +0100161
Paul Kocialkowskif3e85e42014-11-08 20:55:46 +0100162 mdelay(100); /* ramp-up delay from Linux code */
163 } else if (dev_index == 1) {
164 /* Set VMMC2 to 3.15 Volts */
165 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
166 TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
167 TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
168 TWL4030_PM_RECEIVER_DEV_GRP_P1);
169
170 mdelay(100); /* ramp-up delay from Linux code */
171 }
Tom Rixfccc0fc2009-06-28 12:52:31 -0500172}
Adam Ford4c2fb5f2017-04-24 13:34:43 -0500173
174#ifdef CONFIG_CMD_POWEROFF
175int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
176{
177 twl4030_power_off();
178
179 return 0;
180}
181#endif
Jean-Jacques Hiblotfb1b7712018-12-07 14:50:46 +0100182
183#ifdef CONFIG_DM_I2C
184int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
185{
186 struct udevice *dev;
187 int ret;
188
189 ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev);
190 if (ret) {
191 pr_err("unable to get I2C bus. ret %d\n", ret);
192 return ret;
193 }
194 ret = dm_i2c_reg_write(dev, reg, val);
195 if (ret) {
196 pr_err("writing to twl4030 failed. ret %d\n", ret);
197 return ret;
198 }
199 return 0;
200}
201
202int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp)
203{
204 struct udevice *dev;
205 int ret;
206
207 ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev);
208 if (ret) {
209 pr_err("unable to get I2C bus. ret %d\n", ret);
210 return ret;
211 }
212 ret = dm_i2c_reg_read(dev, reg);
213 if (ret < 0) {
214 pr_err("reading from twl4030 failed. ret %d\n", ret);
215 return ret;
216 }
217 *valp = (u8)ret;
218 return 0;
219}
220#endif