blob: 496f4feec5666a5acabc1207472ca2cfa98ac1d1 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +02002/*
3 * LPC32xx I2C interface driver
4 *
Sylvain Lemieux1933af12015-08-04 17:04:41 -04005 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +02006 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +02007 */
8
9#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020011#include <asm/io.h>
12#include <i2c.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020014#include <asm/arch/clk.h>
Liam Beguinfb0578802017-03-14 11:24:44 -040015#include <asm/arch/i2c.h>
Liam Beguind61c7ad2017-03-27 11:13:12 -040016#include <dm.h>
17#include <mapmem.h>
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020018
19/*
20 * Provide default speed and slave if target did not
21 */
22
Tom Rini6e7df1d2023-01-10 11:19:45 -050023#if !defined(CFG_SYS_I2C_LPC32XX_SPEED)
24#define CFG_SYS_I2C_LPC32XX_SPEED 350000
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020025#endif
26
Tom Rini6e7df1d2023-01-10 11:19:45 -050027#if !defined(CFG_SYS_I2C_LPC32XX_SLAVE)
28#define CFG_SYS_I2C_LPC32XX_SLAVE 0
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020029#endif
30
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020031/* TX register fields */
32#define LPC32XX_I2C_TX_START 0x00000100
33#define LPC32XX_I2C_TX_STOP 0x00000200
34
35/* Control register values */
36#define LPC32XX_I2C_SOFT_RESET 0x00000100
37
38/* Status register values */
39#define LPC32XX_I2C_STAT_TFF 0x00000400
40#define LPC32XX_I2C_STAT_RFE 0x00000200
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020041#define LPC32XX_I2C_STAT_NAI 0x00000004
42#define LPC32XX_I2C_STAT_TDI 0x00000001
43
Igor Opaniuk2147a162021-02-09 13:52:45 +020044#if !CONFIG_IS_ENABLED(DM_I2C)
Liam Beguineddac8e2017-03-27 11:11:36 -040045static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
46 (struct lpc32xx_i2c_base *)I2C1_BASE,
47 (struct lpc32xx_i2c_base *)I2C2_BASE,
48 (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020049};
Liam Beguind61c7ad2017-03-27 11:13:12 -040050#endif
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020051
52/* Set I2C bus speed */
Liam Beguineddac8e2017-03-27 11:11:36 -040053static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
54 unsigned int speed, unsigned int chip)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020055{
56 int half_period;
57
58 if (speed == 0)
59 return -EINVAL;
60
Vladimir Zapolskiyea16c6a2015-08-12 20:22:13 +030061 /* OTG I2C clock source and CLK registers are different */
Liam Beguineddac8e2017-03-27 11:11:36 -040062 if (chip == 2) {
Vladimir Zapolskiyea16c6a2015-08-12 20:22:13 +030063 half_period = (get_periph_clk_rate() / speed) / 2;
64 if (half_period > 0xFF)
65 return -EINVAL;
66 } else {
67 half_period = (get_hclk_clk_rate() / speed) / 2;
68 if (half_period > 0x3FF)
69 return -EINVAL;
70 }
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020071
Liam Beguineddac8e2017-03-27 11:11:36 -040072 writel(half_period, &base->clk_hi);
73 writel(half_period, &base->clk_lo);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020074 return 0;
75}
76
77/* I2C init called by cmd_i2c when doing 'i2c reset'. */
Liam Beguineddac8e2017-03-27 11:11:36 -040078static void __i2c_init(struct lpc32xx_i2c_base *base,
79 int requested_speed, int slaveadd, unsigned int chip)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020080{
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020081 /* soft reset (auto-clears) */
Liam Beguineddac8e2017-03-27 11:11:36 -040082 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
Vladimir Zapolskiyea16c6a2015-08-12 20:22:13 +030083 /* set HI and LO periods for half of the default speed */
Liam Beguineddac8e2017-03-27 11:11:36 -040084 __i2c_set_bus_speed(base, requested_speed, chip);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020085}
86
87/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
Liam Beguineddac8e2017-03-27 11:11:36 -040088static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020089{
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020090 int stat;
91
92 /* Soft-reset the controller */
Liam Beguineddac8e2017-03-27 11:11:36 -040093 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
94 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020095 ;
96 /* Addre slave for write with start before and stop after */
97 writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
Liam Beguineddac8e2017-03-27 11:11:36 -040098 &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020099 /* wait for end of transation */
Liam Beguineddac8e2017-03-27 11:11:36 -0400100 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200101 ;
102 /* was there no acknowledge? */
103 return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
104}
105
106/*
107 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
108 * Begin write, send address byte(s), begin read, receive data bytes, end.
109 */
Liam Beguineddac8e2017-03-27 11:11:36 -0400110static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
111 int alen, u8 *data, int length)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200112{
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200113 int stat, wlen;
114
115 /* Soft-reset the controller */
Liam Beguineddac8e2017-03-27 11:11:36 -0400116 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
117 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200118 ;
119 /* do we need to write an address at all? */
120 if (alen) {
121 /* Address slave in write mode */
Liam Beguineddac8e2017-03-27 11:11:36 -0400122 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200123 /* write address bytes */
124 while (alen--) {
125 /* compute address byte + stop for the last one */
126 int a = (addr >> (8 * alen)) & 0xff;
127 if (!alen)
128 a |= LPC32XX_I2C_TX_STOP;
129 /* Send address byte */
Liam Beguineddac8e2017-03-27 11:11:36 -0400130 writel(a, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200131 }
132 /* wait for end of transation */
Liam Beguineddac8e2017-03-27 11:11:36 -0400133 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200134 ;
135 /* clear end-of-transaction flag */
Liam Beguineddac8e2017-03-27 11:11:36 -0400136 writel(1, &base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200137 }
138 /* do we have to read data at all? */
139 if (length) {
140 /* Address slave in read mode */
Liam Beguineddac8e2017-03-27 11:11:36 -0400141 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200142 wlen = length;
143 /* get data */
144 while (length | wlen) {
145 /* read status for TFF and RFE */
Liam Beguineddac8e2017-03-27 11:11:36 -0400146 stat = readl(&base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200147 /* must we, can we write a trigger byte? */
148 if ((wlen > 0)
149 & (!(stat & LPC32XX_I2C_STAT_TFF))) {
150 wlen--;
151 /* write trigger byte + stop if last */
152 writel(wlen ? 0 :
Liam Beguineddac8e2017-03-27 11:11:36 -0400153 LPC32XX_I2C_TX_STOP, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200154 }
155 /* must we, can we read a data byte? */
156 if ((length > 0)
157 & (!(stat & LPC32XX_I2C_STAT_RFE))) {
158 length--;
159 /* read byte */
Liam Beguineddac8e2017-03-27 11:11:36 -0400160 *(data++) = readl(&base->rx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200161 }
162 }
Sylvain Lemieux3d2b6a22015-07-27 13:37:38 -0400163 /* wait for end of transation */
Liam Beguineddac8e2017-03-27 11:11:36 -0400164 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
Sylvain Lemieux3d2b6a22015-07-27 13:37:38 -0400165 ;
166 /* clear end-of-transaction flag */
Liam Beguineddac8e2017-03-27 11:11:36 -0400167 writel(1, &base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200168 }
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200169 /* success */
170 return 0;
171}
172
173/*
174 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
175 * Begin write, send address byte(s), send data bytes, end.
176 */
Liam Beguineddac8e2017-03-27 11:11:36 -0400177static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
178 int alen, u8 *data, int length)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200179{
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200180 int stat;
181
182 /* Soft-reset the controller */
Liam Beguineddac8e2017-03-27 11:11:36 -0400183 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
184 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200185 ;
186 /* do we need to write anything at all? */
187 if (alen | length)
188 /* Address slave in write mode */
Liam Beguineddac8e2017-03-27 11:11:36 -0400189 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
Sylvain Lemieux58243002015-07-27 13:37:39 -0400190 else
191 return 0;
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200192 /* write address bytes */
193 while (alen) {
194 /* wait for transmit fifo not full */
Liam Beguineddac8e2017-03-27 11:11:36 -0400195 stat = readl(&base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200196 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
197 alen--;
198 int a = (addr >> (8 * alen)) & 0xff;
199 if (!(alen | length))
200 a |= LPC32XX_I2C_TX_STOP;
201 /* Send address byte */
Liam Beguineddac8e2017-03-27 11:11:36 -0400202 writel(a, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200203 }
204 }
205 while (length) {
206 /* wait for transmit fifo not full */
Liam Beguineddac8e2017-03-27 11:11:36 -0400207 stat = readl(&base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200208 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
209 /* compute data byte, add stop if length==0 */
210 length--;
211 int d = *(data++);
212 if (!length)
213 d |= LPC32XX_I2C_TX_STOP;
214 /* Send data byte */
Liam Beguineddac8e2017-03-27 11:11:36 -0400215 writel(d, &base->tx);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200216 }
217 }
218 /* wait for end of transation */
Liam Beguineddac8e2017-03-27 11:11:36 -0400219 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200220 ;
221 /* clear end-of-transaction flag */
Liam Beguineddac8e2017-03-27 11:11:36 -0400222 writel(1, &base->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200223 return 0;
224}
225
Igor Opaniuk2147a162021-02-09 13:52:45 +0200226#if !CONFIG_IS_ENABLED(DM_I2C)
Liam Beguin552531e2017-03-14 11:24:40 -0400227static void lpc32xx_i2c_init(struct i2c_adapter *adap,
228 int requested_speed, int slaveadd)
229{
Liam Beguineddac8e2017-03-27 11:11:36 -0400230 __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
231 adap->hwadapnr);
Liam Beguin552531e2017-03-14 11:24:40 -0400232}
233
234static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
235{
Liam Beguineddac8e2017-03-27 11:11:36 -0400236 return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
Liam Beguin552531e2017-03-14 11:24:40 -0400237}
238
239static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
240 int alen, u8 *data, int length)
241{
Liam Beguineddac8e2017-03-27 11:11:36 -0400242 return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
243 alen, data, length);
Liam Beguin552531e2017-03-14 11:24:40 -0400244}
245
246static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
247 int alen, u8 *data, int length)
248{
Liam Beguineddac8e2017-03-27 11:11:36 -0400249 return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
250 alen, data, length);
Liam Beguin552531e2017-03-14 11:24:40 -0400251}
252
253static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
254 unsigned int speed)
255{
Liam Beguineddac8e2017-03-27 11:11:36 -0400256 return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
257 adap->hwadapnr);
Liam Beguin552531e2017-03-14 11:24:40 -0400258}
259
260U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200261 lpc32xx_i2c_read, lpc32xx_i2c_write,
262 lpc32xx_i2c_set_bus_speed,
Tom Rini6e7df1d2023-01-10 11:19:45 -0500263 CFG_SYS_I2C_LPC32XX_SPEED,
264 CFG_SYS_I2C_LPC32XX_SLAVE,
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200265 0)
266
Liam Beguin552531e2017-03-14 11:24:40 -0400267U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200268 lpc32xx_i2c_read, lpc32xx_i2c_write,
269 lpc32xx_i2c_set_bus_speed,
Tom Rini6e7df1d2023-01-10 11:19:45 -0500270 CFG_SYS_I2C_LPC32XX_SPEED,
271 CFG_SYS_I2C_LPC32XX_SLAVE,
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200272 1)
Sylvain Lemieux1933af12015-08-04 17:04:41 -0400273
Liam Beguin552531e2017-03-14 11:24:40 -0400274U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
Sylvain Lemieux1933af12015-08-04 17:04:41 -0400275 lpc32xx_i2c_read, lpc32xx_i2c_write,
276 lpc32xx_i2c_set_bus_speed,
277 100000,
278 0,
279 2)
Liam Beguind61c7ad2017-03-27 11:13:12 -0400280#else /* CONFIG_DM_I2C */
281static int lpc32xx_i2c_probe(struct udevice *bus)
282{
Simon Glassc69cda22020-12-03 16:55:20 -0700283 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
Simon Glass8b85dfc2020-12-16 21:20:07 -0700284
Trevor Woerner3f70acd2021-06-10 22:37:06 -0400285 dev->base = dev_read_addr_ptr(bus);
Liam Beguind61c7ad2017-03-27 11:13:12 -0400286 __i2c_init(dev->base, dev->speed, 0, dev->index);
287 return 0;
288}
289
290static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
291 u32 chip_flags)
292{
Simon Glassc69cda22020-12-03 16:55:20 -0700293 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
Liam Beguind61c7ad2017-03-27 11:13:12 -0400294 return __i2c_probe_chip(dev->base, chip_addr);
295}
296
297static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
298 int nmsgs)
299{
Simon Glassc69cda22020-12-03 16:55:20 -0700300 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
Liam Beguind61c7ad2017-03-27 11:13:12 -0400301 struct i2c_msg *dmsg, *omsg, dummy;
302 uint i = 0, address = 0;
303
304 memset(&dummy, 0, sizeof(struct i2c_msg));
305
306 /* We expect either two messages (one with an offset and one with the
307 * actual data) or one message (just data)
308 */
309 if (nmsgs > 2 || nmsgs == 0) {
310 debug("%s: Only one or two messages are supported.", __func__);
311 return -1;
312 }
313
314 omsg = nmsgs == 1 ? &dummy : msg;
315 dmsg = nmsgs == 1 ? msg : msg + 1;
316
317 /* the address is expected to be a uint, not a array. */
318 address = omsg->buf[0];
319 for (i = 1; i < omsg->len; i++)
320 address = (address << 8) + omsg->buf[i];
321
322 if (dmsg->flags & I2C_M_RD)
323 return __i2c_read(dev->base, dmsg->addr, address,
324 omsg->len, dmsg->buf, dmsg->len);
325 else
326 return __i2c_write(dev->base, dmsg->addr, address,
327 omsg->len, dmsg->buf, dmsg->len);
328}
329
330static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
331{
Simon Glassc69cda22020-12-03 16:55:20 -0700332 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
Liam Beguind61c7ad2017-03-27 11:13:12 -0400333 return __i2c_set_bus_speed(dev->base, speed, dev->index);
334}
335
336static int lpc32xx_i2c_reset(struct udevice *bus)
337{
Simon Glassc69cda22020-12-03 16:55:20 -0700338 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
Liam Beguind61c7ad2017-03-27 11:13:12 -0400339
340 __i2c_init(dev->base, dev->speed, 0, dev->index);
341 return 0;
342}
343
344static const struct dm_i2c_ops lpc32xx_i2c_ops = {
345 .xfer = lpc32xx_i2c_xfer,
346 .probe_chip = lpc32xx_i2c_probe_chip,
347 .deblock = lpc32xx_i2c_reset,
348 .set_bus_speed = lpc32xx_i2c_set_bus_speed,
349};
350
Trevor Woerner103f2332021-06-10 22:37:07 -0400351static const struct udevice_id lpc32xx_i2c_ids[] = {
352 { .compatible = "nxp,pnx-i2c" },
353 { }
354};
355
Liam Beguind61c7ad2017-03-27 11:13:12 -0400356U_BOOT_DRIVER(i2c_lpc32xx) = {
Liam Beguind61c7ad2017-03-27 11:13:12 -0400357 .name = "i2c_lpc32xx",
Trevor Woerner103f2332021-06-10 22:37:07 -0400358 .id = UCLASS_I2C,
359 .of_match = lpc32xx_i2c_ids,
Liam Beguind61c7ad2017-03-27 11:13:12 -0400360 .probe = lpc32xx_i2c_probe,
361 .ops = &lpc32xx_i2c_ops,
362};
363#endif /* CONFIG_DM_I2C */