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Markus Klotzbuecherb02d0172006-07-12 08:48:24 +02001/*
2 * (C) Copyright 2006
3 * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
4 *
5 * Configuation settings for the SPC1920 board.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __H
24#define __CONFIG_H
25
26#define CONFIG_SPC1920 1 /* SPC1920 board */
27#define CONFIG_MPC885 1 /* MPC885 CPU */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xFFF00000
30
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020031#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
32#undef CONFIG_8xx_CONS_SMC2
33#undef CONFIG_8xx_CONS_NONE
34
35#define CONFIG_MII
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050036#define CONFIG_MII_INIT 1
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020037#undef CONFIG_ETHER_ON_FEC1
38#define CONFIG_ETHER_ON_FEC2
39#define FEC_ENET
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020040#define CONFIG_FEC2_PHY 1
41
42#define CONFIG_BAUDRATE 19200
43
44/* use PLD CLK4 instead of brg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_SPC1920_SMC1_CLK4
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020046
47#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
48#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
50#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020053
54#define CONFIG_BOARD_EARLY_INIT_F
Markus Klotzbuecher5921e532007-01-09 14:57:13 +010055#define CONFIG_LAST_STAGE_INIT
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020056
Markus Klotzbuecher5921e532007-01-09 14:57:13 +010057#if 0
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020058#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62
63#define CONFIG_ENV_OVERWRITE
64
65#define CONFIG_NFSBOOTCOMMAND \
66 "dhcp;" \
67 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
69 "bootm"
70
71#define CONFIG_BOOTCOMMAND \
72 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
73 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
74 "bootm fe080000"
75
76#undef CONFIG_BOOTARGS
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
80
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020081
Jon Loeliger46da1e92007-07-04 22:33:30 -050082/*
Jon Loeliger079a1362007-07-10 10:12:10 -050083 * BOOTP options
84 */
85#define CONFIG_BOOTP_BOOTFILESIZE
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_GATEWAY
88#define CONFIG_BOOTP_HOSTNAME
89
90
91/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050092 * Command line configuration.
93 */
94#include <config_cmd_default.h>
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +020095
Jon Loeliger46da1e92007-07-04 22:33:30 -050096#define CONFIG_CMD_ASKENV
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_ECHO
99#define CONFIG_CMD_IMMAP
100#define CONFIG_CMD_JFFS2
Wolfgang Denk1d9e31e2007-09-09 21:21:33 +0200101#define CONFIG_CMD_NET
Jon Loeliger46da1e92007-07-04 22:33:30 -0500102#define CONFIG_CMD_PING
103#define CONFIG_CMD_DHCP
104#define CONFIG_CMD_I2C
105#define CONFIG_CMD_MII
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200106
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
111#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
112#define CONFIG_SYS_HUSH_PARSER
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200113
Jon Loeliger46da1e92007-07-04 22:33:30 -0500114#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200116#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200118#endif
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LOAD_ADDR 0x00100000
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200129
130/*
131 * Low Level Configuration Settings
132 * (address mappings, register initial values, etc.)
133 * You should know what you are doing if you make changes here.
134 */
135
136/*-----------------------------------------------------------------------
137 * Internal Memory Mapped Register
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_IMMR 0xF0000000
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200140
141/*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM)
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200145#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200146#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200148
149/*-----------------------------------------------------------------------
150 * Start addresses for the final memory configuration
151 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
155#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200156
157/*
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization.
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200163
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200166
167#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200169#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200171#endif /* CONFIG_BZIP2 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200174
175/*
176 * Flash
177 */
178/*-----------------------------------------------------------------------
179 * Flash organisation
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_BASE 0xFE000000
182#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200183#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200186
187/* Environment is in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200188#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200189#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200191
192#define CONFIG_ENV_OVERWRITE
193
194/*-----------------------------------------------------------------------
195 * Cache Configuration
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
198#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200199
Jon Loeliger079a1362007-07-10 10:12:10 -0500200#ifdef CONFIG_CMD_DATE
Markus Klotzbuecher0be62722007-01-09 14:57:12 +0100201# define CONFIG_RTC_DS3231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher0be62722007-01-09 14:57:12 +0100203#endif
204
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200205/*-----------------------------------------------------------------------
206 * I2C configuration
207 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500208#if defined(CONFIG_CMD_I2C)
Markus Klotzbuecher3f34f862007-01-09 14:57:10 +0100209/* enable I2C and select the hardware/software driver */
210#undef CONFIG_HARD_I2C /* I2C with hardware support */
211#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
214#define CONFIG_SYS_I2C_SLAVE 0xFE
Markus Klotzbuecher3f34f862007-01-09 14:57:10 +0100215
216#ifdef CONFIG_SOFT_I2C
217/*
218 * Software (bit-bang) I2C driver configuration
219 */
220#define PB_SCL 0x00000020 /* PB 26 */
221#define PB_SDA 0x00000010 /* PB 27 */
222
223#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
224#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
225#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
226#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
227#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
Markus Klotzbuecherd8d9de12007-01-09 14:57:10 +0100228 else immr->im_cpm.cp_pbdat &= ~PB_SDA
Markus Klotzbuecher3f34f862007-01-09 14:57:10 +0100229#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
Markus Klotzbuecherd8d9de12007-01-09 14:57:10 +0100230 else immr->im_cpm.cp_pbdat &= ~PB_SCL
Markus Klotzbuecher3f34f862007-01-09 14:57:10 +0100231#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
232#endif /* CONFIG_SOFT_I2C */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200233#endif
234
235/*-----------------------------------------------------------------------
236 * SYPCR - System Protection Control 11-9
237 * SYPCR can only be written once after reset!
238 *-----------------------------------------------------------------------
239 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
240 */
241#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200243 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
244#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200246#endif
247
248/*-----------------------------------------------------------------------
249 * SIUMCR - SIU Module Configuration 11-6
250 *-----------------------------------------------------------------------
251 * PCMCIA config., multi-function pin tri-state
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_SIUMCR (SIUMCR_FRC)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200254
255/*-----------------------------------------------------------------------
256 * TBSCR - Time Base Status and Control 11-26
257 *-----------------------------------------------------------------------
258 * Clear Reference Interrupt Status, Timebase freezing enabled
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200261
262/*-----------------------------------------------------------------------
263 * PISCR - Periodic Interrupt Status and Control 11-31
264 *-----------------------------------------------------------------------
265 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200268
269/*-----------------------------------------------------------------------
270 * SCCR - System Clock and reset Control Register 15-27
271 *-----------------------------------------------------------------------
272 * Set clock output, timebase and RTC source and divider,
273 * power management and some other internal clocks
274 */
275#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276/* #define CONFIG_SYS_SCCR SCCR_TBS */
277#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200278 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
279 SCCR_DFALCD00)
280
281/*-----------------------------------------------------------------------
282 * DER - Debug Enable Register
283 *-----------------------------------------------------------------------
284 * Set to zero to prevent the processor from entering debug mode
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_DER 0
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200287
288
289/* Because of the way the 860 starts up and assigns CS0 the entire
290 * address space, we have to set the memory controller differently.
291 * Normally, you write the option register first, and then enable the
292 * chip select by writing the base register. For CS0, you must write
293 * the base register first, followed by the option register.
294 */
295
296
297/*
298 * Init Memory Controller:
299 */
300
301/* BR0 and OR0 (FLASH) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200303
304
305/* used to re-map FLASH both when starting from SRAM or FLASH:
306 * restrict access enough to keep SRAM working (if any)
307 * but not too much to meddle with FLASH accesses
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
310#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200311
312/*
313 * FLASH timing:
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
Markus Klotzbuecher8fc21022007-01-09 14:57:14 +0100316 OR_SCY_6_CLK | OR_EHTR | OR_BI)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
319#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
320#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200321
322
323/*
324 * SDRAM CS1 UPMB
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_SDRAM_BASE 0x00000000
327#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200328#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000
331/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200332#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
335#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
338/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
341#define CONFIG_SYS_PTA_PER_CLK 195
342#define CONFIG_SYS_MBMR_PTB 195
343#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
344#define CONFIG_SYS_MAR 0x88
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200347 MBMR_AMB_TYPE_0 | \
348 MBMR_G0CLB_A10 | \
349 MBMR_DSB_1_CYCL | \
350 MBMR_RLFB_1X | \
351 MBMR_WLFB_1X | \
352 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200355 MBMR_AMB_TYPE_1 | \
356 MBMR_G0CLB_A10 | \
357 MBMR_DSB_1_CYCL | \
358 MBMR_RLFB_1X | \
359 MBMR_WLFB_1X | \
360 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
361
362
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100363/*
364 * DSP Host Port Interface CS3
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000
367#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100370 OR_G5LS | \
371 OR_SCY_0_CLK | \
372 OR_BI)
373
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100375 BR_MS_UPMA | \
376 BR_PS_16 | \
Selvamuthukumar03e2dbb2008-10-08 18:12:20 -0500377 BR_V)
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100380 MAMR_RLFA_5X | \
381 MAMR_WLFA_5X)
382
383#define CONFIG_SPC1920_HPI_TEST
384
385#ifdef CONFIG_SPC1920_HPI_TEST
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100387#define HPI_HPIC_1 HPI_REG(0)
388#define HPI_HPIC_2 HPI_REG(2)
Markus Klotzbuecher38ccd2f2007-01-09 14:57:13 +0100389#define HPI_HPIA_1 HPI_REG(0x2000008)
390#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
391#define HPI_HPID_INC_1 HPI_REG(0x1000004)
392#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
393#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
394#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
Markus Klotzbuecherd28707d2007-01-09 14:57:10 +0100395#endif /* CONFIG_SPC1920_HPI_TEST */
396
Markus Klotzbuecherd8d9de12007-01-09 14:57:10 +0100397/*
Markus Klotzbuecher9295acb2007-01-09 14:57:13 +0100398 * Ramtron FM18L08 FRAM 32KB on CS4
399 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000
401#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000
402#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \
Markus Klotzbuecher9295acb2007-01-09 14:57:13 +0100403 OR_ACS_DIV2 | \
404 OR_BI | \
405 OR_SCY_4_CLK | \
406 OR_TRLX)
407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
Markus Klotzbuecher9295acb2007-01-09 14:57:13 +0100409
410/*
Markus Klotzbuecher5921e532007-01-09 14:57:13 +0100411 * PLD CS5
Markus Klotzbuecherd8d9de12007-01-09 14:57:10 +0100412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000
414#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200417 OR_CSNT_SAM | \
418 OR_ACS_DIV1 | \
419 OR_BI | \
420 OR_SCY_0_CLK | \
421 OR_TRLX)
422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200424
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200425#endif /* __CONFIG_H */