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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fc358b1a760228a61388ac3c17b3850ac8f914dd / . / include / configs / sama5d3_xplained.h
blob: 4b13a101170faa812cb86e201e2cdcfa56c12a32 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D3 Xplained board.
4 *
5 * Copyright (C) 2014 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Fabien Lehousseldf1cf772020-02-24 16:45:31 +0100[diff] [blame]12#include <linux/sizes.h>
Wu, Joshb2d387b2015-03-30 14:51:19 +0800[diff] [blame]13#include "at91-sama5_common.h"
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]14
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]15/*
16 * This needs to be defined for the OHCI code to work but it is defined as
17 * ATMEL_ID_UHPHS in the CPU specific header files.
18 */
Wenyou Yange61ed482017-09-14 11:07:42 +0800[diff] [blame]19#define ATMEL_ID_UHP 32
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]20
21/*
22 * Specify the clock enable bit in the PMC_SCER register.
23 */
Wenyou Yange61ed482017-09-14 11:07:42 +0800[diff] [blame]24#define ATMEL_PMC_UHP (1 << 6)
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]25
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]26/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -0500[diff] [blame]27#define CFG_SYS_SDRAM_BASE 0x20000000
28#define CFG_SYS_SDRAM_SIZE 0x10000000
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]29
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]30/* NAND flash */
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]31#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]32#define CFG_SYS_NAND_BASE 0x60000000
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]33/* our ALE is AD21 */
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]34#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]35/* our CLE is AD22 */
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]36#define CFG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rini8f1a80e2017-07-28 21:31:42 -0400[diff] [blame]37#endif
Bo Shen7ca6f362014-02-09 15:52:39 +0800[diff] [blame]38
Bo Shencd23aac42014-03-19 14:48:45 +0800[diff] [blame]39/* SPL */
Bo Shencd23aac42014-03-19 14:48:45 +0800[diff] [blame]40
Fabien Lehousseldf1cf772020-02-24 16:45:31 +0100[diff] [blame]41/* size of u-boot.bin to load */
Bo Shencd23aac42014-03-19 14:48:45 +0800[diff] [blame]42
Michael Opdenackerea83ea52021-05-31 23:23:48 +0200[diff] [blame]43/* Falcon boot support on raw MMC */
Michael Opdenackerea83ea52021-05-31 23:23:48 +0200[diff] [blame]44/* U-Boot proper stored by default at 0x200 (256 KiB) */
Michael Opdenackerea83ea52021-05-31 23:23:48 +0200[diff] [blame]45
Bo Shencd23aac42014-03-19 14:48:45 +0800[diff] [blame]46#endif