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TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M5329EVB_H
31#define _M5329EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF532x /* define processor family */
38#define CONFIG_M5329 /* define processor type */
39
TsiChungLiew9998bd32007-08-05 03:19:10 -050040#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew8e585f02007-06-18 13:50:13 -050042#define CONFIG_BAUDRATE 115200
TsiChung Liew8e585f02007-06-18 13:50:13 -050043
44#undef CONFIG_WATCHDOG
45#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
46
TsiChungLiewab77bc52007-08-15 15:39:17 -050047/* Command line configuration */
48#include <config_cmd_default.h>
49
50#define CONFIG_CMD_CACHE
51#define CONFIG_CMD_DATE
52#define CONFIG_CMD_ELF
53#define CONFIG_CMD_FLASH
54#define CONFIG_CMD_I2C
55#define CONFIG_CMD_MEMORY
56#define CONFIG_CMD_MISC
57#define CONFIG_CMD_MII
58#define CONFIG_CMD_NET
59#define CONFIG_CMD_PING
60#define CONFIG_CMD_REGINFO
TsiChung0dca8742007-07-10 15:45:43 -050061
stany MARCEL96d94382011-10-19 00:17:13 +080062#ifdef CONFIG_NANDFLASH_SIZE
TsiChungLiewab77bc52007-08-15 15:39:17 -050063# define CONFIG_CMD_NAND
TsiChungLiew1a33ce62007-08-05 04:31:18 -050064#endif
65
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_UNIFY_CACHE
TsiChung Liew8e585f02007-06-18 13:50:13 -050067
68#define CONFIG_MCFFEC
69#ifdef CONFIG_MCFFEC
TsiChung Liew8e585f02007-06-18 13:50:13 -050070# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050071# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072# define CONFIG_SYS_DISCOVER_PHY
73# define CONFIG_SYS_RX_ETH_BUFFER 8
74# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew8e585f02007-06-18 13:50:13 -050075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076# define CONFIG_SYS_FEC0_PINMUX 0
77# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020078# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
80# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liew8e585f02007-06-18 13:50:13 -050081# define FECDUPLEX FULL
82# define FECSPEED _100BASET
83# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
85# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew8e585f02007-06-18 13:50:13 -050086# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liew8e585f02007-06-18 13:50:13 -050088#endif
89
TsiChung Liew8e585f02007-06-18 13:50:13 -050090#define CONFIG_MCFRTC
TsiChungLiew48dbfea2007-07-05 22:39:07 -050091#undef RTC_DEBUG
TsiChung Liew8e585f02007-06-18 13:50:13 -050092
93/* Timer */
94#define CONFIG_MCFTMR
TsiChung Liew8e585f02007-06-18 13:50:13 -050095#undef CONFIG_MCFPIT
TsiChung Liew8e585f02007-06-18 13:50:13 -050096
TsiChungLieweaf9e442007-08-05 04:11:20 -050097/* I2C */
98#define CONFIG_FSL_I2C
99#define CONFIG_HARD_I2C /* I2C with hw support */
100#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_I2C_SPEED 80000
102#define CONFIG_SYS_I2C_SLAVE 0x7F
103#define CONFIG_SYS_I2C_OFFSET 0x58000
104#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLieweaf9e442007-08-05 04:11:20 -0500105
TsiChung Liew8e585f02007-06-18 13:50:13 -0500106#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
TsiChungLiewab77bc52007-08-15 15:39:17 -0500107#define CONFIG_UDP_CHECKSUM
108
TsiChung Liew8e585f02007-06-18 13:50:13 -0500109#ifdef CONFIG_MCFFEC
TsiChungLieweaf9e442007-08-05 04:11:20 -0500110# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
111# define CONFIG_IPADDR 192.162.1.2
112# define CONFIG_NETMASK 255.255.255.0
113# define CONFIG_SERVERIP 192.162.1.1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500114# define CONFIG_GATEWAYIP 192.162.1.1
115# define CONFIG_OVERWRITE_ETHADDR_ONCE
116#endif /* FEC_ENET */
117
118#define CONFIG_HOSTNAME M5329EVB
119#define CONFIG_EXTRA_ENV_SETTINGS \
120 "netdev=eth0\0" \
121 "loadaddr=40010000\0" \
122 "u-boot=u-boot.bin\0" \
123 "load=tftp ${loadaddr) ${u-boot}\0" \
124 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +0800125 "prog=prot off 0 3ffff;" \
126 "era 0 3ffff;" \
TsiChung Liew8e585f02007-06-18 13:50:13 -0500127 "cp.b ${loadaddr} 0 ${filesize};" \
128 "save\0" \
129 ""
130
TsiChungLieweaf9e442007-08-05 04:11:20 -0500131#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_PROMPT "-> "
133#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500134
TsiChungLiewab77bc52007-08-15 15:39:17 -0500135#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500137#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500139#endif
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
142#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
144#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_HZ 1000
147#define CONFIG_SYS_CLK 80000000
148#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChung Liew8e585f02007-06-18 13:50:13 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiew1a33ce62007-08-05 04:31:18 -0500153
TsiChung Liew8e585f02007-06-18 13:50:13 -0500154/*
155 * Low Level Configuration Settings
156 * (address mappings, register initial values, etc.)
157 * You should know what you are doing if you make changes here.
158 */
159/*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200163#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200165#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liew8e585f02007-06-18 13:50:13 -0500167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SDRAM_BASE 0x40000000
174#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
175#define CONFIG_SYS_SDRAM_CFG1 0x53722730
176#define CONFIG_SYS_SDRAM_CFG2 0x56670000
177#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
178#define CONFIG_SYS_SDRAM_EMOD 0x40010000
179#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liew8e585f02007-06-18 13:50:13 -0500180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
182#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
185#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
188#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500189
190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization ??
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000196#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500197
198/*-----------------------------------------------------------------------
199 * FLASH organization
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_CFI
202#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200203# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
205# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
206# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
207# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
208# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500209#endif
210
stany MARCEL96d94382011-10-19 00:17:13 +0800211#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212# define CONFIG_SYS_MAX_NAND_DEVICE 1
213# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
214# define CONFIG_SYS_NAND_SIZE 1
215# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewab77bc52007-08-15 15:39:17 -0500216# define NAND_ALLOW_ERASE_ALL 1
217# define CONFIG_JFFS2_NAND 1
218# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewab77bc52007-08-15 15:39:17 -0500220# define CONFIG_JFFS2_PART_OFFSET 0x00000000
TsiChungLiew1a33ce62007-08-05 04:31:18 -0500221#endif
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -0500224
225/* Configuration for environment
226 * Environment is embedded in u-boot in the second sector of the flash
227 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200228#define CONFIG_ENV_OFFSET 0x4000
229#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200230#define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew8e585f02007-06-18 13:50:13 -0500236
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600237#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200238 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600239#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200240 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600241#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
242#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
243 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
244 CF_ACR_EN | CF_ACR_SM_ALL)
245#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
246 CF_CACR_DCM_P)
247
TsiChung Liew8e585f02007-06-18 13:50:13 -0500248/*-----------------------------------------------------------------------
249 * Chipselect bank definitions
250 */
251/*
252 * CS0 - NOR Flash 1, 2, 4, or 8MB
253 * CS1 - CompactFlash and registers
254 * CS2 - NAND Flash 16, 32, or 64MB
255 * CS3 - Available
256 * CS4 - Available
257 * CS5 - Available
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CS0_BASE 0
260#define CONFIG_SYS_CS0_MASK 0x007f0001
261#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_CS1_BASE 0x10000000
264#define CONFIG_SYS_CS1_MASK 0x001f0001
265#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChung Liew8e585f02007-06-18 13:50:13 -0500266
stany MARCEL96d94382011-10-19 00:17:13 +0800267#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_CS2_BASE 0x20000000
stany MARCEL96d94382011-10-19 00:17:13 +0800269#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChung Liew8e585f02007-06-18 13:50:13 -0500271#endif
272
TsiChung Liew8e585f02007-06-18 13:50:13 -0500273#endif /* _M5329EVB_H */