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wdenk2cbe5712004-10-10 17:05:18 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * 2004-2005 Gary Jennejohn <garyj@denx.de>
wdenk2cbe5712004-10-10 17:05:18 +00003 *
wdenk9d5028c2004-11-21 00:06:33 +00004 * Configuration settings for the CMC PU2 board.
wdenk2cbe5712004-10-10 17:05:18 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk45ea3fc2004-12-14 23:28:24 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk2cbe5712004-10-10 17:05:18 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
wdenk2cbe5712004-10-10 17:05:18 +000028/* ARM asynchronous clock */
Wolfgang Denkdf3c7c82005-08-19 00:36:45 +020029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
wdenk101e8df2005-04-04 12:08:28 +000030#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
wdenk2cbe5712004-10-10 17:05:18 +000031
32#define AT91_SLOW_CLOCK 32768 /* slow clock */
33
wdenka85f9f22005-04-06 13:52:31 +000034#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
35#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
wdenka85f9f22005-04-06 13:52:31 +000036#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38#define USE_920T_MMU 1
39
wdenk2cbe5712004-10-10 17:05:18 +000040#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS 1
42#define CONFIG_INITRD_TAG 1
43
wdenk8aa1a2d2005-04-04 12:44:11 +000044#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkef2807c2005-03-31 23:44:33 +000045#define CFG_USE_MAIN_OSCILLATOR 1
46/* flash */
47#define MC_PUIA_VAL 0x00000000
48#define MC_PUP_VAL 0x00000000
49#define MC_PUER_VAL 0x00000000
50#define MC_ASR_VAL 0x00000000
51#define MC_AASR_VAL 0x00000000
52#define EBI_CFGR_VAL 0x00000000
53#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
54
55/* clocks */
Wolfgang Denkdf3c7c82005-08-19 00:36:45 +020056#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
wdenkef2807c2005-03-31 23:44:33 +000057#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
58#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
59
60/* sdram */
61#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
62#define PIOC_BSR_VAL 0x00000000
63#define PIOC_PDR_VAL 0xFFFF0000
64#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
65#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
66#define SDRAM 0x20000000 /* address of the SDRAM */
67#define SDRAM1 0x20000080 /* address of the SDRAM */
68#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
69#define SDRC_MR_VAL 0x00000002 /* Precharge All */
70#define SDRC_MR_VAL1 0x00000004 /* refresh */
71#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
72#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
73#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
wdenk8aa1a2d2005-04-04 12:44:11 +000074#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkef2807c2005-03-31 23:44:33 +000075
wdenk2cbe5712004-10-10 17:05:18 +000076/*
77 * Size of malloc() pool
78 */
79#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
80#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81
wdenk45ea3fc2004-12-14 23:28:24 +000082#define CONFIG_BAUDRATE 9600
wdenk2cbe5712004-10-10 17:05:18 +000083
wdenk2cbe5712004-10-10 17:05:18 +000084/*
85 * Hardware drivers
86 */
87
88/* define one of these to choose the DBGU, USART0 or USART1 as console */
89#undef CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000090#define CONFIG_USART0
91#undef CONFIG_USART1
wdenk2cbe5712004-10-10 17:05:18 +000092
93#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
94
95#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
96
wdenk9d5028c2004-11-21 00:06:33 +000097#define CONFIG_HARD_I2C
wdenk2cbe5712004-10-10 17:05:18 +000098
99#ifdef CONFIG_HARD_I2C
wdenk45ea3fc2004-12-14 23:28:24 +0000100#define CFG_I2C_SPEED 0 /* not used */
101#define CFG_I2C_SLAVE 0 /* not used */
102#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
103#define CFG_I2C_RTC_ADDR 0x32
104#define CFG_I2C_EEPROM_ADDR 0x50
wdenk2cbe5712004-10-10 17:05:18 +0000105#define CFG_I2C_EEPROM_ADDR_LEN 1
106#define CFG_I2C_EEPROM_ADDR_OVERFLOW
107#endif
wdenked54e622004-11-24 23:35:19 +0000108/* still about 20 kB free with this defined */
109#define CFG_LONGHELP
wdenk2cbe5712004-10-10 17:05:18 +0000110
111#define CONFIG_BOOTDELAY 3
wdenk2cbe5712004-10-10 17:05:18 +0000112
113#ifdef CONFIG_HARD_I2C
114#define CONFIG_COMMANDS \
wdenk45ea3fc2004-12-14 23:28:24 +0000115 ((CONFIG_CMD_DFL | \
wdenk45ea3fc2004-12-14 23:28:24 +0000116 CFG_CMD_DATE | \
wdenk414eec32005-04-02 22:37:54 +0000117 CFG_CMD_DHCP | \
wdenk45ea3fc2004-12-14 23:28:24 +0000118 CFG_CMD_EEPROM | \
wdenk414eec32005-04-02 22:37:54 +0000119 CFG_CMD_I2C | \
120 CFG_CMD_NFS | \
121 CFG_CMD_SNTP ) & \
wdenk45ea3fc2004-12-14 23:28:24 +0000122 ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
wdenk2cbe5712004-10-10 17:05:18 +0000123#else
124#define CONFIG_COMMANDS \
wdenk45ea3fc2004-12-14 23:28:24 +0000125 ((CONFIG_CMD_DFL | \
wdenk414eec32005-04-02 22:37:54 +0000126 CFG_CMD_DHCP | \
127 CFG_CMD_NFS | \
128 CFG_CMD_SNTP ) & \
wdenk45ea3fc2004-12-14 23:28:24 +0000129 ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
130#define CONFIG_TIMESTAMP
wdenk2cbe5712004-10-10 17:05:18 +0000131#endif
wdenked54e622004-11-24 23:35:19 +0000132#define CFG_LONGHELP
wdenk2cbe5712004-10-10 17:05:18 +0000133
134/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
135#include <cmd_confdefs.h>
136
wdenk45ea3fc2004-12-14 23:28:24 +0000137#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
138#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
wdenk2cbe5712004-10-10 17:05:18 +0000139
wdenk45ea3fc2004-12-14 23:28:24 +0000140#define CONFIG_NR_DRAM_BANKS 1
141#define PHYS_SDRAM 0x20000000
142#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
wdenk2cbe5712004-10-10 17:05:18 +0000143
wdenk3dd7f0f2005-04-04 23:43:44 +0000144#define CFG_MEMTEST_START PHYS_SDRAM
145#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenk2cbe5712004-10-10 17:05:18 +0000146
147#define CONFIG_DRIVER_ETHER
148#define CONFIG_NET_RETRY_COUNT 20
149#define CONFIG_AT91C_USE_RMII
150
wdenk2cbe5712004-10-10 17:05:18 +0000151#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
wdenk45ea3fc2004-12-14 23:28:24 +0000152#define CFG_MAX_DATAFLASH_BANKS 2
153#define CFG_MAX_DATAFLASH_PAGES 16384
wdenk2cbe5712004-10-10 17:05:18 +0000154#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
155#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
156
157#define PHYS_FLASH_1 0x10000000
wdenk9d5028c2004-11-21 00:06:33 +0000158#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
wdenk2cbe5712004-10-10 17:05:18 +0000159#define CFG_FLASH_BASE PHYS_FLASH_1
wdenk45ea3fc2004-12-14 23:28:24 +0000160#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenk2cbe5712004-10-10 17:05:18 +0000161#define CFG_MAX_FLASH_BANKS 1
162#define CFG_MAX_FLASH_SECT 256
wdenke6ba3c92005-04-01 09:29:14 +0000163#define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */
164#define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */
wdenk2cbe5712004-10-10 17:05:18 +0000165
wdenk2cbe5712004-10-10 17:05:18 +0000166#define CFG_ENV_IS_IN_FLASH 1
wdenk45ea3fc2004-12-14 23:28:24 +0000167#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
168#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
169#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */
wdenk2cbe5712004-10-10 17:05:18 +0000170
171#define CFG_LOAD_ADDR 0x21000000 /* default load address */
172
wdenk45ea3fc2004-12-14 23:28:24 +0000173#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
wdenk2cbe5712004-10-10 17:05:18 +0000174
wdenk45ea3fc2004-12-14 23:28:24 +0000175#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenk2cbe5712004-10-10 17:05:18 +0000176#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk45ea3fc2004-12-14 23:28:24 +0000177#define CFG_MAXARGS 32 /* max number of command args */
wdenk2cbe5712004-10-10 17:05:18 +0000178#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
179
180#ifndef __ASSEMBLY__
181/*-----------------------------------------------------------------------
182 * Board specific extension for bd_info
183 *
184 * This structure is embedded in the global bd_info (bd_t) structure
185 * and can be used by the board specific code (eg board/...)
186 */
187
188struct bd_info_ext {
189 /* helper variable for board environment handling
190 *
wdenk45ea3fc2004-12-14 23:28:24 +0000191 * env_crc_valid == 0 => uninitialised
192 * env_crc_valid > 0 => environment crc in flash is valid
193 * env_crc_valid < 0 => environment crc in flash is invalid
wdenk2cbe5712004-10-10 17:05:18 +0000194 */
195 int env_crc_valid;
196};
wdenk45ea3fc2004-12-14 23:28:24 +0000197#endif /* __ASSEMBLY__ */
wdenk2cbe5712004-10-10 17:05:18 +0000198
wdenk9455b7f2004-10-11 22:25:49 +0000199#define CFG_HZ 1000
wdenk101e8df2005-04-04 12:08:28 +0000200#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
wdenk59acc292005-04-03 14:18:51 +0000201 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenk2cbe5712004-10-10 17:05:18 +0000202
203#define CONFIG_STACKSIZE (32*1024) /* regular stack */
204
205#ifdef CONFIG_USE_IRQ
206#error CONFIG_USE_IRQ not supported
207#endif
208
wdenk3dd7f0f2005-04-04 23:43:44 +0000209#define CFG_DEVICE_NULLDEV 1 /* enble null device */
210#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
211
212#define CONFIG_AUTOBOOT_KEYED
213#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
214#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */
215
216#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
217
218#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100219 "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
wdenk3dd7f0f2005-04-04 23:43:44 +0000220 "addmtd;bootm\0" \
221 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100222 "nfsroot=${serverip}:${rootpath}\0" \
223 "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
wdenk3dd7f0f2005-04-04 23:43:44 +0000224 "addcons addmtd; bootm\0" \
225 "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
226 "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100227 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
228 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
229 "${hostname}::off\0" \
230 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
231 "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
wdenk3dd7f0f2005-04-04 23:43:44 +0000232 "64k(environment),768k(linux),4096k(root),-\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100233 "load=tftp ${loadaddr} ${loadfile}\0" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000234 "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100235 "cp.b ${loadaddr} 10000000 ${filesize};" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000236 "protect on 10000000 1001ffff\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100237 "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
238 "cp.b ${loadaddr} 10030000 ${filesize}\0" \
239 "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
240 "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
241 "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
242 "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
wdenk3dd7f0f2005-04-04 23:43:44 +0000243 "cramfsimage=cramfs_cmc-pu2.img\0" \
244 "jffsimage=jffs2_cmc-pu2.img\0" \
245 "loadfile=u-boot_cmc-pu2.bin\0" \
246 "bootfile=uImage_cmc-pu2\0" \
247 "loadaddr=0x20800000\0" \
248 "hostname=CMC-TC-PU2\0" \
249 "bootcmd=run dhcp_start;run flash_cramfs\0" \
250 "autoload=n\0" \
251 "dhcp_start=echo no DHCP\0" \
252 "ipaddr=192.168.0.190\0"
wdenk45ea3fc2004-12-14 23:28:24 +0000253#endif /* __CONFIG_H */