blob: 7c79e7b73a75727fb483b441ac2a8958546d365b [file] [log] [blame]
HeungJun, Kim89f95492012-01-16 21:13:05 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
Donghwa Lee51b1cd62012-04-05 19:36:27 +00005 * Donghwa Lee <dh09.lee@samsung.com>
HeungJun, Kim89f95492012-01-16 21:13:05 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
HeungJun, Kim89f95492012-01-16 21:13:05 +00008 */
9
10#include <common.h>
Donghwa Lee51b1cd62012-04-05 19:36:27 +000011#include <lcd.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000012#include <asm/io.h>
13#include <asm/arch/cpu.h>
14#include <asm/arch/gpio.h>
Piotr Wilczekd651e882012-09-20 00:19:58 +000015#include <asm/arch/pinmux.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000016#include <asm/arch/clock.h>
Donghwa Lee51b1cd62012-04-05 19:36:27 +000017#include <asm/arch/mipi_dsim.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000018#include <asm/arch/watchdog.h>
19#include <asm/arch/power.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000020#include <power/pmic.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000021#include <usb/s3c_udc.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000022#include <power/max8997_pmic.h>
Łukasz Majewski7dcda992012-11-13 03:22:06 +000023#include <power/max8997_muic.h>
Łukasz Majewski61365ff2012-11-13 03:22:08 +000024#include <power/battery.h>
Łukasz Majewski5a773582012-11-13 03:22:07 +000025#include <power/max17042_fg.h>
Piotr Wilczekfe601642014-03-07 14:59:48 +010026#include <libtizen.h>
Mateusz Zalega16297cf2013-10-04 19:22:26 +020027#include <usb.h>
Lukasz Majewski83301b42013-03-05 12:10:18 +010028#include <usb_mass_storage.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000029
30#include "setup.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
34unsigned int board_rev;
35
36#ifdef CONFIG_REVISION_TAG
37u32 get_board_rev(void)
38{
39 return board_rev;
40}
41#endif
42
43static void check_hw_revision(void);
Lukasz Majewskia241d6e2012-08-06 14:41:10 +020044struct s3c_plat_otg_data s5pc210_otg_data;
45
Piotr Wilczekfe601642014-03-07 14:59:48 +010046int exynos_init(void)
HeungJun, Kim89f95492012-01-16 21:13:05 +000047{
HeungJun, Kim89f95492012-01-16 21:13:05 +000048 check_hw_revision();
49 printf("HW Revision:\t0x%x\n", board_rev);
50
HeungJun, Kim89f95492012-01-16 21:13:05 +000051 return 0;
52}
53
Łukasz Majewskifd8dca82012-09-04 23:15:21 +000054void i2c_init_board(void)
55{
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010056 int err;
Łukasz Majewskifd8dca82012-09-04 23:15:21 +000057 struct exynos4_gpio_part2 *gpio2 =
58 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
59
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010060 /* I2C_5 -> PMIC */
61 err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
62 if (err) {
63 debug("I2C%d not configured\n", (I2C_5));
64 return;
65 }
66
67 /* I2C_8 -> FG */
Łukasz Majewskifd8dca82012-09-04 23:15:21 +000068 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
69 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
70}
71
Łukasz Majewski69ad72a2012-11-13 03:22:10 +000072static void trats_low_power_mode(void)
73{
74 struct exynos4_clock *clk =
75 (struct exynos4_clock *)samsung_get_base_clock();
76 struct exynos4_power *pwr =
77 (struct exynos4_power *)samsung_get_base_power();
78
79 /* Power down CORE1 */
80 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
81 writel(0x0, &pwr->arm_core1_configuration);
82
83 /* Change the APLL frequency */
84 /* ENABLE (1 enable) | LOCKED (1 locked) */
85 /* [31] | [29] */
86 /* FSEL | MDIV | PDIV | SDIV */
87 /* [27] | [25:16] | [13:8] | [2:0] */
88 writel(0xa0c80604, &clk->apll_con0);
89
90 /* Change CPU0 clock divider */
91 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
92 /* [30:28] | [26:24] | [22:20] | [18:16] */
93 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
94 /* [14:12] | [10:8] | [6:4] | [2:0] */
95 writel(0x00000100, &clk->div_cpu0);
96
97 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
98 while (readl(&clk->div_stat_cpu0) & 0x1111111)
99 continue;
100
101 /* Change clock divider ratio for DMC */
102 /* DMCP_RATIO | DMCD_RATIO */
103 /* [22:20] | [18:16] */
104 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
105 /* [14:12] | [10:8] | [6:4] | [2:0] */
106 writel(0x13113117, &clk->div_dmc0);
107
108 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
109 while (readl(&clk->div_stat_dmc0) & 0x11111111)
110 continue;
111
112 /* Turn off unnecessary power domains */
113 writel(0x0, &pwr->xxti_configuration); /* XXTI */
114 writel(0x0, &pwr->cam_configuration); /* CAM */
115 writel(0x0, &pwr->tv_configuration); /* TV */
116 writel(0x0, &pwr->mfc_configuration); /* MFC */
117 writel(0x0, &pwr->g3d_configuration); /* G3D */
118 writel(0x0, &pwr->gps_configuration); /* GPS */
119 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
120
121 /* Turn off unnecessary clocks */
122 writel(0x0, &clk->gate_ip_cam); /* CAM */
123 writel(0x0, &clk->gate_ip_tv); /* TV */
124 writel(0x0, &clk->gate_ip_mfc); /* MFC */
125 writel(0x0, &clk->gate_ip_g3d); /* G3D */
126 writel(0x0, &clk->gate_ip_image); /* IMAGE */
127 writel(0x0, &clk->gate_ip_gps); /* GPS */
128}
129
Łukasz Majewskia52a7b12012-11-13 03:22:05 +0000130static int pmic_init_max8997(void)
131{
132 struct pmic *p = pmic_get("MAX8997_PMIC");
133 int i = 0, ret = 0;
134 u32 val;
135
136 if (pmic_probe(p))
137 return -1;
138
139 /* BUCK1 VARM: 1.2V */
140 val = (1200000 - 650000) / 25000;
141 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
142 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
143 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
144
145 /* BUCK2 VINT: 1.1V */
146 val = (1100000 - 650000) / 25000;
147 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
148 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
149 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
150
151
152 /* BUCK3 G3D: 1.1V - OFF */
153 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
154 val &= ~ENBUCK;
155 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
156
157 val = (1100000 - 750000) / 50000;
158 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
159
160 /* BUCK4 CAMISP: 1.2V - OFF */
161 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
162 val &= ~ENBUCK;
163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
164
165 val = (1200000 - 650000) / 25000;
166 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
167
168 /* BUCK5 VMEM: 1.2V */
169 val = (1200000 - 650000) / 25000;
170 for (i = 0; i < 8; i++)
171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
172
173 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
174 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
175
176 /* BUCK6 CAM AF: 2.8V */
177 /* No Voltage Setting Register */
178 /* GNSLCT 3.0X */
179 val = GNSLCT;
180 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
181
182 /* BUCK7 VCC_SUB: 2.0V */
183 val = (2000000 - 750000) / 50000;
184 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
185
186 /* LDO1 VADC: 3.3V */
187 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
188 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
189
190 /* LDO1 Disable active discharging */
191 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
192 val &= ~LDO_ADE;
193 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
194
195 /* LDO2 VALIVE: 1.1V */
196 val = max8997_reg_ldo(1100000) | EN_LDO;
197 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
198
199 /* LDO3 VUSB/MIPI: 1.1V */
200 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
201 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
202
203 /* LDO4 VMIPI: 1.8V */
204 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
205 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
206
207 /* LDO5 VHSIC: 1.2V */
208 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
209 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
210
211 /* LDO6 VCC_1.8V_PDA: 1.8V */
212 val = max8997_reg_ldo(1800000) | EN_LDO;
213 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
214
215 /* LDO7 CAM_ISP: 1.8V */
216 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
217 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
218
219 /* LDO8 VDAC/VUSB: 3.3V */
220 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
221 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
222
223 /* LDO9 VCC_2.8V_PDA: 2.8V */
224 val = max8997_reg_ldo(2800000) | EN_LDO;
225 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
226
227 /* LDO10 VPLL: 1.1V */
228 val = max8997_reg_ldo(1100000) | EN_LDO;
229 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
230
231 /* LDO11 TOUCH: 2.8V */
232 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
233 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
234
235 /* LDO12 VTCAM: 1.8V */
236 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
237 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
238
239 /* LDO13 VCC_3.0_LCD: 3.0V */
240 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
241 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
242
243 /* LDO14 MOTOR: 3.0V */
244 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
245 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
246
247 /* LDO15 LED_A: 2.8V */
248 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
249 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
250
251 /* LDO16 CAM_SENSOR: 1.8V */
252 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
253 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
254
255 /* LDO17 VTF: 2.8V */
256 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
257 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
258
259 /* LDO18 TOUCH_LED 3.3V */
260 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
261 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
262
263 /* LDO21 VDDQ: 1.2V */
264 val = max8997_reg_ldo(1200000) | EN_LDO;
265 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
266
267 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
268 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
269 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
270 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
271
272 if (ret) {
273 puts("MAX8997 PMIC setting error!\n");
274 return -1;
275 }
276 return 0;
277}
278
Piotr Wilczekfe601642014-03-07 14:59:48 +0100279int exynos_power_init(void)
Łukasz Majewskid47ab982012-11-13 03:21:57 +0000280{
Łukasz Majewskibdee9c82012-11-13 03:22:11 +0000281 int chrg, ret;
282 struct power_battery *pb;
283 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
Łukasz Majewskid47ab982012-11-13 03:21:57 +0000284
Łukasz Majewski2936df12013-08-16 15:33:33 +0200285 /*
286 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
287 * to logical I2C adapter 0
288 *
289 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
290 * to logical I2C adapter 1
291 */
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +0100292 ret = pmic_init(I2C_5);
Łukasz Majewskia52a7b12012-11-13 03:22:05 +0000293 ret |= pmic_init_max8997();
Piotr Wilczekef23b992013-12-18 15:43:37 +0100294 ret |= power_fg_init(I2C_9);
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +0100295 ret |= power_muic_init(I2C_5);
Łukasz Majewski61365ff2012-11-13 03:22:08 +0000296 ret |= power_bat_init(0);
Łukasz Majewskid47ab982012-11-13 03:21:57 +0000297 if (ret)
298 return ret;
299
Łukasz Majewskibdee9c82012-11-13 03:22:11 +0000300 p_fg = pmic_get("MAX17042_FG");
301 if (!p_fg) {
302 puts("MAX17042_FG: Not found\n");
303 return -ENODEV;
304 }
305
306 p_chrg = pmic_get("MAX8997_PMIC");
307 if (!p_chrg) {
308 puts("MAX8997_PMIC: Not found\n");
309 return -ENODEV;
310 }
311
312 p_muic = pmic_get("MAX8997_MUIC");
313 if (!p_muic) {
314 puts("MAX8997_MUIC: Not found\n");
315 return -ENODEV;
316 }
317
318 p_bat = pmic_get("BAT_TRATS");
319 if (!p_bat) {
320 puts("BAT_TRATS: Not found\n");
321 return -ENODEV;
322 }
323
324 p_fg->parent = p_bat;
325 p_chrg->parent = p_bat;
326 p_muic->parent = p_bat;
327
328 p_bat->low_power_mode = trats_low_power_mode;
329 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
330
331 pb = p_bat->pbat;
332 chrg = p_muic->chrg->chrg_type(p_muic);
333 debug("CHARGER TYPE: %d\n", chrg);
334
335 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
336 puts("No battery detected\n");
337 return -1;
338 }
339
340 p_fg->fg->fg_battery_check(p_fg, p_bat);
341
342 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
343 puts("CHARGE Battery !\n");
344
Łukasz Majewskid47ab982012-11-13 03:21:57 +0000345 return 0;
346}
347
HeungJun, Kim89f95492012-01-16 21:13:05 +0000348static unsigned int get_hw_revision(void)
349{
350 struct exynos4_gpio_part1 *gpio =
351 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
352 int hwrev = 0;
353 int i;
354
355 /* hw_rev[3:0] == GPE1[3:0] */
356 for (i = 0; i < 4; i++) {
357 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
358 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
359 }
360
361 udelay(1);
362
363 for (i = 0; i < 4; i++)
364 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
365
366 debug("hwrev 0x%x\n", hwrev);
367
368 return hwrev;
369}
370
371static void check_hw_revision(void)
372{
373 int hwrev;
374
375 hwrev = get_hw_revision();
376
377 board_rev |= hwrev;
378}
379
HeungJun, Kim89f95492012-01-16 21:13:05 +0000380
381#ifdef CONFIG_USB_GADGET
382static int s5pc210_phy_control(int on)
383{
384 int ret = 0;
Łukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000385 u32 val = 0;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000386 struct pmic *p = pmic_get("MAX8997_PMIC");
387 if (!p)
388 return -ENODEV;
HeungJun, Kim89f95492012-01-16 21:13:05 +0000389
390 if (pmic_probe(p))
391 return -1;
392
393 if (on) {
Łukasz Majewski04ce68e2012-03-29 01:29:18 +0000394 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
395 ENSAFEOUT1, LDO_ON);
Łukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000396 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
397 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
398
399 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
400 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
HeungJun, Kim89f95492012-01-16 21:13:05 +0000401 } else {
Łukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000402 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
403 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
404
405 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
406 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
Łukasz Majewski04ce68e2012-03-29 01:29:18 +0000407 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
408 ENSAFEOUT1, LDO_OFF);
HeungJun, Kim89f95492012-01-16 21:13:05 +0000409 }
410
411 if (ret) {
Łukasz Majewski04ce68e2012-03-29 01:29:18 +0000412 puts("MAX8997 LDO setting error!\n");
HeungJun, Kim89f95492012-01-16 21:13:05 +0000413 return -1;
414 }
415
416 return 0;
417}
418
419struct s3c_plat_otg_data s5pc210_otg_data = {
420 .phy_control = s5pc210_phy_control,
421 .regs_phy = EXYNOS4_USBPHY_BASE,
422 .regs_otg = EXYNOS4_USBOTG_BASE,
423 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
424 .usb_flags = PHY0_SLEEP,
425};
Lukasz Majewskia241d6e2012-08-06 14:41:10 +0200426
Troy Kiskybba67912013-10-10 15:27:55 -0700427int board_usb_init(int index, enum usb_init_type init)
Lukasz Majewskia241d6e2012-08-06 14:41:10 +0200428{
429 debug("USB_udc_probe\n");
Mateusz Zalega16297cf2013-10-04 19:22:26 +0200430 return s3c_udc_probe(&s5pc210_otg_data);
Lukasz Majewskia241d6e2012-08-06 14:41:10 +0200431}
Przemyslaw Marczak0938f5b2013-12-02 13:54:01 +0100432
433#ifdef CONFIG_USB_CABLE_CHECK
434int usb_cable_connected(void)
435{
436 struct pmic *muic = pmic_get("MAX8997_MUIC");
437 if (!muic)
438 return 0;
439
440 return !!muic->chrg->chrg_type(muic);
441}
442#endif
HeungJun, Kim89f95492012-01-16 21:13:05 +0000443#endif
444
445static void pmic_reset(void)
446{
447 struct exynos4_gpio_part2 *gpio =
448 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
449
450 s5p_gpio_direction_output(&gpio->x0, 7, 1);
451 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
452}
453
454static void board_clock_init(void)
455{
456 struct exynos4_clock *clk =
457 (struct exynos4_clock *)samsung_get_base_clock();
458
459 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
460 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
461 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
462 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
463
464 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
465 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
466 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
467 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
468 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
469 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
470 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
471 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
472 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
473 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
474 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
475 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
476
477 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
478 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
479 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
480 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
481 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
482 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
483 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
484 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
485 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
486 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
487 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
488 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
489
490 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
491 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
492 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
493 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
494 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
495 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
496 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
497 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
498 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
499 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
500 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
501 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
502}
503
HeungJun, Kim89f95492012-01-16 21:13:05 +0000504static void board_power_init(void)
505{
506 struct exynos4_power *pwr =
507 (struct exynos4_power *)samsung_get_base_power();
508
509 /* PS HOLD */
510 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
511
512 /* Set power down */
513 writel(0, (unsigned int)&pwr->cam_configuration);
514 writel(0, (unsigned int)&pwr->tv_configuration);
515 writel(0, (unsigned int)&pwr->mfc_configuration);
516 writel(0, (unsigned int)&pwr->g3d_configuration);
517 writel(0, (unsigned int)&pwr->lcd1_configuration);
518 writel(0, (unsigned int)&pwr->gps_configuration);
519 writel(0, (unsigned int)&pwr->gps_alive_configuration);
Piotr Wilczekab233042012-10-08 20:45:42 +0000520
521 /* It is necessary to power down core 1 */
522 /* to successfully boot CPU1 in kernel */
523 writel(0, (unsigned int)&pwr->arm_core1_configuration);
HeungJun, Kim89f95492012-01-16 21:13:05 +0000524}
525
Piotr Wilczekfe601642014-03-07 14:59:48 +0100526static void exynos_uart_init(void)
HeungJun, Kim89f95492012-01-16 21:13:05 +0000527{
HeungJun, Kim89f95492012-01-16 21:13:05 +0000528 struct exynos4_gpio_part2 *gpio2 =
529 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
HeungJun, Kim89f95492012-01-16 21:13:05 +0000530
531 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
532 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
533 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
534}
535
Piotr Wilczekfe601642014-03-07 14:59:48 +0100536int exynos_early_init_f(void)
HeungJun, Kim89f95492012-01-16 21:13:05 +0000537{
Minkyu Kang85948a82012-01-18 15:56:47 +0900538 wdt_stop();
HeungJun, Kim89f95492012-01-16 21:13:05 +0000539 pmic_reset();
540 board_clock_init();
Piotr Wilczekfe601642014-03-07 14:59:48 +0100541 exynos_uart_init();
HeungJun, Kim89f95492012-01-16 21:13:05 +0000542 board_power_init();
543
544 return 0;
545}
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000546
Ajay Kumar29fd5702013-02-21 23:52:57 +0000547void exynos_reset_lcd(void)
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000548{
549 struct exynos4_gpio_part2 *gpio2 =
550 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
551
552 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
553 udelay(10000);
554 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
555 udelay(10000);
556 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
557}
558
Piotr Wilczekfe601642014-03-07 14:59:48 +0100559int lcd_power(void)
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000560{
561 int ret = 0;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000562 struct pmic *p = pmic_get("MAX8997_PMIC");
563 if (!p)
564 return -ENODEV;
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000565
566 if (pmic_probe(p))
567 return 0;
568
569 /* LDO15 voltage: 2.2v */
570 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
571 /* LDO13 voltage: 3.0v */
572 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
573
574 if (ret) {
575 puts("MAX8997 LDO setting error!\n");
576 return -1;
577 }
578
579 return 0;
580}
581
Piotr Wilczekfe601642014-03-07 14:59:48 +0100582int mipi_power(void)
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000583{
584 int ret = 0;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000585 struct pmic *p = pmic_get("MAX8997_PMIC");
586 if (!p)
587 return -ENODEV;
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000588
589 if (pmic_probe(p))
590 return 0;
591
592 /* LDO3 voltage: 1.1v */
593 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
594 /* LDO4 voltage: 1.8v */
595 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
596
597 if (ret) {
598 puts("MAX8997 LDO setting error!\n");
599 return -1;
600 }
601
602 return 0;
603}
604
Piotr Wilczekfe601642014-03-07 14:59:48 +0100605void exynos_lcd_misc_init(vidinfo_t *vid)
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000606{
Donghwa Lee90464972012-05-09 19:23:46 +0000607#ifdef CONFIG_TIZEN
608 get_tizen_logo_info(vid);
609#endif
Piotr Wilczekfe601642014-03-07 14:59:48 +0100610#ifdef CONFIG_S6E8AX0
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000611 s6e8ax0_init();
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000612 setenv("lcdinfo", "lcd=s6e8ax0");
Piotr Wilczekfe601642014-03-07 14:59:48 +0100613#endif
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000614}