blob: 68f686b7e6abdef1c07e8494639eb1da2e5b20ac [file] [log] [blame]
Haiying Wang765547d2009-03-27 17:02:45 -04001/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
Haiying Wang765547d2009-03-27 17:02:45 -040010
11#include <asm/fsl_ddr_sdram.h>
12#include <asm/fsl_ddr_dimm_params.h>
13
Haiying Wang765547d2009-03-27 17:02:45 -040014void fsl_ddr_board_options(memctl_options_t *popts,
15 dimm_params_t *pdimm,
16 unsigned int ctrl_num)
17{
18 /*
19 * Factors to consider for clock adjust:
20 * - number of chips on bus
21 * - position of slot
22 * - DDR1 vs. DDR2?
23 * - ???
24 *
25 * This needs to be determined on a board-by-board basis.
26 * 0110 3/4 cycle late
27 * 0111 7/8 cycle late
28 */
Dave Liu1b5291d2009-03-27 14:32:43 +080029 popts->clk_adjust = 4;
Haiying Wang765547d2009-03-27 17:02:45 -040030
31 /*
32 * Factors to consider for CPO:
33 * - frequency
34 * - ddr1 vs. ddr2
35 */
36 popts->cpo_override = 0xff;
37
38 /*
39 * Factors to consider for write data delay:
40 * - number of DIMMs
41 *
42 * 1 = 1/4 clock delay
43 * 2 = 1/2 clock delay
44 * 3 = 3/4 clock delay
45 * 4 = 1 clock delay
46 * 5 = 5/4 clock delay
47 * 6 = 3/2 clock delay
48 */
49 popts->write_data_delay = 2;
50
51 /*
Haiying Wangb6bde932010-09-29 13:31:36 -040052 * Enable half drive strength
Haiying Wang765547d2009-03-27 17:02:45 -040053 */
Haiying Wangb6bde932010-09-29 13:31:36 -040054 popts->half_strength_driver_enable = 1;
55
56 /* Write leveling override */
57 popts->wrlvl_en = 1;
58 popts->wrlvl_override = 1;
59 popts->wrlvl_sample = 0xa;
60 popts->wrlvl_start = 0x4;
61
62 /* Rtt and Rtt_W override */
63 popts->rtt_override = 1;
64 popts->rtt_override_value = DDR3_RTT_60_OHM;
65 popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
Haiying Wang765547d2009-03-27 17:02:45 -040066}