blob: 8c9afdf79aba5c857b4f2f5644b846ffcb37ec27 [file] [log] [blame]
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001/*
2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Marcin Wojtas <mw@semihalf.com>
7 *
8 * U-Boot version:
Stefan Roesec9607c92017-02-24 10:12:41 +01009 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010010 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070017#include <cpu_func.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010018#include <dm.h>
Simon Glass90526e92020-05-10 11:39:56 -060019#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060020#include <asm/global_data.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010021#include <dm/device-internal.h>
Simon Glass336d4612020-02-03 07:36:16 -070022#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070023#include <dm/devres.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010024#include <dm/lists.h>
25#include <net.h>
26#include <netdev.h>
27#include <config.h>
28#include <malloc.h>
29#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060030#include <linux/bitops.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060031#include <linux/bug.h>
Simon Glassc05ed002020-05-10 11:40:11 -060032#include <linux/delay.h>
Simon Glass61b29b82020-02-03 07:36:15 -070033#include <linux/err.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090034#include <linux/errno.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010035#include <phy.h>
36#include <miiphy.h>
37#include <watchdog.h>
38#include <asm/arch/cpu.h>
39#include <asm/arch/soc.h>
40#include <linux/compat.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060041#include <linux/libfdt.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010042#include <linux/mbus.h>
Stefan Chulski41893732017-08-09 10:37:43 +030043#include <asm-generic/gpio.h>
Stefan Chulski377883f2017-08-09 10:37:44 +030044#include <fdt_support.h>
Nevo Hed2a428702019-08-15 18:08:44 -040045#include <linux/mdio.h>
Stefan Roese99d4c6d2016-02-10 07:22:10 +010046
47DECLARE_GLOBAL_DATA_PTR;
48
Stefan Roese99d4c6d2016-02-10 07:22:10 +010049#define __verify_pcpu_ptr(ptr) \
50do { \
51 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
52 (void)__vpp_verify; \
53} while (0)
54
55#define VERIFY_PERCPU_PTR(__p) \
56({ \
57 __verify_pcpu_ptr(__p); \
58 (typeof(*(__p)) __kernel __force *)(__p); \
59})
60
61#define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
62#define smp_processor_id() 0
63#define num_present_cpus() 1
64#define for_each_present_cpu(cpu) \
65 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66
67#define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68
69#define CONFIG_NR_CPUS 1
Stefan Roese99d4c6d2016-02-10 07:22:10 +010070
71/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72#define WRAP (2 + ETH_HLEN + 4 + 32)
73#define MTU 1500
74#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
75
Stefan Roese99d4c6d2016-02-10 07:22:10 +010076/* RX Fifo Registers */
77#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
78#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
79#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
80#define MVPP2_RX_FIFO_INIT_REG 0x64
81
82/* RX DMA Top Registers */
83#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
84#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
85#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
86#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
87#define MVPP2_POOL_BUF_SIZE_OFFSET 5
88#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
89#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
90#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
91#define MVPP2_RXQ_POOL_SHORT_OFFS 20
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +010092#define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
93#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
Stefan Roese99d4c6d2016-02-10 07:22:10 +010094#define MVPP2_RXQ_POOL_LONG_OFFS 24
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +010095#define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
96#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
Stefan Roese99d4c6d2016-02-10 07:22:10 +010097#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
98#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
99#define MVPP2_RXQ_DISABLE_MASK BIT(31)
100
101/* Parser Registers */
102#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
103#define MVPP2_PRS_PORT_LU_MAX 0xf
104#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
105#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
106#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
107#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
108#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
109#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
110#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
111#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
112#define MVPP2_PRS_TCAM_IDX_REG 0x1100
113#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
114#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
115#define MVPP2_PRS_SRAM_IDX_REG 0x1200
116#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
117#define MVPP2_PRS_TCAM_CTRL_REG 0x1230
118#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
119
120/* Classifier Registers */
121#define MVPP2_CLS_MODE_REG 0x1800
122#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
123#define MVPP2_CLS_PORT_WAY_REG 0x1810
124#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
125#define MVPP2_CLS_LKP_INDEX_REG 0x1814
126#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
127#define MVPP2_CLS_LKP_TBL_REG 0x1818
128#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
129#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
130#define MVPP2_CLS_FLOW_INDEX_REG 0x1820
131#define MVPP2_CLS_FLOW_TBL0_REG 0x1824
132#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
133#define MVPP2_CLS_FLOW_TBL2_REG 0x182c
134#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
135#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
136#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
137#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
138#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
139#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
140
141/* Descriptor Manager Top Registers */
142#define MVPP2_RXQ_NUM_REG 0x2040
143#define MVPP2_RXQ_DESC_ADDR_REG 0x2044
Thomas Petazzoni80350f52017-02-20 11:36:57 +0100144#define MVPP22_DESC_ADDR_OFFS 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100145#define MVPP2_RXQ_DESC_SIZE_REG 0x2048
146#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
147#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
148#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
149#define MVPP2_RXQ_NUM_NEW_OFFSET 16
150#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
151#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
152#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
153#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
154#define MVPP2_RXQ_THRESH_REG 0x204c
155#define MVPP2_OCCUPIED_THRESH_OFFSET 0
156#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
157#define MVPP2_RXQ_INDEX_REG 0x2050
158#define MVPP2_TXQ_NUM_REG 0x2080
159#define MVPP2_TXQ_DESC_ADDR_REG 0x2084
160#define MVPP2_TXQ_DESC_SIZE_REG 0x2088
161#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
162#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
163#define MVPP2_TXQ_THRESH_REG 0x2094
164#define MVPP2_TRANSMITTED_THRESH_OFFSET 16
165#define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
166#define MVPP2_TXQ_INDEX_REG 0x2098
167#define MVPP2_TXQ_PREF_BUF_REG 0x209c
168#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
169#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
170#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
171#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
172#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
173#define MVPP2_TXQ_PENDING_REG 0x20a0
174#define MVPP2_TXQ_PENDING_MASK 0x3fff
175#define MVPP2_TXQ_INT_STATUS_REG 0x20a4
176#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
177#define MVPP2_TRANSMITTED_COUNT_OFFSET 16
178#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
179#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
180#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
181#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
182#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
183#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
184#define MVPP2_TXQ_RSVD_CLR_OFFSET 16
185#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
Thomas Petazzoni80350f52017-02-20 11:36:57 +0100186#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100187#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
188#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
189#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
190#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
191#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
192
193/* MBUS bridge registers */
194#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
195#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
196#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
197#define MVPP2_BASE_ADDR_ENABLE 0x4060
198
Thomas Petazzonicdf77792017-02-16 08:41:07 +0100199/* AXI Bridge Registers */
200#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
201#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
202#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
203#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
204#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
205#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
206#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
207#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
208#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
209#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
210#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
211#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
212
213/* Values for AXI Bridge registers */
214#define MVPP22_AXI_ATTR_CACHE_OFFS 0
215#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
216
217#define MVPP22_AXI_CODE_CACHE_OFFS 0
218#define MVPP22_AXI_CODE_DOMAIN_OFFS 4
219
220#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
221#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
222#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
223
224#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
225#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
226
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100227/* Interrupt Cause and Mask registers */
228#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
Thomas Petazzonibc0bbf42017-02-16 08:46:37 +0100229#define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
230
231#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
232#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
233#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
234#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
235
236#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
237#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
238
239#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
240#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
241#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
242#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
243
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100244#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
245#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
246#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
247#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
248#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
249#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
250#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
251#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
252#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
253#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
254#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
255#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
256#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
257#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
258#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
259#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
260#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
261#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
262
263/* Buffer Manager registers */
264#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
265#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
266#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
267#define MVPP2_BM_POOL_SIZE_MASK 0xfff0
268#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
269#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
270#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
271#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
272#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
273#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
274#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
275#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
276#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
277#define MVPP2_BM_START_MASK BIT(0)
278#define MVPP2_BM_STOP_MASK BIT(1)
279#define MVPP2_BM_STATE_MASK BIT(4)
280#define MVPP2_BM_LOW_THRESH_OFFS 8
281#define MVPP2_BM_LOW_THRESH_MASK 0x7f00
282#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
283 MVPP2_BM_LOW_THRESH_OFFS)
284#define MVPP2_BM_HIGH_THRESH_OFFS 16
285#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
286#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
287 MVPP2_BM_HIGH_THRESH_OFFS)
288#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
289#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
290#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
291#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
292#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
293#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
294#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
295#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
296#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
297#define MVPP2_BM_VIRT_ALLOC_REG 0x6440
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100298#define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
299#define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
300#define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
301#define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100302#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
303#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
304#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
305#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
306#define MVPP2_BM_VIRT_RLS_REG 0x64c0
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100307#define MVPP21_BM_MC_RLS_REG 0x64c4
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100308#define MVPP2_BM_MC_ID_MASK 0xfff
309#define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
Thomas Petazzonic8feeb22017-02-20 11:29:16 +0100310#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
311#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
312#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
313#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
314#define MVPP22_BM_MC_RLS_REG 0x64d4
Stefan Chulski783e7852017-08-09 10:37:50 +0300315#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
316#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100317
318/* TX Scheduler registers */
319#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325#define MVPP2_TXP_SCHED_MTU_REG 0x801c
326#define MVPP2_TXP_MTU_MAX 0x7FFFF
327#define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
341
342/* TX general registers */
343#define MVPP2_TX_SNOOP_REG 0x8800
344#define MVPP2_TX_PORT_FLUSH_REG 0x8810
345#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
346
347/* LMS registers */
348#define MVPP2_SRC_ADDR_MIDDLE 0x24
349#define MVPP2_SRC_ADDR_HIGH 0x28
350#define MVPP2_PHY_AN_CFG0_REG 0x34
351#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100352#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
Thomas Petazzoni6b28f422017-02-15 12:16:23 +0100353#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100354
355/* Per-port registers */
356#define MVPP2_GMAC_CTRL_0_REG 0x0
357#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100358#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100359#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
360#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
361#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
362#define MVPP2_GMAC_CTRL_1_REG 0x4
363#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
364#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
365#define MVPP2_GMAC_PCS_LB_EN_BIT 6
366#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
367#define MVPP2_GMAC_SA_LOW_OFFS 7
368#define MVPP2_GMAC_CTRL_2_REG 0x8
369#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100370#define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100371#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
372#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100373#define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100374#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100375#define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100376#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
377#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
378#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100379#define MVPP2_GMAC_EN_PCS_AN BIT(2)
380#define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100381#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
382#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
383#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
384#define MVPP2_GMAC_FC_ADV_EN BIT(9)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100385#define MVPP2_GMAC_EN_FC_AN BIT(11)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100386#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
387#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100388#define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100389#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
390#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
391#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
392#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
393 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100394#define MVPP2_GMAC_CTRL_4_REG 0x90
395#define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
396#define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
397#define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
398#define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100399
Stefan Roese31aa1e32017-03-22 15:07:30 +0100400/*
401 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
402 * relative to port->base.
403 */
404
405/* Port Mac Control0 */
406#define MVPP22_XLG_CTRL0_REG 0x100
407#define MVPP22_XLG_PORT_EN BIT(0)
408#define MVPP22_XLG_MAC_RESETN BIT(1)
409#define MVPP22_XLG_RX_FC_EN BIT(7)
410#define MVPP22_XLG_MIBCNT_DIS BIT(13)
411/* Port Mac Control1 */
412#define MVPP22_XLG_CTRL1_REG 0x104
413#define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
414#define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
415/* Port Interrupt Mask */
416#define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
417#define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
418/* Port Mac Control3 */
419#define MVPP22_XLG_CTRL3_REG 0x11c
420#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
421#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
422#define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
423/* Port Mac Control4 */
424#define MVPP22_XLG_CTRL4_REG 0x184
425#define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
426#define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
427#define MVPP22_XLG_MODE_DMA_1G BIT(12)
428#define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
429
430/* XPCS registers */
431
432/* Global Configuration 0 */
433#define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
434#define MVPP22_XPCS_PCSRESET BIT(0)
435#define MVPP22_XPCS_PCSMODE_OFFS 3
436#define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
437 MVPP22_XPCS_PCSMODE_OFFS)
438#define MVPP22_XPCS_LANEACTIVE_OFFS 5
439#define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
440 MVPP22_XPCS_LANEACTIVE_OFFS)
441
442/* MPCS registers */
443
444#define PCS40G_COMMON_CONTROL 0x14
Stefan Chulskie09d0c82017-04-06 15:39:08 +0200445#define FORWARD_ERROR_CORRECTION_MASK BIT(10)
Stefan Roese31aa1e32017-03-22 15:07:30 +0100446
447#define PCS_CLOCK_RESET 0x14c
448#define TX_SD_CLK_RESET_MASK BIT(0)
449#define RX_SD_CLK_RESET_MASK BIT(1)
450#define MAC_CLK_RESET_MASK BIT(2)
451#define CLK_DIVISION_RATIO_OFFS 4
452#define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
453#define CLK_DIV_PHASE_SET_MASK BIT(11)
454
455/* System Soft Reset 1 */
456#define GOP_SOFT_RESET_1_REG 0x108
457#define NETC_GOP_SOFT_RESET_OFFS 6
458#define NETC_GOP_SOFT_RESET_MASK (0x1 << \
459 NETC_GOP_SOFT_RESET_OFFS)
460
461/* Ports Control 0 */
462#define NETCOMP_PORTS_CONTROL_0_REG 0x110
463#define NETC_BUS_WIDTH_SELECT_OFFS 1
464#define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
465 NETC_BUS_WIDTH_SELECT_OFFS)
466#define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
467#define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
468 NETC_GIG_RX_DATA_SAMPLE_OFFS)
469#define NETC_CLK_DIV_PHASE_OFFS 31
470#define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
471/* Ports Control 1 */
472#define NETCOMP_PORTS_CONTROL_1_REG 0x114
473#define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
474#define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
475 NETC_PORTS_ACTIVE_OFFSET(p))
476#define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
477#define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
478 NETC_PORT_GIG_RF_RESET_OFFS(p))
479#define NETCOMP_CONTROL_0_REG 0x120
480#define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
481#define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
482 NETC_GBE_PORT0_SGMII_MODE_OFFS)
483#define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
484#define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
485 NETC_GBE_PORT1_SGMII_MODE_OFFS)
486#define NETC_GBE_PORT1_MII_MODE_OFFS 2
487#define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
488 NETC_GBE_PORT1_MII_MODE_OFFS)
489
490#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +0100491#define MVPP22_SMI_POLLING_EN BIT(10)
492
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100493#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
494
495/* Descriptor ring Macros */
496#define MVPP2_QUEUE_NEXT_DESC(q, index) \
497 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
498
Stefan Roese0a61e9a2017-02-16 08:31:32 +0100499/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
500#define MVPP22_SMI 0x1200
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100501
Stefan Roese31aa1e32017-03-22 15:07:30 +0100502/* Additional PPv2.2 offsets */
503#define MVPP22_MPCS 0x007000
504#define MVPP22_XPCS 0x007400
505#define MVPP22_PORT_BASE 0x007e00
506#define MVPP22_PORT_OFFSET 0x001000
507#define MVPP22_RFU1 0x318000
508
509/* Maximum number of ports */
510#define MVPP22_GOP_MAC_NUM 4
511
512/* Sets the field located at the specified in data */
513#define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
514#define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
515#define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
516
517/* Net Complex */
518enum mv_netc_topology {
519 MV_NETC_GE_MAC2_SGMII = BIT(0),
Stefan Chulski8d3aa372021-05-03 08:08:45 +0200520 MV_NETC_GE_MAC2_RGMII = BIT(1),
521 MV_NETC_GE_MAC3_SGMII = BIT(2),
522 MV_NETC_GE_MAC3_RGMII = BIT(3),
Stefan Roese31aa1e32017-03-22 15:07:30 +0100523};
524
525enum mv_netc_phase {
526 MV_NETC_FIRST_PHASE,
527 MV_NETC_SECOND_PHASE,
528};
529
530enum mv_netc_sgmii_xmi_mode {
531 MV_NETC_GBE_SGMII,
532 MV_NETC_GBE_XMII,
533};
534
535enum mv_netc_mii_mode {
536 MV_NETC_GBE_RGMII,
537 MV_NETC_GBE_MII,
538};
539
540enum mv_netc_lanes {
541 MV_NETC_LANE_23,
542 MV_NETC_LANE_45,
543};
544
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100545/* Various constants */
546
547/* Coalescing */
548#define MVPP2_TXDONE_COAL_PKTS_THRESH 15
549#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
550#define MVPP2_RX_COAL_PKTS 32
551#define MVPP2_RX_COAL_USEC 100
552
553/* The two bytes Marvell header. Either contains a special value used
554 * by Marvell switches when a specific hardware mode is enabled (not
555 * supported by this driver) or is filled automatically by zeroes on
556 * the RX side. Those two bytes being at the front of the Ethernet
557 * header, they allow to have the IP header aligned on a 4 bytes
558 * boundary automatically: the hardware skips those two bytes on its
559 * own.
560 */
561#define MVPP2_MH_SIZE 2
562#define MVPP2_ETH_TYPE_LEN 2
563#define MVPP2_PPPOE_HDR_SIZE 8
564#define MVPP2_VLAN_TAG_LEN 4
565
566/* Lbtd 802.3 type */
567#define MVPP2_IP_LBDT_TYPE 0xfffa
568
569#define MVPP2_CPU_D_CACHE_LINE_SIZE 32
570#define MVPP2_TX_CSUM_MAX_SIZE 9800
571
572/* Timeout constants */
573#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
574#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
575
576#define MVPP2_TX_MTU_MAX 0x7ffff
577
578/* Maximum number of T-CONTs of PON port */
579#define MVPP2_MAX_TCONT 16
580
581/* Maximum number of supported ports */
582#define MVPP2_MAX_PORTS 4
583
584/* Maximum number of TXQs used by single port */
585#define MVPP2_MAX_TXQ 8
586
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100587/* Default number of TXQs in use */
588#define MVPP2_DEFAULT_TXQ 1
589
Flavio Suligoidad9af52020-01-29 09:38:56 +0100590/* Default number of RXQs in use */
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100591#define MVPP2_DEFAULT_RXQ 1
592#define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
593
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100594/* Max number of Rx descriptors */
595#define MVPP2_MAX_RXD 16
596
597/* Max number of Tx descriptors */
598#define MVPP2_MAX_TXD 16
599
600/* Amount of Tx descriptors that can be reserved at once by CPU */
Stefan Chulskif0e970f2017-08-09 10:37:47 +0300601#define MVPP2_CPU_DESC_CHUNK 16
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100602
603/* Max number of Tx descriptors in each aggregated queue */
Stefan Chulskif0e970f2017-08-09 10:37:47 +0300604#define MVPP2_AGGR_TXQ_SIZE 16
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100605
606/* Descriptor aligned size */
607#define MVPP2_DESC_ALIGNED_SIZE 32
608
609/* Descriptor alignment mask */
610#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
611
612/* RX FIFO constants */
Stefan Roeseff572c62017-03-01 13:09:42 +0100613#define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
614#define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
615#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
616#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
617#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
618#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
619#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
620#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
621#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
622
623/* TX general registers */
624#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
625#define MVPP22_TX_FIFO_SIZE_MASK 0xf
626
627/* TX FIFO constants */
628#define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
629#define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100630
631/* RX buffer constants */
632#define MVPP2_SKB_SHINFO_SIZE \
633 0
634
635#define MVPP2_RX_PKT_SIZE(mtu) \
636 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
637 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
638
639#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
640#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
641#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
642 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
643
644#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
645
646/* IPv6 max L3 address size */
647#define MVPP2_MAX_L3_ADDR_SIZE 16
648
649/* Port flags */
650#define MVPP2_F_LOOPBACK BIT(0)
651
652/* Marvell tag types */
653enum mvpp2_tag_type {
654 MVPP2_TAG_TYPE_NONE = 0,
655 MVPP2_TAG_TYPE_MH = 1,
656 MVPP2_TAG_TYPE_DSA = 2,
657 MVPP2_TAG_TYPE_EDSA = 3,
658 MVPP2_TAG_TYPE_VLAN = 4,
659 MVPP2_TAG_TYPE_LAST = 5
660};
661
662/* Parser constants */
663#define MVPP2_PRS_TCAM_SRAM_SIZE 256
664#define MVPP2_PRS_TCAM_WORDS 6
665#define MVPP2_PRS_SRAM_WORDS 4
666#define MVPP2_PRS_FLOW_ID_SIZE 64
667#define MVPP2_PRS_FLOW_ID_MASK 0x3f
668#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
669#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
670#define MVPP2_PRS_IPV4_HEAD 0x40
671#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
672#define MVPP2_PRS_IPV4_MC 0xe0
673#define MVPP2_PRS_IPV4_MC_MASK 0xf0
674#define MVPP2_PRS_IPV4_BC_MASK 0xff
675#define MVPP2_PRS_IPV4_IHL 0x5
676#define MVPP2_PRS_IPV4_IHL_MASK 0xf
677#define MVPP2_PRS_IPV6_MC 0xff
678#define MVPP2_PRS_IPV6_MC_MASK 0xff
679#define MVPP2_PRS_IPV6_HOP_MASK 0xff
680#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
681#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
682#define MVPP2_PRS_DBL_VLANS_MAX 100
683
684/* Tcam structure:
685 * - lookup ID - 4 bits
686 * - port ID - 1 byte
687 * - additional information - 1 byte
688 * - header data - 8 bytes
689 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
690 */
691#define MVPP2_PRS_AI_BITS 8
692#define MVPP2_PRS_PORT_MASK 0xff
693#define MVPP2_PRS_LU_MASK 0xf
694#define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
695 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
696#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
697 (((offs) * 2) - ((offs) % 2) + 2)
698#define MVPP2_PRS_TCAM_AI_BYTE 16
699#define MVPP2_PRS_TCAM_PORT_BYTE 17
700#define MVPP2_PRS_TCAM_LU_BYTE 20
701#define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
702#define MVPP2_PRS_TCAM_INV_WORD 5
703/* Tcam entries ID */
704#define MVPP2_PE_DROP_ALL 0
705#define MVPP2_PE_FIRST_FREE_TID 1
706#define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
707#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
708#define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
709#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
710#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
711#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
712#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
713#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
714#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
715#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
716#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
717#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
718#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
719#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
720#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
721#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
722#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
723#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
724#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
725#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
726#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
727#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
728#define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
729#define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
730#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
731
732/* Sram structure
733 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
734 */
735#define MVPP2_PRS_SRAM_RI_OFFS 0
736#define MVPP2_PRS_SRAM_RI_WORD 0
737#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
738#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
739#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
740#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
741#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
742#define MVPP2_PRS_SRAM_UDF_OFFS 73
743#define MVPP2_PRS_SRAM_UDF_BITS 8
744#define MVPP2_PRS_SRAM_UDF_MASK 0xff
745#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
746#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
747#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
748#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
749#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
750#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
751#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
752#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
753#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
754#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
755#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
756#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
757#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
758#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
759#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
760#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
761#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
762#define MVPP2_PRS_SRAM_AI_OFFS 90
763#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
764#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
765#define MVPP2_PRS_SRAM_AI_MASK 0xff
766#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
767#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
768#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
769#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
770
771/* Sram result info bits assignment */
772#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
773#define MVPP2_PRS_RI_DSA_MASK 0x2
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100774#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
775#define MVPP2_PRS_RI_VLAN_NONE 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100776#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
777#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
778#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
779#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
780#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100781#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
782#define MVPP2_PRS_RI_L2_UCAST 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100783#define MVPP2_PRS_RI_L2_MCAST BIT(9)
784#define MVPP2_PRS_RI_L2_BCAST BIT(10)
785#define MVPP2_PRS_RI_PPPOE_MASK 0x800
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100786#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
787#define MVPP2_PRS_RI_L3_UN 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100788#define MVPP2_PRS_RI_L3_IP4 BIT(12)
789#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
790#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
791#define MVPP2_PRS_RI_L3_IP6 BIT(14)
792#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
793#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
Thomas Petazzonic0abc762017-02-15 12:19:36 +0100794#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
795#define MVPP2_PRS_RI_L3_UCAST 0x0
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100796#define MVPP2_PRS_RI_L3_MCAST BIT(15)
797#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
798#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
799#define MVPP2_PRS_RI_UDF3_MASK 0x300000
800#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
801#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
802#define MVPP2_PRS_RI_L4_TCP BIT(22)
803#define MVPP2_PRS_RI_L4_UDP BIT(23)
804#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
805#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
806#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
807#define MVPP2_PRS_RI_DROP_MASK 0x80000000
808
809/* Sram additional info bits assignment */
810#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
811#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
812#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
813#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
814#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
815#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
816#define MVPP2_PRS_SINGLE_VLAN_AI 0
817#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
818
819/* DSA/EDSA type */
820#define MVPP2_PRS_TAGGED true
821#define MVPP2_PRS_UNTAGGED false
822#define MVPP2_PRS_EDSA true
823#define MVPP2_PRS_DSA false
824
825/* MAC entries, shadow udf */
826enum mvpp2_prs_udf {
827 MVPP2_PRS_UDF_MAC_DEF,
828 MVPP2_PRS_UDF_MAC_RANGE,
829 MVPP2_PRS_UDF_L2_DEF,
830 MVPP2_PRS_UDF_L2_DEF_COPY,
831 MVPP2_PRS_UDF_L2_USER,
832};
833
834/* Lookup ID */
835enum mvpp2_prs_lookup {
836 MVPP2_PRS_LU_MH,
837 MVPP2_PRS_LU_MAC,
838 MVPP2_PRS_LU_DSA,
839 MVPP2_PRS_LU_VLAN,
840 MVPP2_PRS_LU_L2,
841 MVPP2_PRS_LU_PPPOE,
842 MVPP2_PRS_LU_IP4,
843 MVPP2_PRS_LU_IP6,
844 MVPP2_PRS_LU_FLOWS,
845 MVPP2_PRS_LU_LAST,
846};
847
848/* L3 cast enum */
849enum mvpp2_prs_l3_cast {
850 MVPP2_PRS_L3_UNI_CAST,
851 MVPP2_PRS_L3_MULTI_CAST,
852 MVPP2_PRS_L3_BROAD_CAST
853};
854
855/* Classifier constants */
856#define MVPP2_CLS_FLOWS_TBL_SIZE 512
857#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
858#define MVPP2_CLS_LKP_TBL_SIZE 64
859
860/* BM constants */
861#define MVPP2_BM_POOLS_NUM 1
862#define MVPP2_BM_LONG_BUF_NUM 16
863#define MVPP2_BM_SHORT_BUF_NUM 16
864#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
865#define MVPP2_BM_POOL_PTR_ALIGN 128
866#define MVPP2_BM_SWF_LONG_POOL(port) 0
867
868/* BM cookie (32 bits) definition */
869#define MVPP2_BM_COOKIE_POOL_OFFS 8
870#define MVPP2_BM_COOKIE_CPU_OFFS 24
871
872/* BM short pool packet size
873 * These value assure that for SWF the total number
874 * of bytes allocated for each buffer will be 512
875 */
876#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
877
878enum mvpp2_bm_type {
879 MVPP2_BM_FREE,
880 MVPP2_BM_SWF_LONG,
881 MVPP2_BM_SWF_SHORT
882};
883
884/* Definitions */
885
886/* Shared Packet Processor resources */
887struct mvpp2 {
888 /* Shared registers' base addresses */
889 void __iomem *base;
890 void __iomem *lms_base;
Thomas Petazzoni26a52782017-02-16 08:03:37 +0100891 void __iomem *iface_base;
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100892
Stefan Roese31aa1e32017-03-22 15:07:30 +0100893 void __iomem *mpcs_base;
894 void __iomem *xpcs_base;
895 void __iomem *rfu1_base;
896
897 u32 netc_config;
898
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100899 /* List of pointers to port structures */
900 struct mvpp2_port **port_list;
901
902 /* Aggregated TXQs */
903 struct mvpp2_tx_queue *aggr_txqs;
904
905 /* BM pools */
906 struct mvpp2_bm_pool *bm_pools;
907
908 /* PRS shadow table */
909 struct mvpp2_prs_shadow *prs_shadow;
910 /* PRS auxiliary table for double vlan entries control */
911 bool *prs_double_vlans;
912
913 /* Tclk value */
914 u32 tclk;
915
Thomas Petazzoni16a98982017-02-15 14:08:59 +0100916 /* HW version */
917 enum { MVPP21, MVPP22 } hw_version;
918
Thomas Petazzoni09b3f942017-02-16 09:03:16 +0100919 /* Maximum number of RXQs per port */
920 unsigned int max_port_rxqs;
921
Stefan Roese1fabbd02017-02-16 15:26:06 +0100922 int probe_done;
Stefan Chulskibb915c82017-08-09 10:37:46 +0300923 u8 num_ports;
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100924};
925
926struct mvpp2_pcpu_stats {
927 u64 rx_packets;
928 u64 rx_bytes;
929 u64 tx_packets;
930 u64 tx_bytes;
931};
932
933struct mvpp2_port {
934 u8 id;
935
Thomas Petazzoni26a52782017-02-16 08:03:37 +0100936 /* Index of the port from the "group of ports" complex point
937 * of view
938 */
939 int gop_id;
940
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100941 int irq;
942
943 struct mvpp2 *priv;
944
945 /* Per-port registers' base address */
946 void __iomem *base;
947
948 struct mvpp2_rx_queue **rxqs;
949 struct mvpp2_tx_queue **txqs;
950
951 int pkt_size;
952
953 u32 pending_cause_rx;
954
955 /* Per-CPU port control */
956 struct mvpp2_port_pcpu __percpu *pcpu;
957
958 /* Flags */
959 unsigned long flags;
960
961 u16 tx_ring_size;
962 u16 rx_ring_size;
963 struct mvpp2_pcpu_stats __percpu *stats;
964
965 struct phy_device *phy_dev;
966 phy_interface_t phy_interface;
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100967 int phyaddr;
Nevo Hed2a428702019-08-15 18:08:44 -0400968 struct udevice *mdio_dev;
Simon Glassbcee8d62019-12-06 21:41:35 -0700969 struct mii_dev *bus;
970#if CONFIG_IS_ENABLED(DM_GPIO)
Stefan Chulski41893732017-08-09 10:37:43 +0300971 struct gpio_desc phy_reset_gpio;
972 struct gpio_desc phy_tx_disable_gpio;
973#endif
Stefan Roese99d4c6d2016-02-10 07:22:10 +0100974 int init;
975 unsigned int link;
976 unsigned int duplex;
977 unsigned int speed;
978
979 struct mvpp2_bm_pool *pool_long;
980 struct mvpp2_bm_pool *pool_short;
981
982 /* Index of first port's physical RXQ */
983 u8 first_rxq;
984
985 u8 dev_addr[ETH_ALEN];
986};
987
988/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
989 * layout of the transmit and reception DMA descriptors, and their
990 * layout is therefore defined by the hardware design
991 */
992
993#define MVPP2_TXD_L3_OFF_SHIFT 0
994#define MVPP2_TXD_IP_HLEN_SHIFT 8
995#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
996#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
997#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
998#define MVPP2_TXD_PADDING_DISABLE BIT(23)
999#define MVPP2_TXD_L4_UDP BIT(24)
1000#define MVPP2_TXD_L3_IP6 BIT(26)
1001#define MVPP2_TXD_L_DESC BIT(28)
1002#define MVPP2_TXD_F_DESC BIT(29)
1003
1004#define MVPP2_RXD_ERR_SUMMARY BIT(15)
1005#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1006#define MVPP2_RXD_ERR_CRC 0x0
1007#define MVPP2_RXD_ERR_OVERRUN BIT(13)
1008#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1009#define MVPP2_RXD_BM_POOL_ID_OFFS 16
1010#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1011#define MVPP2_RXD_HWF_SYNC BIT(21)
1012#define MVPP2_RXD_L4_CSUM_OK BIT(22)
1013#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1014#define MVPP2_RXD_L4_TCP BIT(25)
1015#define MVPP2_RXD_L4_UDP BIT(26)
1016#define MVPP2_RXD_L3_IP4 BIT(28)
1017#define MVPP2_RXD_L3_IP6 BIT(30)
1018#define MVPP2_RXD_BUF_HDR BIT(31)
1019
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001020/* HW TX descriptor for PPv2.1 */
1021struct mvpp21_tx_desc {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001022 u32 command; /* Options used by HW for packet transmitting.*/
1023 u8 packet_offset; /* the offset from the buffer beginning */
1024 u8 phys_txq; /* destination queue ID */
1025 u16 data_size; /* data size of transmitted packet in bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001026 u32 buf_dma_addr; /* physical addr of transmitted buffer */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001027 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1028 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1029 u32 reserved2; /* reserved (for future use) */
1030};
1031
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001032/* HW RX descriptor for PPv2.1 */
1033struct mvpp21_rx_desc {
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001034 u32 status; /* info about received packet */
1035 u16 reserved1; /* parser_info (for future use, PnC) */
1036 u16 data_size; /* size of received packet in bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001037 u32 buf_dma_addr; /* physical address of the buffer */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001038 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1039 u16 reserved2; /* gem_port_id (for future use, PON) */
1040 u16 reserved3; /* csum_l4 (for future use, PnC) */
1041 u8 reserved4; /* bm_qset (for future use, BM) */
1042 u8 reserved5;
1043 u16 reserved6; /* classify_info (for future use, PnC) */
1044 u32 reserved7; /* flow_id (for future use, PnC) */
1045 u32 reserved8;
1046};
1047
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001048/* HW TX descriptor for PPv2.2 */
1049struct mvpp22_tx_desc {
1050 u32 command;
1051 u8 packet_offset;
1052 u8 phys_txq;
1053 u16 data_size;
1054 u64 reserved1;
1055 u64 buf_dma_addr_ptp;
1056 u64 buf_cookie_misc;
1057};
1058
1059/* HW RX descriptor for PPv2.2 */
1060struct mvpp22_rx_desc {
1061 u32 status;
1062 u16 reserved1;
1063 u16 data_size;
1064 u32 reserved2;
1065 u32 reserved3;
1066 u64 buf_dma_addr_key_hash;
1067 u64 buf_cookie_misc;
1068};
1069
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001070/* Opaque type used by the driver to manipulate the HW TX and RX
1071 * descriptors
1072 */
1073struct mvpp2_tx_desc {
1074 union {
1075 struct mvpp21_tx_desc pp21;
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001076 struct mvpp22_tx_desc pp22;
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001077 };
1078};
1079
1080struct mvpp2_rx_desc {
1081 union {
1082 struct mvpp21_rx_desc pp21;
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001083 struct mvpp22_rx_desc pp22;
Thomas Petazzoni9a6db0b2017-02-15 16:25:53 +01001084 };
1085};
1086
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001087/* Per-CPU Tx queue control */
1088struct mvpp2_txq_pcpu {
1089 int cpu;
1090
1091 /* Number of Tx DMA descriptors in the descriptor ring */
1092 int size;
1093
1094 /* Number of currently used Tx DMA descriptor in the
1095 * descriptor ring
1096 */
1097 int count;
1098
1099 /* Number of Tx DMA descriptors reserved for each CPU */
1100 int reserved_num;
1101
1102 /* Index of last TX DMA descriptor that was inserted */
1103 int txq_put_index;
1104
1105 /* Index of the TX DMA descriptor to be cleaned up */
1106 int txq_get_index;
1107};
1108
1109struct mvpp2_tx_queue {
1110 /* Physical number of this Tx queue */
1111 u8 id;
1112
1113 /* Logical number of this Tx queue */
1114 u8 log_id;
1115
1116 /* Number of Tx DMA descriptors in the descriptor ring */
1117 int size;
1118
1119 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1120 int count;
1121
1122 /* Per-CPU control of physical Tx queues */
1123 struct mvpp2_txq_pcpu __percpu *pcpu;
1124
1125 u32 done_pkts_coal;
1126
1127 /* Virtual address of thex Tx DMA descriptors array */
1128 struct mvpp2_tx_desc *descs;
1129
1130 /* DMA address of the Tx DMA descriptors array */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001131 dma_addr_t descs_dma;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001132
1133 /* Index of the last Tx DMA descriptor */
1134 int last_desc;
1135
1136 /* Index of the next Tx DMA descriptor to process */
1137 int next_desc_to_proc;
1138};
1139
1140struct mvpp2_rx_queue {
1141 /* RX queue number, in the range 0-31 for physical RXQs */
1142 u8 id;
1143
1144 /* Num of rx descriptors in the rx descriptor ring */
1145 int size;
1146
1147 u32 pkts_coal;
1148 u32 time_coal;
1149
1150 /* Virtual address of the RX DMA descriptors array */
1151 struct mvpp2_rx_desc *descs;
1152
1153 /* DMA address of the RX DMA descriptors array */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001154 dma_addr_t descs_dma;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001155
1156 /* Index of the last RX DMA descriptor */
1157 int last_desc;
1158
1159 /* Index of the next RX DMA descriptor to process */
1160 int next_desc_to_proc;
1161
1162 /* ID of port to which physical RXQ is mapped */
1163 int port;
1164
1165 /* Port's logic RXQ number to which physical RXQ is mapped */
1166 int logic_rxq;
1167};
1168
1169union mvpp2_prs_tcam_entry {
1170 u32 word[MVPP2_PRS_TCAM_WORDS];
1171 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1172};
1173
1174union mvpp2_prs_sram_entry {
1175 u32 word[MVPP2_PRS_SRAM_WORDS];
1176 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1177};
1178
1179struct mvpp2_prs_entry {
1180 u32 index;
1181 union mvpp2_prs_tcam_entry tcam;
1182 union mvpp2_prs_sram_entry sram;
1183};
1184
1185struct mvpp2_prs_shadow {
1186 bool valid;
1187 bool finish;
1188
1189 /* Lookup ID */
1190 int lu;
1191
1192 /* User defined offset */
1193 int udf;
1194
1195 /* Result info */
1196 u32 ri;
1197 u32 ri_mask;
1198};
1199
1200struct mvpp2_cls_flow_entry {
1201 u32 index;
1202 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1203};
1204
1205struct mvpp2_cls_lookup_entry {
1206 u32 lkpid;
1207 u32 way;
1208 u32 data;
1209};
1210
1211struct mvpp2_bm_pool {
1212 /* Pool number in the range 0-7 */
1213 int id;
1214 enum mvpp2_bm_type type;
1215
1216 /* Buffer Pointers Pool External (BPPE) size */
1217 int size;
1218 /* Number of buffers for this pool */
1219 int buf_num;
1220 /* Pool buffer size */
1221 int buf_size;
1222 /* Packet size */
1223 int pkt_size;
1224
1225 /* BPPE virtual base address */
Stefan Roesea7c28ff2017-02-15 12:46:18 +01001226 unsigned long *virt_addr;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01001227 /* BPPE DMA base address */
1228 dma_addr_t dma_addr;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001229
1230 /* Ports using BM pool */
1231 u32 port_map;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001232};
1233
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001234/* Static declaractions */
1235
1236/* Number of RXQs used by single port */
1237static int rxq_number = MVPP2_DEFAULT_RXQ;
1238/* Number of TXQs used by single port */
1239static int txq_number = MVPP2_DEFAULT_TXQ;
1240
Stefan Roesec9607c92017-02-24 10:12:41 +01001241static int base_id;
1242
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001243#define MVPP2_DRIVER_NAME "mvpp2"
1244#define MVPP2_DRIVER_VERSION "1.0"
1245
1246/*
1247 * U-Boot internal data, mostly uncached buffers for descriptors and data
1248 */
1249struct buffer_location {
1250 struct mvpp2_tx_desc *aggr_tx_descs;
1251 struct mvpp2_tx_desc *tx_descs;
1252 struct mvpp2_rx_desc *rx_descs;
Stefan Roesea7c28ff2017-02-15 12:46:18 +01001253 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1254 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001255 int first_rxq;
1256};
1257
1258/*
1259 * All 4 interfaces use the same global buffer, since only one interface
1260 * can be enabled at once
1261 */
1262static struct buffer_location buffer_loc;
Sven Auhagen3078e032020-07-01 17:43:43 +02001263static int buffer_loc_init;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001264
1265/*
1266 * Page table entries are set to 1MB, or multiples of 1MB
1267 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1268 */
1269#define BD_SPACE (1 << 20)
1270
1271/* Utility/helper methods */
1272
1273static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1274{
1275 writel(data, priv->base + offset);
1276}
1277
1278static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1279{
1280 return readl(priv->base + offset);
1281}
1282
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001283static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1284 struct mvpp2_tx_desc *tx_desc,
1285 dma_addr_t dma_addr)
1286{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001287 if (port->priv->hw_version == MVPP21) {
1288 tx_desc->pp21.buf_dma_addr = dma_addr;
1289 } else {
1290 u64 val = (u64)dma_addr;
1291
1292 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1293 tx_desc->pp22.buf_dma_addr_ptp |= val;
1294 }
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001295}
1296
1297static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1298 struct mvpp2_tx_desc *tx_desc,
1299 size_t size)
1300{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001301 if (port->priv->hw_version == MVPP21)
1302 tx_desc->pp21.data_size = size;
1303 else
1304 tx_desc->pp22.data_size = size;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001305}
1306
1307static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1308 struct mvpp2_tx_desc *tx_desc,
1309 unsigned int txq)
1310{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001311 if (port->priv->hw_version == MVPP21)
1312 tx_desc->pp21.phys_txq = txq;
1313 else
1314 tx_desc->pp22.phys_txq = txq;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001315}
1316
1317static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1318 struct mvpp2_tx_desc *tx_desc,
1319 unsigned int command)
1320{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001321 if (port->priv->hw_version == MVPP21)
1322 tx_desc->pp21.command = command;
1323 else
1324 tx_desc->pp22.command = command;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001325}
1326
1327static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1328 struct mvpp2_tx_desc *tx_desc,
1329 unsigned int offset)
1330{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001331 if (port->priv->hw_version == MVPP21)
1332 tx_desc->pp21.packet_offset = offset;
1333 else
1334 tx_desc->pp22.packet_offset = offset;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001335}
1336
1337static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1338 struct mvpp2_rx_desc *rx_desc)
1339{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001340 if (port->priv->hw_version == MVPP21)
1341 return rx_desc->pp21.buf_dma_addr;
1342 else
1343 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001344}
1345
1346static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1347 struct mvpp2_rx_desc *rx_desc)
1348{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001349 if (port->priv->hw_version == MVPP21)
1350 return rx_desc->pp21.buf_cookie;
1351 else
1352 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001353}
1354
1355static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1356 struct mvpp2_rx_desc *rx_desc)
1357{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001358 if (port->priv->hw_version == MVPP21)
1359 return rx_desc->pp21.data_size;
1360 else
1361 return rx_desc->pp22.data_size;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001362}
1363
1364static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1365 struct mvpp2_rx_desc *rx_desc)
1366{
Thomas Petazzonif50a0112017-02-20 11:08:46 +01001367 if (port->priv->hw_version == MVPP21)
1368 return rx_desc->pp21.status;
1369 else
1370 return rx_desc->pp22.status;
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01001371}
1372
Stefan Roese99d4c6d2016-02-10 07:22:10 +01001373static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1374{
1375 txq_pcpu->txq_get_index++;
1376 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1377 txq_pcpu->txq_get_index = 0;
1378}
1379
1380/* Get number of physical egress port */
1381static inline int mvpp2_egress_port(struct mvpp2_port *port)
1382{
1383 return MVPP2_MAX_TCONT + port->id;
1384}
1385
1386/* Get number of physical TXQ */
1387static inline int mvpp2_txq_phys(int port, int txq)
1388{
1389 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1390}
1391
1392/* Parser configuration routines */
1393
1394/* Update parser tcam and sram hw entries */
1395static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1396{
1397 int i;
1398
1399 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1400 return -EINVAL;
1401
1402 /* Clear entry invalidation bit */
1403 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1404
1405 /* Write tcam index - indirect access */
1406 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1407 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1408 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1409
1410 /* Write sram index - indirect access */
1411 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1412 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1414
1415 return 0;
1416}
1417
1418/* Read tcam entry from hw */
1419static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1420{
1421 int i;
1422
1423 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1424 return -EINVAL;
1425
1426 /* Write tcam index - indirect access */
1427 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1428
1429 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1430 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1431 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1432 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1433
1434 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1435 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1436
1437 /* Write sram index - indirect access */
1438 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1439 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1441
1442 return 0;
1443}
1444
1445/* Invalidate tcam hw entry */
1446static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1447{
1448 /* Write index - indirect access */
1449 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1450 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1451 MVPP2_PRS_TCAM_INV_MASK);
1452}
1453
1454/* Enable shadow table entry and set its lookup ID */
1455static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1456{
1457 priv->prs_shadow[index].valid = true;
1458 priv->prs_shadow[index].lu = lu;
1459}
1460
1461/* Update ri fields in shadow table entry */
1462static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1463 unsigned int ri, unsigned int ri_mask)
1464{
1465 priv->prs_shadow[index].ri_mask = ri_mask;
1466 priv->prs_shadow[index].ri = ri;
1467}
1468
1469/* Update lookup field in tcam sw entry */
1470static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1471{
1472 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1473
1474 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1475 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1476}
1477
1478/* Update mask for single port in tcam sw entry */
1479static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1480 unsigned int port, bool add)
1481{
1482 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1483
1484 if (add)
1485 pe->tcam.byte[enable_off] &= ~(1 << port);
1486 else
1487 pe->tcam.byte[enable_off] |= 1 << port;
1488}
1489
1490/* Update port map in tcam sw entry */
1491static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1492 unsigned int ports)
1493{
1494 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1495 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1496
1497 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1498 pe->tcam.byte[enable_off] &= ~port_mask;
1499 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1500}
1501
1502/* Obtain port map from tcam sw entry */
1503static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1504{
1505 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1506
1507 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1508}
1509
1510/* Set byte of data and its enable bits in tcam sw entry */
1511static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1512 unsigned int offs, unsigned char byte,
1513 unsigned char enable)
1514{
1515 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1516 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1517}
1518
1519/* Get byte of data and its enable bits from tcam sw entry */
1520static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1521 unsigned int offs, unsigned char *byte,
1522 unsigned char *enable)
1523{
1524 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1525 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1526}
1527
1528/* Set ethertype in tcam sw entry */
1529static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1530 unsigned short ethertype)
1531{
1532 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1533 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1534}
1535
1536/* Set bits in sram sw entry */
1537static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1538 int val)
1539{
1540 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1541}
1542
1543/* Clear bits in sram sw entry */
1544static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1545 int val)
1546{
1547 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1548}
1549
1550/* Update ri bits in sram sw entry */
1551static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1552 unsigned int bits, unsigned int mask)
1553{
1554 unsigned int i;
1555
1556 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1557 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1558
1559 if (!(mask & BIT(i)))
1560 continue;
1561
1562 if (bits & BIT(i))
1563 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1564 else
1565 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1566
1567 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1568 }
1569}
1570
1571/* Update ai bits in sram sw entry */
1572static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1573 unsigned int bits, unsigned int mask)
1574{
1575 unsigned int i;
1576 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1577
1578 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1579
1580 if (!(mask & BIT(i)))
1581 continue;
1582
1583 if (bits & BIT(i))
1584 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1585 else
1586 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1587
1588 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1589 }
1590}
1591
1592/* Read ai bits from sram sw entry */
1593static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1594{
1595 u8 bits;
1596 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1597 int ai_en_off = ai_off + 1;
1598 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1599
1600 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1601 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1602
1603 return bits;
1604}
1605
1606/* In sram sw entry set lookup ID field of the tcam key to be used in the next
1607 * lookup interation
1608 */
1609static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1610 unsigned int lu)
1611{
1612 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1613
1614 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1615 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1616 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1617}
1618
1619/* In the sram sw entry set sign and value of the next lookup offset
1620 * and the offset value generated to the classifier
1621 */
1622static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1623 unsigned int op)
1624{
1625 /* Set sign */
1626 if (shift < 0) {
1627 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1628 shift = 0 - shift;
1629 } else {
1630 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1631 }
1632
1633 /* Set value */
1634 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1635 (unsigned char)shift;
1636
1637 /* Reset and set operation */
1638 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1639 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1640 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1641
1642 /* Set base offset as current */
1643 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1644}
1645
1646/* In the sram sw entry set sign and value of the user defined offset
1647 * generated to the classifier
1648 */
1649static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1650 unsigned int type, int offset,
1651 unsigned int op)
1652{
1653 /* Set sign */
1654 if (offset < 0) {
1655 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1656 offset = 0 - offset;
1657 } else {
1658 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1659 }
1660
1661 /* Set value */
1662 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1663 MVPP2_PRS_SRAM_UDF_MASK);
1664 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1665 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1666 MVPP2_PRS_SRAM_UDF_BITS)] &=
1667 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1668 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1669 MVPP2_PRS_SRAM_UDF_BITS)] |=
1670 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1671
1672 /* Set offset type */
1673 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1674 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1675 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1676
1677 /* Set offset operation */
1678 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1679 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1680 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1681
1682 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1683 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1684 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1685 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1686
1687 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1688 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1689 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1690
1691 /* Set base offset as current */
1692 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1693}
1694
1695/* Find parser flow entry */
1696static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1697{
1698 struct mvpp2_prs_entry *pe;
1699 int tid;
1700
1701 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1702 if (!pe)
1703 return NULL;
1704 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1705
1706 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1707 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1708 u8 bits;
1709
1710 if (!priv->prs_shadow[tid].valid ||
1711 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1712 continue;
1713
1714 pe->index = tid;
1715 mvpp2_prs_hw_read(priv, pe);
1716 bits = mvpp2_prs_sram_ai_get(pe);
1717
1718 /* Sram store classification lookup ID in AI bits [5:0] */
1719 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1720 return pe;
1721 }
1722 kfree(pe);
1723
1724 return NULL;
1725}
1726
1727/* Return first free tcam index, seeking from start to end */
1728static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1729 unsigned char end)
1730{
1731 int tid;
1732
1733 if (start > end)
1734 swap(start, end);
1735
1736 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1737 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1738
1739 for (tid = start; tid <= end; tid++) {
1740 if (!priv->prs_shadow[tid].valid)
1741 return tid;
1742 }
1743
1744 return -EINVAL;
1745}
1746
1747/* Enable/disable dropping all mac da's */
1748static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1749{
1750 struct mvpp2_prs_entry pe;
1751
1752 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1753 /* Entry exist - update port only */
1754 pe.index = MVPP2_PE_DROP_ALL;
1755 mvpp2_prs_hw_read(priv, &pe);
1756 } else {
1757 /* Entry doesn't exist - create new */
1758 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1759 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1760 pe.index = MVPP2_PE_DROP_ALL;
1761
1762 /* Non-promiscuous mode for all ports - DROP unknown packets */
1763 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1764 MVPP2_PRS_RI_DROP_MASK);
1765
1766 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1767 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1768
1769 /* Update shadow table */
1770 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1771
1772 /* Mask all ports */
1773 mvpp2_prs_tcam_port_map_set(&pe, 0);
1774 }
1775
1776 /* Update port mask */
1777 mvpp2_prs_tcam_port_set(&pe, port, add);
1778
1779 mvpp2_prs_hw_write(priv, &pe);
1780}
1781
1782/* Set port to promiscuous mode */
1783static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1784{
1785 struct mvpp2_prs_entry pe;
1786
1787 /* Promiscuous mode - Accept unknown packets */
1788
1789 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1790 /* Entry exist - update port only */
1791 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1792 mvpp2_prs_hw_read(priv, &pe);
1793 } else {
1794 /* Entry doesn't exist - create new */
1795 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1796 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1797 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1798
1799 /* Continue - set next lookup */
1800 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1801
1802 /* Set result info bits */
1803 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1804 MVPP2_PRS_RI_L2_CAST_MASK);
1805
1806 /* Shift to ethertype */
1807 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1808 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1809
1810 /* Mask all ports */
1811 mvpp2_prs_tcam_port_map_set(&pe, 0);
1812
1813 /* Update shadow table */
1814 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1815 }
1816
1817 /* Update port mask */
1818 mvpp2_prs_tcam_port_set(&pe, port, add);
1819
1820 mvpp2_prs_hw_write(priv, &pe);
1821}
1822
1823/* Accept multicast */
1824static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1825 bool add)
1826{
1827 struct mvpp2_prs_entry pe;
1828 unsigned char da_mc;
1829
1830 /* Ethernet multicast address first byte is
1831 * 0x01 for IPv4 and 0x33 for IPv6
1832 */
1833 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1834
1835 if (priv->prs_shadow[index].valid) {
1836 /* Entry exist - update port only */
1837 pe.index = index;
1838 mvpp2_prs_hw_read(priv, &pe);
1839 } else {
1840 /* Entry doesn't exist - create new */
1841 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1842 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1843 pe.index = index;
1844
1845 /* Continue - set next lookup */
1846 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1847
1848 /* Set result info bits */
1849 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1850 MVPP2_PRS_RI_L2_CAST_MASK);
1851
1852 /* Update tcam entry data first byte */
1853 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1854
1855 /* Shift to ethertype */
1856 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1857 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1858
1859 /* Mask all ports */
1860 mvpp2_prs_tcam_port_map_set(&pe, 0);
1861
1862 /* Update shadow table */
1863 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1864 }
1865
1866 /* Update port mask */
1867 mvpp2_prs_tcam_port_set(&pe, port, add);
1868
1869 mvpp2_prs_hw_write(priv, &pe);
1870}
1871
1872/* Parser per-port initialization */
1873static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1874 int lu_max, int offset)
1875{
1876 u32 val;
1877
1878 /* Set lookup ID */
1879 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1880 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1881 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1882 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1883
1884 /* Set maximum number of loops for packet received from port */
1885 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1886 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1887 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1888 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1889
1890 /* Set initial offset for packet header extraction for the first
1891 * searching loop
1892 */
1893 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1894 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1895 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1896 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1897}
1898
1899/* Default flow entries initialization for all ports */
1900static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1901{
1902 struct mvpp2_prs_entry pe;
1903 int port;
1904
1905 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1906 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1907 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1908 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1909
1910 /* Mask all ports */
1911 mvpp2_prs_tcam_port_map_set(&pe, 0);
1912
1913 /* Set flow ID*/
1914 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1915 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1916
1917 /* Update shadow table and hw entry */
1918 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1919 mvpp2_prs_hw_write(priv, &pe);
1920 }
1921}
1922
1923/* Set default entry for Marvell Header field */
1924static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1925{
1926 struct mvpp2_prs_entry pe;
1927
1928 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1929
1930 pe.index = MVPP2_PE_MH_DEFAULT;
1931 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1932 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1933 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1934 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1935
1936 /* Unmask all ports */
1937 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1938
1939 /* Update shadow table and hw entry */
1940 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1941 mvpp2_prs_hw_write(priv, &pe);
1942}
1943
1944/* Set default entires (place holder) for promiscuous, non-promiscuous and
1945 * multicast MAC addresses
1946 */
1947static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1948{
1949 struct mvpp2_prs_entry pe;
1950
1951 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1952
1953 /* Non-promiscuous mode for all ports - DROP unknown packets */
1954 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1955 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1956
1957 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1958 MVPP2_PRS_RI_DROP_MASK);
1959 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1960 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1961
1962 /* Unmask all ports */
1963 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1964
1965 /* Update shadow table and hw entry */
1966 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1967 mvpp2_prs_hw_write(priv, &pe);
1968
1969 /* place holders only - no ports */
1970 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1971 mvpp2_prs_mac_promisc_set(priv, 0, false);
1972 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1973 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1974}
1975
1976/* Match basic ethertypes */
1977static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1978{
1979 struct mvpp2_prs_entry pe;
1980 int tid;
1981
1982 /* Ethertype: PPPoE */
1983 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1984 MVPP2_PE_LAST_FREE_TID);
1985 if (tid < 0)
1986 return tid;
1987
1988 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1989 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1990 pe.index = tid;
1991
1992 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1993
1994 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1995 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1996 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1997 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1998 MVPP2_PRS_RI_PPPOE_MASK);
1999
2000 /* Update shadow table and hw entry */
2001 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2002 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2003 priv->prs_shadow[pe.index].finish = false;
2004 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2005 MVPP2_PRS_RI_PPPOE_MASK);
2006 mvpp2_prs_hw_write(priv, &pe);
2007
2008 /* Ethertype: ARP */
2009 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2010 MVPP2_PE_LAST_FREE_TID);
2011 if (tid < 0)
2012 return tid;
2013
2014 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2015 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2016 pe.index = tid;
2017
2018 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2019
2020 /* Generate flow in the next iteration*/
2021 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2022 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2023 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2024 MVPP2_PRS_RI_L3_PROTO_MASK);
2025 /* Set L3 offset */
2026 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2027 MVPP2_ETH_TYPE_LEN,
2028 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2029
2030 /* Update shadow table and hw entry */
2031 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2032 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2033 priv->prs_shadow[pe.index].finish = true;
2034 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2035 MVPP2_PRS_RI_L3_PROTO_MASK);
2036 mvpp2_prs_hw_write(priv, &pe);
2037
2038 /* Ethertype: LBTD */
2039 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2040 MVPP2_PE_LAST_FREE_TID);
2041 if (tid < 0)
2042 return tid;
2043
2044 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2045 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2046 pe.index = tid;
2047
2048 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2049
2050 /* Generate flow in the next iteration*/
2051 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2052 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2054 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2055 MVPP2_PRS_RI_CPU_CODE_MASK |
2056 MVPP2_PRS_RI_UDF3_MASK);
2057 /* Set L3 offset */
2058 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2059 MVPP2_ETH_TYPE_LEN,
2060 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2061
2062 /* Update shadow table and hw entry */
2063 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2064 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2065 priv->prs_shadow[pe.index].finish = true;
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2067 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2068 MVPP2_PRS_RI_CPU_CODE_MASK |
2069 MVPP2_PRS_RI_UDF3_MASK);
2070 mvpp2_prs_hw_write(priv, &pe);
2071
2072 /* Ethertype: IPv4 without options */
2073 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2074 MVPP2_PE_LAST_FREE_TID);
2075 if (tid < 0)
2076 return tid;
2077
2078 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2079 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2080 pe.index = tid;
2081
2082 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2083 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2084 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2085 MVPP2_PRS_IPV4_HEAD_MASK |
2086 MVPP2_PRS_IPV4_IHL_MASK);
2087
2088 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2089 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2090 MVPP2_PRS_RI_L3_PROTO_MASK);
2091 /* Skip eth_type + 4 bytes of IP header */
2092 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2093 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2094 /* Set L3 offset */
2095 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2096 MVPP2_ETH_TYPE_LEN,
2097 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2098
2099 /* Update shadow table and hw entry */
2100 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2101 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2102 priv->prs_shadow[pe.index].finish = false;
2103 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2104 MVPP2_PRS_RI_L3_PROTO_MASK);
2105 mvpp2_prs_hw_write(priv, &pe);
2106
2107 /* Ethertype: IPv4 with options */
2108 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2109 MVPP2_PE_LAST_FREE_TID);
2110 if (tid < 0)
2111 return tid;
2112
2113 pe.index = tid;
2114
2115 /* Clear tcam data before updating */
2116 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2117 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2118
2119 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2120 MVPP2_PRS_IPV4_HEAD,
2121 MVPP2_PRS_IPV4_HEAD_MASK);
2122
2123 /* Clear ri before updating */
2124 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2125 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2126 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2127 MVPP2_PRS_RI_L3_PROTO_MASK);
2128
2129 /* Update shadow table and hw entry */
2130 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2131 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2132 priv->prs_shadow[pe.index].finish = false;
2133 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2134 MVPP2_PRS_RI_L3_PROTO_MASK);
2135 mvpp2_prs_hw_write(priv, &pe);
2136
2137 /* Ethertype: IPv6 without options */
2138 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2139 MVPP2_PE_LAST_FREE_TID);
2140 if (tid < 0)
2141 return tid;
2142
2143 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2144 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2145 pe.index = tid;
2146
2147 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2148
2149 /* Skip DIP of IPV6 header */
2150 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2151 MVPP2_MAX_L3_ADDR_SIZE,
2152 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2153 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2154 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2155 MVPP2_PRS_RI_L3_PROTO_MASK);
2156 /* Set L3 offset */
2157 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2158 MVPP2_ETH_TYPE_LEN,
2159 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2160
2161 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2162 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2163 priv->prs_shadow[pe.index].finish = false;
2164 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2165 MVPP2_PRS_RI_L3_PROTO_MASK);
2166 mvpp2_prs_hw_write(priv, &pe);
2167
2168 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2169 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2170 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2171 pe.index = MVPP2_PE_ETH_TYPE_UN;
2172
2173 /* Unmask all ports */
2174 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2175
2176 /* Generate flow in the next iteration*/
2177 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2178 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2179 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2180 MVPP2_PRS_RI_L3_PROTO_MASK);
2181 /* Set L3 offset even it's unknown L3 */
2182 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2183 MVPP2_ETH_TYPE_LEN,
2184 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2185
2186 /* Update shadow table and hw entry */
2187 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2188 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2189 priv->prs_shadow[pe.index].finish = true;
2190 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2191 MVPP2_PRS_RI_L3_PROTO_MASK);
2192 mvpp2_prs_hw_write(priv, &pe);
2193
2194 return 0;
2195}
2196
2197/* Parser default initialization */
2198static int mvpp2_prs_default_init(struct udevice *dev,
2199 struct mvpp2 *priv)
2200{
2201 int err, index, i;
2202
2203 /* Enable tcam table */
2204 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2205
2206 /* Clear all tcam and sram entries */
2207 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2208 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2209 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2210 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2211
2212 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2213 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2215 }
2216
2217 /* Invalidate all tcam entries */
2218 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2219 mvpp2_prs_hw_inv(priv, index);
2220
2221 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2222 sizeof(struct mvpp2_prs_shadow),
2223 GFP_KERNEL);
2224 if (!priv->prs_shadow)
2225 return -ENOMEM;
2226
2227 /* Always start from lookup = 0 */
2228 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2229 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2230 MVPP2_PRS_PORT_LU_MAX, 0);
2231
2232 mvpp2_prs_def_flow_init(priv);
2233
2234 mvpp2_prs_mh_init(priv);
2235
2236 mvpp2_prs_mac_init(priv);
2237
2238 err = mvpp2_prs_etype_init(priv);
2239 if (err)
2240 return err;
2241
2242 return 0;
2243}
2244
2245/* Compare MAC DA with tcam entry data */
2246static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2247 const u8 *da, unsigned char *mask)
2248{
2249 unsigned char tcam_byte, tcam_mask;
2250 int index;
2251
2252 for (index = 0; index < ETH_ALEN; index++) {
2253 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2254 if (tcam_mask != mask[index])
2255 return false;
2256
2257 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2258 return false;
2259 }
2260
2261 return true;
2262}
2263
2264/* Find tcam entry with matched pair <MAC DA, port> */
2265static struct mvpp2_prs_entry *
2266mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2267 unsigned char *mask, int udf_type)
2268{
2269 struct mvpp2_prs_entry *pe;
2270 int tid;
2271
2272 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2273 if (!pe)
2274 return NULL;
2275 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2276
2277 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2278 for (tid = MVPP2_PE_FIRST_FREE_TID;
2279 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2280 unsigned int entry_pmap;
2281
2282 if (!priv->prs_shadow[tid].valid ||
2283 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2284 (priv->prs_shadow[tid].udf != udf_type))
2285 continue;
2286
2287 pe->index = tid;
2288 mvpp2_prs_hw_read(priv, pe);
2289 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2290
2291 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2292 entry_pmap == pmap)
2293 return pe;
2294 }
2295 kfree(pe);
2296
2297 return NULL;
2298}
2299
2300/* Update parser's mac da entry */
2301static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2302 const u8 *da, bool add)
2303{
2304 struct mvpp2_prs_entry *pe;
2305 unsigned int pmap, len, ri;
2306 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2307 int tid;
2308
2309 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2310 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2311 MVPP2_PRS_UDF_MAC_DEF);
2312
2313 /* No such entry */
2314 if (!pe) {
2315 if (!add)
2316 return 0;
2317
2318 /* Create new TCAM entry */
2319 /* Find first range mac entry*/
2320 for (tid = MVPP2_PE_FIRST_FREE_TID;
2321 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2322 if (priv->prs_shadow[tid].valid &&
2323 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2324 (priv->prs_shadow[tid].udf ==
2325 MVPP2_PRS_UDF_MAC_RANGE))
2326 break;
2327
2328 /* Go through the all entries from first to last */
2329 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2330 tid - 1);
2331 if (tid < 0)
2332 return tid;
2333
2334 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2335 if (!pe)
2336 return -1;
2337 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2338 pe->index = tid;
2339
2340 /* Mask all ports */
2341 mvpp2_prs_tcam_port_map_set(pe, 0);
2342 }
2343
2344 /* Update port mask */
2345 mvpp2_prs_tcam_port_set(pe, port, add);
2346
2347 /* Invalidate the entry if no ports are left enabled */
2348 pmap = mvpp2_prs_tcam_port_map_get(pe);
2349 if (pmap == 0) {
2350 if (add) {
2351 kfree(pe);
2352 return -1;
2353 }
2354 mvpp2_prs_hw_inv(priv, pe->index);
2355 priv->prs_shadow[pe->index].valid = false;
2356 kfree(pe);
2357 return 0;
2358 }
2359
2360 /* Continue - set next lookup */
2361 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2362
2363 /* Set match on DA */
2364 len = ETH_ALEN;
2365 while (len--)
2366 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2367
2368 /* Set result info bits */
2369 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2370
2371 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2372 MVPP2_PRS_RI_MAC_ME_MASK);
2373 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2374 MVPP2_PRS_RI_MAC_ME_MASK);
2375
2376 /* Shift to ethertype */
2377 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2378 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2379
2380 /* Update shadow table and hw entry */
2381 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2382 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2383 mvpp2_prs_hw_write(priv, pe);
2384
2385 kfree(pe);
2386
2387 return 0;
2388}
2389
2390static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2391{
2392 int err;
2393
2394 /* Remove old parser entry */
2395 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2396 false);
2397 if (err)
2398 return err;
2399
2400 /* Add new parser entry */
2401 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2402 if (err)
2403 return err;
2404
2405 /* Set addr in the device */
2406 memcpy(port->dev_addr, da, ETH_ALEN);
2407
2408 return 0;
2409}
2410
2411/* Set prs flow for the port */
2412static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2413{
2414 struct mvpp2_prs_entry *pe;
2415 int tid;
2416
2417 pe = mvpp2_prs_flow_find(port->priv, port->id);
2418
2419 /* Such entry not exist */
2420 if (!pe) {
2421 /* Go through the all entires from last to first */
2422 tid = mvpp2_prs_tcam_first_free(port->priv,
2423 MVPP2_PE_LAST_FREE_TID,
2424 MVPP2_PE_FIRST_FREE_TID);
2425 if (tid < 0)
2426 return tid;
2427
2428 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2429 if (!pe)
2430 return -ENOMEM;
2431
2432 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2433 pe->index = tid;
2434
2435 /* Set flow ID*/
2436 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2437 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2438
2439 /* Update shadow table */
2440 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2441 }
2442
2443 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2444 mvpp2_prs_hw_write(port->priv, pe);
2445 kfree(pe);
2446
2447 return 0;
2448}
2449
2450/* Classifier configuration routines */
2451
2452/* Update classification flow table registers */
2453static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2454 struct mvpp2_cls_flow_entry *fe)
2455{
2456 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2457 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2458 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2459 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2460}
2461
2462/* Update classification lookup table register */
2463static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2464 struct mvpp2_cls_lookup_entry *le)
2465{
2466 u32 val;
2467
2468 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2469 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2470 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2471}
2472
2473/* Classifier default initialization */
2474static void mvpp2_cls_init(struct mvpp2 *priv)
2475{
2476 struct mvpp2_cls_lookup_entry le;
2477 struct mvpp2_cls_flow_entry fe;
2478 int index;
2479
2480 /* Enable classifier */
2481 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2482
2483 /* Clear classifier flow table */
2484 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2485 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2486 fe.index = index;
2487 mvpp2_cls_flow_write(priv, &fe);
2488 }
2489
2490 /* Clear classifier lookup table */
2491 le.data = 0;
2492 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2493 le.lkpid = index;
2494 le.way = 0;
2495 mvpp2_cls_lookup_write(priv, &le);
2496
2497 le.way = 1;
2498 mvpp2_cls_lookup_write(priv, &le);
2499 }
2500}
2501
2502static void mvpp2_cls_port_config(struct mvpp2_port *port)
2503{
2504 struct mvpp2_cls_lookup_entry le;
2505 u32 val;
2506
2507 /* Set way for the port */
2508 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2509 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2510 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2511
2512 /* Pick the entry to be accessed in lookup ID decoding table
2513 * according to the way and lkpid.
2514 */
2515 le.lkpid = port->id;
2516 le.way = 0;
2517 le.data = 0;
2518
2519 /* Set initial CPU queue for receiving packets */
2520 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2521 le.data |= port->first_rxq;
2522
2523 /* Disable classification engines */
2524 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2525
2526 /* Update lookup ID table entry */
2527 mvpp2_cls_lookup_write(port->priv, &le);
2528}
2529
2530/* Set CPU queue number for oversize packets */
2531static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2532{
2533 u32 val;
2534
2535 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2536 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2537
2538 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2539 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2540
2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2542 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2544}
2545
2546/* Buffer Manager configuration routines */
2547
2548/* Create pool */
2549static int mvpp2_bm_pool_create(struct udevice *dev,
2550 struct mvpp2 *priv,
2551 struct mvpp2_bm_pool *bm_pool, int size)
2552{
2553 u32 val;
2554
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002555 /* Number of buffer pointers must be a multiple of 16, as per
2556 * hardware constraints
2557 */
2558 if (!IS_ALIGNED(size, 16))
2559 return -EINVAL;
2560
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002561 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002562 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002563 if (!bm_pool->virt_addr)
2564 return -ENOMEM;
2565
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002566 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2567 MVPP2_BM_POOL_PTR_ALIGN)) {
Sean Andersonddc48c12020-09-15 10:44:56 -04002568 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002569 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2570 return -ENOMEM;
2571 }
2572
2573 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002574 lower_32_bits(bm_pool->dma_addr));
Stefan Chulski783e7852017-08-09 10:37:50 +03002575 if (priv->hw_version == MVPP22)
2576 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
2577 (upper_32_bits(bm_pool->dma_addr) &
2578 MVPP22_BM_POOL_BASE_HIGH_MASK));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002579 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2580
2581 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2582 val |= MVPP2_BM_START_MASK;
2583 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2584
2585 bm_pool->type = MVPP2_BM_FREE;
2586 bm_pool->size = size;
2587 bm_pool->pkt_size = 0;
2588 bm_pool->buf_num = 0;
2589
2590 return 0;
2591}
2592
2593/* Set pool buffer size */
2594static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2595 struct mvpp2_bm_pool *bm_pool,
2596 int buf_size)
2597{
2598 u32 val;
2599
2600 bm_pool->buf_size = buf_size;
2601
2602 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2603 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2604}
2605
2606/* Free all buffers from the pool */
2607static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2608 struct mvpp2_bm_pool *bm_pool)
2609{
Stefan Roese2f720f12017-03-23 17:01:59 +01002610 int i;
2611
2612 for (i = 0; i < bm_pool->buf_num; i++) {
2613 /* Allocate buffer back from the buffer manager */
2614 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2615 }
2616
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002617 bm_pool->buf_num = 0;
2618}
2619
2620/* Cleanup pool */
2621static int mvpp2_bm_pool_destroy(struct udevice *dev,
2622 struct mvpp2 *priv,
2623 struct mvpp2_bm_pool *bm_pool)
2624{
2625 u32 val;
2626
2627 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2628 if (bm_pool->buf_num) {
2629 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2630 return 0;
2631 }
2632
2633 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2634 val |= MVPP2_BM_STOP_MASK;
2635 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2636
2637 return 0;
2638}
2639
2640static int mvpp2_bm_pools_init(struct udevice *dev,
2641 struct mvpp2 *priv)
2642{
2643 int i, err, size;
2644 struct mvpp2_bm_pool *bm_pool;
2645
2646 /* Create all pools with maximum size */
2647 size = MVPP2_BM_POOL_SIZE_MAX;
2648 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2649 bm_pool = &priv->bm_pools[i];
2650 bm_pool->id = i;
2651 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2652 if (err)
2653 goto err_unroll_pools;
Stefan Chulskiceec6c42017-08-09 10:37:52 +03002654 mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002655 }
2656 return 0;
2657
2658err_unroll_pools:
Sean Andersonddc48c12020-09-15 10:44:56 -04002659 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002660 for (i = i - 1; i >= 0; i--)
2661 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2662 return err;
2663}
2664
2665static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2666{
2667 int i, err;
2668
2669 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2670 /* Mask BM all interrupts */
2671 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2672 /* Clear BM cause register */
2673 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2674 }
2675
2676 /* Allocate and initialize BM pools */
2677 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2678 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2679 if (!priv->bm_pools)
2680 return -ENOMEM;
2681
2682 err = mvpp2_bm_pools_init(dev, priv);
2683 if (err < 0)
2684 return err;
2685 return 0;
2686}
2687
2688/* Attach long pool to rxq */
2689static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2690 int lrxq, int long_pool)
2691{
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002692 u32 val, mask;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002693 int prxq;
2694
2695 /* Get queue physical ID */
2696 prxq = port->rxqs[lrxq]->id;
2697
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002698 if (port->priv->hw_version == MVPP21)
2699 mask = MVPP21_RXQ_POOL_LONG_MASK;
2700 else
2701 mask = MVPP22_RXQ_POOL_LONG_MASK;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002702
Thomas Petazzoni8f3e4c32017-02-16 06:53:51 +01002703 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2704 val &= ~mask;
2705 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002706 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2707}
2708
2709/* Set pool number in a BM cookie */
2710static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2711{
2712 u32 bm;
2713
2714 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2715 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2716
2717 return bm;
2718}
2719
2720/* Get pool number from a BM cookie */
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002721static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002722{
2723 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2724}
2725
2726/* Release buffer to BM */
2727static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002728 dma_addr_t buf_dma_addr,
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002729 unsigned long buf_phys_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002730{
Thomas Petazzonic8feeb22017-02-20 11:29:16 +01002731 if (port->priv->hw_version == MVPP22) {
2732 u32 val = 0;
2733
2734 if (sizeof(dma_addr_t) == 8)
2735 val |= upper_32_bits(buf_dma_addr) &
2736 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2737
2738 if (sizeof(phys_addr_t) == 8)
2739 val |= (upper_32_bits(buf_phys_addr)
2740 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2741 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2742
2743 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2744 }
2745
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002746 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2747 * returned in the "cookie" field of the RX
2748 * descriptor. Instead of storing the virtual address, we
2749 * store the physical address
2750 */
2751 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002752 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002753}
2754
2755/* Refill BM pool */
2756static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01002757 dma_addr_t dma_addr,
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002758 phys_addr_t phys_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002759{
2760 int pool = mvpp2_bm_cookie_pool_get(bm);
2761
Thomas Petazzonicd9ee192017-02-20 10:37:59 +01002762 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002763}
2764
2765/* Allocate buffers for the pool */
2766static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2767 struct mvpp2_bm_pool *bm_pool, int buf_num)
2768{
2769 int i;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002770
2771 if (buf_num < 0 ||
2772 (buf_num + bm_pool->buf_num > bm_pool->size)) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04002773 dev_err(port->phy_dev->dev,
2774 "cannot allocate %d buffers for pool %d\n", buf_num,
2775 bm_pool->id);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002776 return 0;
2777 }
2778
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002779 for (i = 0; i < buf_num; i++) {
Thomas Petazzonif1060f02017-02-15 12:13:43 +01002780 mvpp2_bm_pool_put(port, bm_pool->id,
Thomas Petazzonid1d075a2017-02-15 12:31:53 +01002781 (dma_addr_t)buffer_loc.rx_buffer[i],
2782 (unsigned long)buffer_loc.rx_buffer[i]);
Thomas Petazzonif1060f02017-02-15 12:13:43 +01002783
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002784 }
2785
2786 /* Update BM driver with number of buffers added to pool */
2787 bm_pool->buf_num += i;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002788
2789 return i;
2790}
2791
2792/* Notify the driver that BM pool is being used as specific type and return the
2793 * pool pointer on success
2794 */
2795static struct mvpp2_bm_pool *
2796mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2797 int pkt_size)
2798{
2799 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2800 int num;
2801
2802 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04002803 dev_err(port->phy_dev->dev, "mixing pool types is forbidden\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002804 return NULL;
2805 }
2806
2807 if (new_pool->type == MVPP2_BM_FREE)
2808 new_pool->type = type;
2809
2810 /* Allocate buffers in case BM pool is used as long pool, but packet
2811 * size doesn't match MTU or BM pool hasn't being used yet
2812 */
2813 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2814 (new_pool->pkt_size == 0)) {
2815 int pkts_num;
2816
2817 /* Set default buffer number or free all the buffers in case
2818 * the pool is not empty
2819 */
2820 pkts_num = new_pool->buf_num;
2821 if (pkts_num == 0)
2822 pkts_num = type == MVPP2_BM_SWF_LONG ?
2823 MVPP2_BM_LONG_BUF_NUM :
2824 MVPP2_BM_SHORT_BUF_NUM;
2825 else
2826 mvpp2_bm_bufs_free(NULL,
2827 port->priv, new_pool);
2828
2829 new_pool->pkt_size = pkt_size;
2830
2831 /* Allocate buffers for this pool */
2832 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2833 if (num != pkts_num) {
Sean Andersonddc48c12020-09-15 10:44:56 -04002834 dev_err(port->phy_dev->dev,
2835 "pool %d: %d of %d allocated\n", new_pool->id,
2836 num, pkts_num);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002837 return NULL;
2838 }
2839 }
2840
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002841 return new_pool;
2842}
2843
2844/* Initialize pools for swf */
2845static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2846{
2847 int rxq;
2848
2849 if (!port->pool_long) {
2850 port->pool_long =
2851 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2852 MVPP2_BM_SWF_LONG,
2853 port->pkt_size);
2854 if (!port->pool_long)
2855 return -ENOMEM;
2856
2857 port->pool_long->port_map |= (1 << port->id);
2858
2859 for (rxq = 0; rxq < rxq_number; rxq++)
2860 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2861 }
2862
2863 return 0;
2864}
2865
2866/* Port configuration routines */
2867
2868static void mvpp2_port_mii_set(struct mvpp2_port *port)
2869{
2870 u32 val;
2871
2872 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2873
2874 switch (port->phy_interface) {
2875 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02002876 case PHY_INTERFACE_MODE_SGMII_2500:
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002877 val |= MVPP2_GMAC_INBAND_AN_MASK;
2878 break;
Stefan Chulski8299abc2021-05-03 08:08:46 +02002879 case PHY_INTERFACE_MODE_1000BASEX:
2880 case PHY_INTERFACE_MODE_2500BASEX:
2881 val &= ~MVPP2_GMAC_INBAND_AN_MASK;
2882 break;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002883 case PHY_INTERFACE_MODE_RGMII:
Stefan Roese025e5922017-03-22 15:11:00 +01002884 case PHY_INTERFACE_MODE_RGMII_ID:
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002885 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2886 default:
2887 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2888 }
2889
2890 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2891}
2892
2893static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2894{
2895 u32 val;
2896
2897 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2898 val |= MVPP2_GMAC_FC_ADV_EN;
2899 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2900}
2901
2902static void mvpp2_port_enable(struct mvpp2_port *port)
2903{
2904 u32 val;
2905
2906 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2907 val |= MVPP2_GMAC_PORT_EN_MASK;
2908 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2909 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2910}
2911
2912static void mvpp2_port_disable(struct mvpp2_port *port)
2913{
2914 u32 val;
2915
2916 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2917 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2918 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2919}
2920
2921/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2922static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2923{
2924 u32 val;
2925
2926 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2927 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2928 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2929}
2930
2931/* Configure loopback port */
2932static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2933{
2934 u32 val;
2935
2936 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2937
2938 if (port->speed == 1000)
2939 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2940 else
2941 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2942
Stefan Chulski8299abc2021-05-03 08:08:46 +02002943 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
Marcin Wojtasd24efc62021-05-03 08:08:53 +02002944 port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
Stefan Chulski8299abc2021-05-03 08:08:46 +02002945 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2946 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01002947 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2948 else
2949 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2950
2951 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2952}
2953
2954static void mvpp2_port_reset(struct mvpp2_port *port)
2955{
2956 u32 val;
2957
2958 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2959 ~MVPP2_GMAC_PORT_RESET_MASK;
2960 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2961
2962 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2963 MVPP2_GMAC_PORT_RESET_MASK)
2964 continue;
2965}
2966
2967/* Change maximum receive size of the port */
2968static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2969{
2970 u32 val;
2971
2972 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2973 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2974 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2975 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2976 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2977}
2978
Stefan Roese31aa1e32017-03-22 15:07:30 +01002979/* PPv2.2 GoP/GMAC config */
2980
2981/* Set the MAC to reset or exit from reset */
2982static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2983{
2984 u32 val;
2985
2986 /* read - modify - write */
2987 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2988 if (reset)
2989 val |= MVPP2_GMAC_PORT_RESET_MASK;
2990 else
2991 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2992 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2993
2994 return 0;
2995}
2996
2997/*
2998 * gop_gpcs_mode_cfg
2999 *
3000 * Configure port to working with Gig PCS or don't.
3001 */
3002static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
3003{
3004 u32 val;
3005
3006 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3007 if (en)
3008 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
3009 else
3010 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3011 /* enable / disable PCS on this port */
3012 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3013
3014 return 0;
3015}
3016
3017static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3018{
3019 u32 val;
3020
3021 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3022 if (en)
3023 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3024 else
3025 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3026 /* enable / disable PCS on this port */
3027 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3028
3029 return 0;
3030}
3031
3032static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3033{
3034 u32 val, thresh;
3035
3036 /*
3037 * Configure minimal level of the Tx FIFO before the lower part
3038 * starts to read a packet
3039 */
3040 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3041 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3042 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3043 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3044 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3045
3046 /* Disable bypass of sync module */
3047 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3048 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3049 /* configure DP clock select according to mode */
3050 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3051 /* configure QSGMII bypass according to mode */
3052 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3053 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3054
Stefan Roese31aa1e32017-03-22 15:07:30 +01003055 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3056 /*
Stefan Chulski8299abc2021-05-03 08:08:46 +02003057 * Configure GIG MAC to SGMII mode connected to a fiber
Stefan Roese31aa1e32017-03-22 15:07:30 +01003058 * transceiver
3059 */
Stefan Chulski8299abc2021-05-03 08:08:46 +02003060 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003061 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3062
3063 /* configure AN 0x9268 */
3064 val = MVPP2_GMAC_EN_PCS_AN |
3065 MVPP2_GMAC_AN_BYPASS_EN |
3066 MVPP2_GMAC_CONFIG_MII_SPEED |
3067 MVPP2_GMAC_CONFIG_GMII_SPEED |
3068 MVPP2_GMAC_FC_ADV_EN |
3069 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3070 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3071 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3072}
3073
3074static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3075{
3076 u32 val, thresh;
3077
3078 /*
3079 * Configure minimal level of the Tx FIFO before the lower part
3080 * starts to read a packet
3081 */
3082 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3083 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3084 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3085 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3086 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3087
3088 /* Disable bypass of sync module */
3089 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3090 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3091 /* configure DP clock select according to mode */
3092 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3093 /* configure QSGMII bypass according to mode */
3094 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3095 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3096
Stefan Roese31aa1e32017-03-22 15:07:30 +01003097 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3098 /* configure GIG MAC to SGMII mode */
3099 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3100 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3101
3102 /* configure AN */
3103 val = MVPP2_GMAC_EN_PCS_AN |
3104 MVPP2_GMAC_AN_BYPASS_EN |
3105 MVPP2_GMAC_AN_SPEED_EN |
3106 MVPP2_GMAC_EN_FC_AN |
3107 MVPP2_GMAC_AN_DUPLEX_EN |
3108 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3109 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3110}
3111
Stefan Chulski8299abc2021-05-03 08:08:46 +02003112static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
3113{
3114 u32 val, thresh;
3115
3116 /*
3117 * Configure minimal level of the Tx FIFO before the lower part
3118 * starts to read a packet
3119 */
3120 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3121 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3122 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3123 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3124 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3125
3126 /* Disable bypass of sync module */
3127 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3128 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3129 /* configure DP clock select according to mode */
3130 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3131 /* configure QSGMII bypass according to mode */
3132 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3133 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3134
3135 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3136 /*
3137 * Configure GIG MAC to 2500Base-X mode connected to a fiber
3138 * transceiver
3139 */
3140 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3141 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3142
3143 /* In 2500BaseX mode, we can't negotiate speed
3144 * and we do not want InBand autoneg
3145 * bypass enabled (link interrupt storm risk
3146 * otherwise).
3147 */
Ben Peled7589be82021-05-03 08:08:49 +02003148 val = MVPP2_GMAC_AN_BYPASS_EN |
3149 MVPP2_GMAC_EN_PCS_AN |
Stefan Chulski8299abc2021-05-03 08:08:46 +02003150 MVPP2_GMAC_CONFIG_GMII_SPEED |
3151 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3152 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3153 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3154}
3155
3156static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
3157{
3158 u32 val, thresh;
3159
3160 /*
3161 * Configure minimal level of the Tx FIFO before the lower part
3162 * starts to read a packet
3163 */
3164 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3165 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3166 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3167 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3168 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3169
3170 /* Disable bypass of sync module */
3171 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3172 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3173 /* configure DP clock select according to mode */
3174 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3175 /* configure QSGMII bypass according to mode */
3176 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3177 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3178
3179 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3180 /* configure GIG MAC to 1000BASEX mode */
3181 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3182 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3183
3184 /* In 1000BaseX mode, we can't negotiate speed (it's
3185 * only 1000), and we do not want InBand autoneg
3186 * bypass enabled (link interrupt storm risk
3187 * otherwise).
3188 */
Ben Peled7589be82021-05-03 08:08:49 +02003189 val = MVPP2_GMAC_AN_BYPASS_EN |
3190 MVPP2_GMAC_EN_PCS_AN |
Stefan Chulski8299abc2021-05-03 08:08:46 +02003191 MVPP2_GMAC_CONFIG_GMII_SPEED |
3192 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3193 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3194 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3195}
3196
Stefan Roese31aa1e32017-03-22 15:07:30 +01003197static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3198{
3199 u32 val, thresh;
3200
3201 /*
3202 * Configure minimal level of the Tx FIFO before the lower part
3203 * starts to read a packet
3204 */
3205 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3206 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3207 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3208 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3209 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3210
3211 /* Disable bypass of sync module */
3212 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3213 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3214 /* configure DP clock select according to mode */
3215 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3216 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3217 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3218 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3219
Stefan Roese31aa1e32017-03-22 15:07:30 +01003220 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3221 /* configure GIG MAC to SGMII mode */
3222 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3223 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3224
3225 /* configure AN 0xb8e8 */
3226 val = MVPP2_GMAC_AN_BYPASS_EN |
3227 MVPP2_GMAC_AN_SPEED_EN |
3228 MVPP2_GMAC_EN_FC_AN |
3229 MVPP2_GMAC_AN_DUPLEX_EN |
3230 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3231 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3232}
3233
3234/* Set the internal mux's to the required MAC in the GOP */
3235static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3236{
3237 u32 val;
3238
3239 /* Set TX FIFO thresholds */
3240 switch (port->phy_interface) {
3241 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003242 gop_gmac_sgmii_cfg(port);
Stefan Roese31aa1e32017-03-22 15:07:30 +01003243 break;
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003244 case PHY_INTERFACE_MODE_SGMII_2500:
3245 gop_gmac_sgmii2_5_cfg(port);
3246 break;
Stefan Chulski8299abc2021-05-03 08:08:46 +02003247 case PHY_INTERFACE_MODE_1000BASEX:
3248 gop_gmac_1000basex_cfg(port);
Ben Peledd757c852021-05-03 08:08:51 +02003249 break;
Stefan Chulski8299abc2021-05-03 08:08:46 +02003250
3251 case PHY_INTERFACE_MODE_2500BASEX:
3252 gop_gmac_2500basex_cfg(port);
Ben Peledd757c852021-05-03 08:08:51 +02003253 break;
Stefan Chulski8299abc2021-05-03 08:08:46 +02003254
Stefan Roese31aa1e32017-03-22 15:07:30 +01003255 case PHY_INTERFACE_MODE_RGMII:
3256 case PHY_INTERFACE_MODE_RGMII_ID:
3257 gop_gmac_rgmii_cfg(port);
3258 break;
3259
3260 default:
3261 return -1;
3262 }
3263
3264 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3265 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3266 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3267 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3268 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3269
3270 /* PeriodicXonEn disable */
3271 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3272 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3273 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3274
3275 return 0;
3276}
3277
3278static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3279{
3280 u32 val;
3281
3282 /* relevant only for MAC0 (XLG0 and GMAC0) */
3283 if (port->gop_id > 0)
3284 return;
3285
3286 /* configure 1Gig MAC mode */
3287 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3288 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3289 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3290 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3291}
3292
3293static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3294{
3295 u32 val;
3296
3297 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3298 if (reset)
3299 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3300 else
3301 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3302 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3303
3304 return 0;
3305}
3306
Stefan Roese2fe23042017-03-22 15:09:38 +01003307static int gop_mpcs_mode(struct mvpp2_port *port)
3308{
3309 u32 val;
3310
3311 /* configure PCS40G COMMON CONTROL */
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003312 val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
3313 PCS40G_COMMON_CONTROL);
Stefan Roese2fe23042017-03-22 15:09:38 +01003314 val &= ~FORWARD_ERROR_CORRECTION_MASK;
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003315 writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
3316 PCS40G_COMMON_CONTROL);
Stefan Roese2fe23042017-03-22 15:09:38 +01003317
3318 /* configure PCS CLOCK RESET */
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003319 val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
3320 PCS_CLOCK_RESET);
Stefan Roese2fe23042017-03-22 15:09:38 +01003321 val &= ~CLK_DIVISION_RATIO_MASK;
3322 val |= 1 << CLK_DIVISION_RATIO_OFFS;
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003323 writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
3324 PCS_CLOCK_RESET);
Stefan Roese2fe23042017-03-22 15:09:38 +01003325
3326 val &= ~CLK_DIV_PHASE_SET_MASK;
3327 val |= MAC_CLK_RESET_MASK;
3328 val |= RX_SD_CLK_RESET_MASK;
3329 val |= TX_SD_CLK_RESET_MASK;
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003330 writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
3331 PCS_CLOCK_RESET);
Stefan Roese2fe23042017-03-22 15:09:38 +01003332
3333 return 0;
3334}
3335
3336/* Set the internal mux's to the required MAC in the GOP */
3337static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3338{
3339 u32 val;
3340
3341 /* configure 10G MAC mode */
3342 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3343 val |= MVPP22_XLG_RX_FC_EN;
3344 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3345
3346 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3347 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3348 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3349 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3350
3351 /* read - modify - write */
3352 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3353 val &= ~MVPP22_XLG_MODE_DMA_1G;
3354 val |= MVPP22_XLG_FORWARD_PFC_EN;
3355 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3356 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3357 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3358
3359 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3360 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3361 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3362 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3363 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3364
3365 /* unmask link change interrupt */
3366 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3367 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3368 val |= 1; /* unmask summary bit */
3369 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3370
3371 return 0;
3372}
3373
Stefan Roese2fe23042017-03-22 15:09:38 +01003374/* Set the MAC to reset or exit from reset */
3375static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3376{
3377 u32 val;
3378
3379 /* read - modify - write */
3380 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3381 if (reset)
3382 val &= ~MVPP22_XLG_MAC_RESETN;
3383 else
3384 val |= MVPP22_XLG_MAC_RESETN;
3385 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3386
3387 return 0;
3388}
3389
Stefan Roese31aa1e32017-03-22 15:07:30 +01003390/*
3391 * gop_port_init
3392 *
3393 * Init physical port. Configures the port mode and all it's elements
3394 * accordingly.
3395 * Does not verify that the selected mode/port number is valid at the
3396 * core level.
3397 */
3398static int gop_port_init(struct mvpp2_port *port)
3399{
3400 int mac_num = port->gop_id;
Stefan Roese2fe23042017-03-22 15:09:38 +01003401 int num_of_act_lanes;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003402
3403 if (mac_num >= MVPP22_GOP_MAC_NUM) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04003404 log_err("illegal port number %d", mac_num);
Stefan Roese31aa1e32017-03-22 15:07:30 +01003405 return -1;
3406 }
3407
3408 switch (port->phy_interface) {
3409 case PHY_INTERFACE_MODE_RGMII:
3410 case PHY_INTERFACE_MODE_RGMII_ID:
3411 gop_gmac_reset(port, 1);
3412
3413 /* configure PCS */
3414 gop_gpcs_mode_cfg(port, 0);
3415 gop_bypass_clk_cfg(port, 1);
3416
3417 /* configure MAC */
3418 gop_gmac_mode_cfg(port);
3419 /* pcs unreset */
3420 gop_gpcs_reset(port, 0);
3421
3422 /* mac unreset */
3423 gop_gmac_reset(port, 0);
3424 break;
3425
3426 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003427 case PHY_INTERFACE_MODE_SGMII_2500:
Stefan Chulski8299abc2021-05-03 08:08:46 +02003428 case PHY_INTERFACE_MODE_1000BASEX:
3429 case PHY_INTERFACE_MODE_2500BASEX:
Stefan Roese31aa1e32017-03-22 15:07:30 +01003430 /* configure PCS */
3431 gop_gpcs_mode_cfg(port, 1);
3432
3433 /* configure MAC */
3434 gop_gmac_mode_cfg(port);
3435 /* select proper Mac mode */
3436 gop_xlg_2_gig_mac_cfg(port);
3437
3438 /* pcs unreset */
3439 gop_gpcs_reset(port, 0);
3440 /* mac unreset */
3441 gop_gmac_reset(port, 0);
3442 break;
3443
Stefan Roese2fe23042017-03-22 15:09:38 +01003444 case PHY_INTERFACE_MODE_SFI:
3445 num_of_act_lanes = 2;
3446 mac_num = 0;
3447 /* configure PCS */
Stefan Roese2fe23042017-03-22 15:09:38 +01003448 gop_mpcs_mode(port);
3449 /* configure MAC */
3450 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3451
Stefan Roese2fe23042017-03-22 15:09:38 +01003452 /* mac unreset */
3453 gop_xlg_mac_reset(port, 0);
3454 break;
3455
Stefan Roese31aa1e32017-03-22 15:07:30 +01003456 default:
Sean Anderson9db60ee2020-09-15 10:44:57 -04003457 log_err("Requested port mode (%d) not supported\n",
3458 port->phy_interface);
Stefan Roese31aa1e32017-03-22 15:07:30 +01003459 return -1;
3460 }
3461
3462 return 0;
3463}
3464
Stefan Roese2fe23042017-03-22 15:09:38 +01003465static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3466{
3467 u32 val;
3468
3469 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3470 if (enable) {
3471 /* Enable port and MIB counters update */
3472 val |= MVPP22_XLG_PORT_EN;
3473 val &= ~MVPP22_XLG_MIBCNT_DIS;
3474 } else {
3475 /* Disable port */
3476 val &= ~MVPP22_XLG_PORT_EN;
3477 }
3478 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3479}
3480
Stefan Roese31aa1e32017-03-22 15:07:30 +01003481static void gop_port_enable(struct mvpp2_port *port, int enable)
3482{
3483 switch (port->phy_interface) {
3484 case PHY_INTERFACE_MODE_RGMII:
3485 case PHY_INTERFACE_MODE_RGMII_ID:
3486 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003487 case PHY_INTERFACE_MODE_SGMII_2500:
Stefan Chulski8299abc2021-05-03 08:08:46 +02003488 case PHY_INTERFACE_MODE_1000BASEX:
3489 case PHY_INTERFACE_MODE_2500BASEX:
Stefan Roese31aa1e32017-03-22 15:07:30 +01003490 if (enable)
3491 mvpp2_port_enable(port);
3492 else
3493 mvpp2_port_disable(port);
3494 break;
3495
Stefan Roese2fe23042017-03-22 15:09:38 +01003496 case PHY_INTERFACE_MODE_SFI:
3497 gop_xlg_mac_port_enable(port, enable);
3498
3499 break;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003500 default:
Sean Anderson9db60ee2020-09-15 10:44:57 -04003501 log_err("%s: Wrong port mode (%d)\n", __func__,
3502 port->phy_interface);
Stefan Roese31aa1e32017-03-22 15:07:30 +01003503 return;
3504 }
3505}
3506
3507/* RFU1 functions */
3508static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3509{
3510 return readl(priv->rfu1_base + offset);
3511}
3512
3513static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3514{
3515 writel(data, priv->rfu1_base + offset);
3516}
3517
3518static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3519{
3520 u32 val = 0;
3521
3522 if (gop_id == 2) {
Stefan Chulski8299abc2021-05-03 08:08:46 +02003523 if (phy_type == PHY_INTERFACE_MODE_SGMII ||
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003524 phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
Stefan Chulski8299abc2021-05-03 08:08:46 +02003525 phy_type == PHY_INTERFACE_MODE_1000BASEX ||
3526 phy_type == PHY_INTERFACE_MODE_2500BASEX)
Stefan Roese31aa1e32017-03-22 15:07:30 +01003527 val |= MV_NETC_GE_MAC2_SGMII;
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003528 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3529 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3530 val |= MV_NETC_GE_MAC2_RGMII;
Stefan Roese31aa1e32017-03-22 15:07:30 +01003531 }
3532
3533 if (gop_id == 3) {
Stefan Chulski8299abc2021-05-03 08:08:46 +02003534 if (phy_type == PHY_INTERFACE_MODE_SGMII ||
Marcin Wojtasd24efc62021-05-03 08:08:53 +02003535 phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
Stefan Chulski8299abc2021-05-03 08:08:46 +02003536 phy_type == PHY_INTERFACE_MODE_1000BASEX ||
3537 phy_type == PHY_INTERFACE_MODE_2500BASEX)
Stefan Roese31aa1e32017-03-22 15:07:30 +01003538 val |= MV_NETC_GE_MAC3_SGMII;
3539 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3540 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3541 val |= MV_NETC_GE_MAC3_RGMII;
3542 }
3543
3544 return val;
3545}
3546
3547static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3548{
3549 u32 reg;
3550
3551 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3552 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3553
3554 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3555 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3556
3557 reg |= val;
3558
3559 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3560}
3561
3562static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3563{
3564 u32 reg;
3565
3566 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3567 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3568
3569 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3570 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3571
3572 reg |= val;
3573
3574 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3575}
3576
3577static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3578{
3579 u32 reg;
3580
3581 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3582 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3583
3584 val <<= NETC_GOP_SOFT_RESET_OFFS;
3585 val &= NETC_GOP_SOFT_RESET_MASK;
3586
3587 reg |= val;
3588
3589 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3590}
3591
3592static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3593{
3594 u32 reg;
3595
3596 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3597 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3598
3599 val <<= NETC_CLK_DIV_PHASE_OFFS;
3600 val &= NETC_CLK_DIV_PHASE_MASK;
3601
3602 reg |= val;
3603
3604 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3605}
3606
3607static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3608{
3609 u32 reg;
3610
3611 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3612 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3613
3614 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3615 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3616
3617 reg |= val;
3618
3619 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3620}
3621
3622static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3623 u32 val)
3624{
3625 u32 reg, mask, offset;
3626
3627 if (gop_id == 2) {
3628 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3629 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3630 } else {
3631 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3632 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3633 }
3634 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3635 reg &= ~mask;
3636
3637 val <<= offset;
3638 val &= mask;
3639
3640 reg |= val;
3641
3642 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3643}
3644
3645static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3646{
3647 u32 reg;
3648
3649 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3650 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3651
3652 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3653 val &= NETC_BUS_WIDTH_SELECT_MASK;
3654
3655 reg |= val;
3656
3657 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3658}
3659
3660static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3661{
3662 u32 reg;
3663
3664 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3665 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3666
3667 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3668 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3669
3670 reg |= val;
3671
3672 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3673}
3674
3675static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3676 enum mv_netc_phase phase)
3677{
3678 switch (phase) {
3679 case MV_NETC_FIRST_PHASE:
3680 /* Set Bus Width to HB mode = 1 */
3681 gop_netc_bus_width_select(priv, 1);
3682 /* Select RGMII mode */
3683 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3684 break;
3685
3686 case MV_NETC_SECOND_PHASE:
3687 /* De-assert the relevant port HB reset */
3688 gop_netc_port_rf_reset(priv, gop_id, 1);
3689 break;
3690 }
3691}
3692
3693static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3694 enum mv_netc_phase phase)
3695{
3696 switch (phase) {
3697 case MV_NETC_FIRST_PHASE:
3698 /* Set Bus Width to HB mode = 1 */
3699 gop_netc_bus_width_select(priv, 1);
3700 /* Select SGMII mode */
3701 if (gop_id >= 1) {
3702 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3703 MV_NETC_GBE_SGMII);
3704 }
3705
3706 /* Configure the sample stages */
3707 gop_netc_sample_stages_timing(priv, 0);
3708 /* Configure the ComPhy Selector */
3709 /* gop_netc_com_phy_selector_config(netComplex); */
3710 break;
3711
3712 case MV_NETC_SECOND_PHASE:
3713 /* De-assert the relevant port HB reset */
3714 gop_netc_port_rf_reset(priv, gop_id, 1);
3715 break;
3716 }
3717}
3718
3719static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3720{
3721 u32 c = priv->netc_config;
3722
3723 if (c & MV_NETC_GE_MAC2_SGMII)
3724 gop_netc_mac_to_sgmii(priv, 2, phase);
Stefan Chulski8d3aa372021-05-03 08:08:45 +02003725 else if (c & MV_NETC_GE_MAC2_RGMII)
Stefan Roese31aa1e32017-03-22 15:07:30 +01003726 gop_netc_mac_to_xgmii(priv, 2, phase);
3727
3728 if (c & MV_NETC_GE_MAC3_SGMII) {
3729 gop_netc_mac_to_sgmii(priv, 3, phase);
3730 } else {
3731 gop_netc_mac_to_xgmii(priv, 3, phase);
3732 if (c & MV_NETC_GE_MAC3_RGMII)
3733 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3734 else
3735 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3736 }
3737
3738 /* Activate gop ports 0, 2, 3 */
3739 gop_netc_active_port(priv, 0, 1);
3740 gop_netc_active_port(priv, 2, 1);
3741 gop_netc_active_port(priv, 3, 1);
3742
3743 if (phase == MV_NETC_SECOND_PHASE) {
3744 /* Enable the GOP internal clock logic */
3745 gop_netc_gop_clock_logic_set(priv, 1);
3746 /* De-assert GOP unit reset */
3747 gop_netc_gop_reset(priv, 1);
3748 }
3749
3750 return 0;
3751}
3752
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003753/* Set defaults to the MVPP2 port */
3754static void mvpp2_defaults_set(struct mvpp2_port *port)
3755{
3756 int tx_port_num, val, queue, ptxq, lrxq;
3757
Thomas Petazzonib8c8e6f2017-02-16 06:57:24 +01003758 if (port->priv->hw_version == MVPP21) {
3759 /* Configure port to loopback if needed */
3760 if (port->flags & MVPP2_F_LOOPBACK)
3761 mvpp2_port_loopback_set(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003762
Thomas Petazzonib8c8e6f2017-02-16 06:57:24 +01003763 /* Update TX FIFO MIN Threshold */
3764 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3765 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3766 /* Min. TX threshold must be less than minimal packet length */
3767 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3768 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3769 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003770
3771 /* Disable Legacy WRR, Disable EJP, Release from reset */
3772 tx_port_num = mvpp2_egress_port(port);
3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3774 tx_port_num);
3775 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3776
3777 /* Close bandwidth for all queues */
3778 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3779 ptxq = mvpp2_txq_phys(port->id, queue);
3780 mvpp2_write(port->priv,
3781 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3782 }
3783
3784 /* Set refill period to 1 usec, refill tokens
3785 * and bucket size to maximum
3786 */
3787 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3788 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3789 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3790 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3791 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3792 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3793 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3794 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3795
3796 /* Set MaximumLowLatencyPacketSize value to 256 */
3797 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3798 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3799 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3800
3801 /* Enable Rx cache snoop */
3802 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3803 queue = port->rxqs[lrxq]->id;
3804 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3805 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3806 MVPP2_SNOOP_BUF_HDR_MASK;
3807 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3808 }
3809}
3810
3811/* Enable/disable receiving packets */
3812static void mvpp2_ingress_enable(struct mvpp2_port *port)
3813{
3814 u32 val;
3815 int lrxq, queue;
3816
3817 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3818 queue = port->rxqs[lrxq]->id;
3819 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3820 val &= ~MVPP2_RXQ_DISABLE_MASK;
3821 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3822 }
3823}
3824
3825static void mvpp2_ingress_disable(struct mvpp2_port *port)
3826{
3827 u32 val;
3828 int lrxq, queue;
3829
3830 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3831 queue = port->rxqs[lrxq]->id;
3832 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3833 val |= MVPP2_RXQ_DISABLE_MASK;
3834 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3835 }
3836}
3837
3838/* Enable transmit via physical egress queue
3839 * - HW starts take descriptors from DRAM
3840 */
3841static void mvpp2_egress_enable(struct mvpp2_port *port)
3842{
3843 u32 qmap;
3844 int queue;
3845 int tx_port_num = mvpp2_egress_port(port);
3846
3847 /* Enable all initialized TXs. */
3848 qmap = 0;
3849 for (queue = 0; queue < txq_number; queue++) {
3850 struct mvpp2_tx_queue *txq = port->txqs[queue];
3851
3852 if (txq->descs != NULL)
3853 qmap |= (1 << queue);
3854 }
3855
3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3857 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3858}
3859
3860/* Disable transmit via physical egress queue
3861 * - HW doesn't take descriptors from DRAM
3862 */
3863static void mvpp2_egress_disable(struct mvpp2_port *port)
3864{
3865 u32 reg_data;
3866 int delay;
3867 int tx_port_num = mvpp2_egress_port(port);
3868
3869 /* Issue stop command for active channels only */
3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3871 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3872 MVPP2_TXP_SCHED_ENQ_MASK;
3873 if (reg_data != 0)
3874 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3875 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3876
3877 /* Wait for all Tx activity to terminate. */
3878 delay = 0;
3879 do {
3880 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04003881 dev_warn(port->phy_dev->dev,
3882 "Tx stop timed out, status=0x%08x\n",
3883 reg_data);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003884 break;
3885 }
3886 mdelay(1);
3887 delay++;
3888
3889 /* Check port TX Command register that all
3890 * Tx queues are stopped
3891 */
3892 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3894}
3895
3896/* Rx descriptors helper methods */
3897
3898/* Get number of Rx descriptors occupied by received packets */
3899static inline int
3900mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3901{
3902 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3903
3904 return val & MVPP2_RXQ_OCCUPIED_MASK;
3905}
3906
3907/* Update Rx queue status with the number of occupied and available
3908 * Rx descriptor slots.
3909 */
3910static inline void
3911mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3912 int used_count, int free_count)
3913{
3914 /* Decrement the number of used descriptors and increment count
3915 * increment the number of free descriptors.
3916 */
3917 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3918
3919 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3920}
3921
3922/* Get pointer to next RX descriptor to be processed by SW */
3923static inline struct mvpp2_rx_desc *
3924mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3925{
3926 int rx_desc = rxq->next_desc_to_proc;
3927
3928 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3929 prefetch(rxq->descs + rxq->next_desc_to_proc);
3930 return rxq->descs + rx_desc;
3931}
3932
3933/* Set rx queue offset */
3934static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3935 int prxq, int offset)
3936{
3937 u32 val;
3938
3939 /* Convert offset from bytes to units of 32 bytes */
3940 offset = offset >> 5;
3941
3942 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3943 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3944
3945 /* Offset is in */
3946 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3947 MVPP2_RXQ_PACKET_OFFSET_MASK);
3948
3949 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3950}
3951
3952/* Obtain BM cookie information from descriptor */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01003953static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3954 struct mvpp2_rx_desc *rx_desc)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003955{
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003956 int cpu = smp_processor_id();
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01003957 int pool;
3958
3959 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3960 MVPP2_RXD_BM_POOL_ID_MASK) >>
3961 MVPP2_RXD_BM_POOL_ID_OFFS;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01003962
3963 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3964 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3965}
3966
3967/* Tx descriptors helper methods */
3968
3969/* Get number of Tx descriptors waiting to be transmitted by HW */
3970static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3971 struct mvpp2_tx_queue *txq)
3972{
3973 u32 val;
3974
3975 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3976 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3977
3978 return val & MVPP2_TXQ_PENDING_MASK;
3979}
3980
3981/* Get pointer to next Tx descriptor to be processed (send) by HW */
3982static struct mvpp2_tx_desc *
3983mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3984{
3985 int tx_desc = txq->next_desc_to_proc;
3986
3987 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3988 return txq->descs + tx_desc;
3989}
3990
3991/* Update HW with number of aggregated Tx descriptors to be sent */
3992static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3993{
3994 /* aggregated access - relevant TXQ number is written in TX desc */
3995 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3996}
3997
3998/* Get number of sent descriptors and decrement counter.
3999 * The number of sent descriptors is returned.
4000 * Per-CPU access
4001 */
4002static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
4003 struct mvpp2_tx_queue *txq)
4004{
4005 u32 val;
4006
4007 /* Reading status reg resets transmitted descriptor counter */
4008 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
4009
4010 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
4011 MVPP2_TRANSMITTED_COUNT_OFFSET;
4012}
4013
4014static void mvpp2_txq_sent_counter_clear(void *arg)
4015{
4016 struct mvpp2_port *port = arg;
4017 int queue;
4018
4019 for (queue = 0; queue < txq_number; queue++) {
4020 int id = port->txqs[queue]->id;
4021
4022 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
4023 }
4024}
4025
4026/* Set max sizes for Tx queues */
4027static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
4028{
4029 u32 val, size, mtu;
4030 int txq, tx_port_num;
4031
4032 mtu = port->pkt_size * 8;
4033 if (mtu > MVPP2_TXP_MTU_MAX)
4034 mtu = MVPP2_TXP_MTU_MAX;
4035
4036 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
4037 mtu = 3 * mtu;
4038
4039 /* Indirect access to registers */
4040 tx_port_num = mvpp2_egress_port(port);
4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4042
4043 /* Set MTU */
4044 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4045 val &= ~MVPP2_TXP_MTU_MAX;
4046 val |= mtu;
4047 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4048
4049 /* TXP token size and all TXQs token size must be larger that MTU */
4050 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4051 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4052 if (size < mtu) {
4053 size = mtu;
4054 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4055 val |= size;
4056 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4057 }
4058
4059 for (txq = 0; txq < txq_number; txq++) {
4060 val = mvpp2_read(port->priv,
4061 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4062 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4063
4064 if (size < mtu) {
4065 size = mtu;
4066 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4067 val |= size;
4068 mvpp2_write(port->priv,
4069 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4070 val);
4071 }
4072 }
4073}
4074
4075/* Free Tx queue skbuffs */
4076static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4077 struct mvpp2_tx_queue *txq,
4078 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4079{
4080 int i;
4081
4082 for (i = 0; i < num; i++)
4083 mvpp2_txq_inc_get(txq_pcpu);
4084}
4085
4086static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4087 u32 cause)
4088{
4089 int queue = fls(cause) - 1;
4090
4091 return port->rxqs[queue];
4092}
4093
4094static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4095 u32 cause)
4096{
4097 int queue = fls(cause) - 1;
4098
4099 return port->txqs[queue];
4100}
4101
4102/* Rx/Tx queue initialization/cleanup methods */
4103
4104/* Allocate and initialize descriptors for aggr TXQ */
4105static int mvpp2_aggr_txq_init(struct udevice *dev,
4106 struct mvpp2_tx_queue *aggr_txq,
4107 int desc_num, int cpu,
4108 struct mvpp2 *priv)
4109{
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004110 u32 txq_dma;
4111
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004112 /* Allocate memory for TX descriptors */
4113 aggr_txq->descs = buffer_loc.aggr_tx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004114 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004115 if (!aggr_txq->descs)
4116 return -ENOMEM;
4117
4118 /* Make sure descriptor address is cache line size aligned */
4119 BUG_ON(aggr_txq->descs !=
4120 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4121
4122 aggr_txq->last_desc = aggr_txq->size - 1;
4123
4124 /* Aggr TXQ no reset WA */
4125 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4126 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4127
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004128 /* Set Tx descriptors queue starting address indirect
4129 * access
4130 */
4131 if (priv->hw_version == MVPP21)
4132 txq_dma = aggr_txq->descs_dma;
4133 else
4134 txq_dma = aggr_txq->descs_dma >>
4135 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4136
4137 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004138 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4139
4140 return 0;
4141}
4142
4143/* Create a specified Rx queue */
4144static int mvpp2_rxq_init(struct mvpp2_port *port,
4145 struct mvpp2_rx_queue *rxq)
4146
4147{
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004148 u32 rxq_dma;
4149
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004150 rxq->size = port->rx_ring_size;
4151
4152 /* Allocate memory for RX descriptors */
4153 rxq->descs = buffer_loc.rx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004154 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004155 if (!rxq->descs)
4156 return -ENOMEM;
4157
4158 BUG_ON(rxq->descs !=
4159 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4160
4161 rxq->last_desc = rxq->size - 1;
4162
4163 /* Zero occupied and non-occupied counters - direct access */
4164 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4165
4166 /* Set Rx descriptors queue starting address - indirect access */
4167 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
Thomas Petazzoni80350f52017-02-20 11:36:57 +01004168 if (port->priv->hw_version == MVPP21)
4169 rxq_dma = rxq->descs_dma;
4170 else
4171 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4172 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004173 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4174 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4175
4176 /* Set Offset */
4177 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4178
4179 /* Add number of descriptors ready for receiving packets */
4180 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4181
4182 return 0;
4183}
4184
4185/* Push packets received by the RXQ to BM pool */
4186static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4187 struct mvpp2_rx_queue *rxq)
4188{
4189 int rx_received, i;
4190
4191 rx_received = mvpp2_rxq_received(port, rxq->id);
4192 if (!rx_received)
4193 return;
4194
4195 for (i = 0; i < rx_received; i++) {
4196 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004197 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004198
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004199 mvpp2_pool_refill(port, bm,
4200 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4201 mvpp2_rxdesc_cookie_get(port, rx_desc));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004202 }
4203 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4204}
4205
4206/* Cleanup Rx queue */
4207static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4208 struct mvpp2_rx_queue *rxq)
4209{
4210 mvpp2_rxq_drop_pkts(port, rxq);
4211
4212 rxq->descs = NULL;
4213 rxq->last_desc = 0;
4214 rxq->next_desc_to_proc = 0;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004215 rxq->descs_dma = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004216
4217 /* Clear Rx descriptors queue starting address and size;
4218 * free descriptor number
4219 */
4220 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4221 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4222 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4223 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4224}
4225
4226/* Create and initialize a Tx queue */
4227static int mvpp2_txq_init(struct mvpp2_port *port,
4228 struct mvpp2_tx_queue *txq)
4229{
4230 u32 val;
4231 int cpu, desc, desc_per_txq, tx_port_num;
4232 struct mvpp2_txq_pcpu *txq_pcpu;
4233
4234 txq->size = port->tx_ring_size;
4235
4236 /* Allocate memory for Tx descriptors */
4237 txq->descs = buffer_loc.tx_descs;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004238 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004239 if (!txq->descs)
4240 return -ENOMEM;
4241
4242 /* Make sure descriptor address is cache line size aligned */
4243 BUG_ON(txq->descs !=
4244 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4245
4246 txq->last_desc = txq->size - 1;
4247
4248 /* Set Tx descriptors queue starting address - indirect access */
4249 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004250 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004251 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4252 MVPP2_TXQ_DESC_SIZE_MASK);
4253 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4254 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4255 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4256 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4257 val &= ~MVPP2_TXQ_PENDING_MASK;
4258 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4259
4260 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4261 * for each existing TXQ.
4262 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4263 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4264 */
4265 desc_per_txq = 16;
4266 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4267 (txq->log_id * desc_per_txq);
4268
4269 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4270 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
Thomas Petazzoni26a52782017-02-16 08:03:37 +01004271 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004272
4273 /* WRR / EJP configuration - indirect access */
4274 tx_port_num = mvpp2_egress_port(port);
4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4276
4277 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4278 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4279 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4280 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4281 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4282
4283 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4284 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4285 val);
4286
4287 for_each_present_cpu(cpu) {
4288 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4289 txq_pcpu->size = txq->size;
4290 }
4291
4292 return 0;
4293}
4294
4295/* Free allocated TXQ resources */
4296static void mvpp2_txq_deinit(struct mvpp2_port *port,
4297 struct mvpp2_tx_queue *txq)
4298{
4299 txq->descs = NULL;
4300 txq->last_desc = 0;
4301 txq->next_desc_to_proc = 0;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004302 txq->descs_dma = 0;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004303
4304 /* Set minimum bandwidth for disabled TXQs */
4305 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4306
4307 /* Set Tx descriptors queue starting address and size */
4308 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4309 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4310 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4311}
4312
4313/* Cleanup Tx ports */
4314static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4315{
4316 struct mvpp2_txq_pcpu *txq_pcpu;
4317 int delay, pending, cpu;
4318 u32 val;
4319
4320 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4321 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4322 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4323 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4324
4325 /* The napi queue has been stopped so wait for all packets
4326 * to be transmitted.
4327 */
4328 delay = 0;
4329 do {
4330 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004331 dev_warn(port->phy_dev->dev,
4332 "port %d: cleaning queue %d timed out\n",
4333 port->id, txq->log_id);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004334 break;
4335 }
4336 mdelay(1);
4337 delay++;
4338
4339 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4340 } while (pending);
4341
4342 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4343 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4344
4345 for_each_present_cpu(cpu) {
4346 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4347
4348 /* Release all packets */
4349 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4350
4351 /* Reset queue */
4352 txq_pcpu->count = 0;
4353 txq_pcpu->txq_put_index = 0;
4354 txq_pcpu->txq_get_index = 0;
4355 }
4356}
4357
4358/* Cleanup all Tx queues */
4359static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4360{
4361 struct mvpp2_tx_queue *txq;
4362 int queue;
4363 u32 val;
4364
4365 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4366
4367 /* Reset Tx ports and delete Tx queues */
4368 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4369 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4370
4371 for (queue = 0; queue < txq_number; queue++) {
4372 txq = port->txqs[queue];
4373 mvpp2_txq_clean(port, txq);
4374 mvpp2_txq_deinit(port, txq);
4375 }
4376
4377 mvpp2_txq_sent_counter_clear(port);
4378
4379 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4380 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4381}
4382
4383/* Cleanup all Rx queues */
4384static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4385{
4386 int queue;
4387
4388 for (queue = 0; queue < rxq_number; queue++)
4389 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4390}
4391
4392/* Init all Rx queues for port */
4393static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4394{
4395 int queue, err;
4396
4397 for (queue = 0; queue < rxq_number; queue++) {
4398 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4399 if (err)
4400 goto err_cleanup;
4401 }
4402 return 0;
4403
4404err_cleanup:
4405 mvpp2_cleanup_rxqs(port);
4406 return err;
4407}
4408
4409/* Init all tx queues for port */
4410static int mvpp2_setup_txqs(struct mvpp2_port *port)
4411{
4412 struct mvpp2_tx_queue *txq;
4413 int queue, err;
4414
4415 for (queue = 0; queue < txq_number; queue++) {
4416 txq = port->txqs[queue];
4417 err = mvpp2_txq_init(port, txq);
4418 if (err)
4419 goto err_cleanup;
4420 }
4421
4422 mvpp2_txq_sent_counter_clear(port);
4423 return 0;
4424
4425err_cleanup:
4426 mvpp2_cleanup_txqs(port);
4427 return err;
4428}
4429
4430/* Adjust link */
4431static void mvpp2_link_event(struct mvpp2_port *port)
4432{
4433 struct phy_device *phydev = port->phy_dev;
4434 int status_change = 0;
4435 u32 val;
4436
4437 if (phydev->link) {
4438 if ((port->speed != phydev->speed) ||
4439 (port->duplex != phydev->duplex)) {
4440 u32 val;
4441
4442 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4443 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4444 MVPP2_GMAC_CONFIG_GMII_SPEED |
4445 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4446 MVPP2_GMAC_AN_SPEED_EN |
4447 MVPP2_GMAC_AN_DUPLEX_EN);
4448
4449 if (phydev->duplex)
4450 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4451
Stefan Chulski08f462d2021-05-03 08:08:48 +02004452 if (phydev->speed == SPEED_1000 ||
4453 phydev->speed == 2500)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004454 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4455 else if (phydev->speed == SPEED_100)
4456 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4457
4458 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4459
4460 port->duplex = phydev->duplex;
4461 port->speed = phydev->speed;
4462 }
4463 }
4464
4465 if (phydev->link != port->link) {
4466 if (!phydev->link) {
4467 port->duplex = -1;
4468 port->speed = 0;
4469 }
4470
4471 port->link = phydev->link;
4472 status_change = 1;
4473 }
4474
4475 if (status_change) {
4476 if (phydev->link) {
4477 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4478 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4479 MVPP2_GMAC_FORCE_LINK_DOWN);
4480 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4481 mvpp2_egress_enable(port);
4482 mvpp2_ingress_enable(port);
4483 } else {
4484 mvpp2_ingress_disable(port);
4485 mvpp2_egress_disable(port);
4486 }
4487 }
4488}
4489
4490/* Main RX/TX processing routines */
4491
4492/* Display more error info */
4493static void mvpp2_rx_error(struct mvpp2_port *port,
4494 struct mvpp2_rx_desc *rx_desc)
4495{
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01004496 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4497 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004498
4499 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4500 case MVPP2_RXD_ERR_CRC:
Sean Anderson9db60ee2020-09-15 10:44:57 -04004501 dev_err(port->phy_dev->dev,
4502 "bad rx status %08x (crc error), size=%zu\n", status,
4503 sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004504 break;
4505 case MVPP2_RXD_ERR_OVERRUN:
Sean Anderson9db60ee2020-09-15 10:44:57 -04004506 dev_err(port->phy_dev->dev,
4507 "bad rx status %08x (overrun error), size=%zu\n",
4508 status, sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004509 break;
4510 case MVPP2_RXD_ERR_RESOURCE:
Sean Anderson9db60ee2020-09-15 10:44:57 -04004511 dev_err(port->phy_dev->dev,
4512 "bad rx status %08x (resource error), size=%zu\n",
4513 status, sz);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004514 break;
4515 }
4516}
4517
4518/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4519static int mvpp2_rx_refill(struct mvpp2_port *port,
4520 struct mvpp2_bm_pool *bm_pool,
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004521 u32 bm, dma_addr_t dma_addr)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004522{
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01004523 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004524 return 0;
4525}
4526
4527/* Set hw internals when starting port */
4528static void mvpp2_start_dev(struct mvpp2_port *port)
4529{
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004530 switch (port->phy_interface) {
4531 case PHY_INTERFACE_MODE_RGMII:
4532 case PHY_INTERFACE_MODE_RGMII_ID:
4533 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02004534 case PHY_INTERFACE_MODE_SGMII_2500:
Stefan Chulski8299abc2021-05-03 08:08:46 +02004535 case PHY_INTERFACE_MODE_1000BASEX:
4536 case PHY_INTERFACE_MODE_2500BASEX:
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004537 mvpp2_gmac_max_rx_size_set(port);
4538 default:
4539 break;
4540 }
4541
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004542 mvpp2_txp_max_tx_size_set(port);
4543
Stefan Roese31aa1e32017-03-22 15:07:30 +01004544 if (port->priv->hw_version == MVPP21)
4545 mvpp2_port_enable(port);
4546 else
4547 gop_port_enable(port, 1);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004548}
4549
4550/* Set hw internals when stopping port */
4551static void mvpp2_stop_dev(struct mvpp2_port *port)
4552{
4553 /* Stop new packets from arriving to RXQs */
4554 mvpp2_ingress_disable(port);
4555
4556 mvpp2_egress_disable(port);
Stefan Roese31aa1e32017-03-22 15:07:30 +01004557
4558 if (port->priv->hw_version == MVPP21)
4559 mvpp2_port_disable(port);
4560 else
4561 gop_port_enable(port, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004562}
4563
Stefan Chulski13b725f2019-08-15 18:08:41 -04004564static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004565{
4566 struct phy_device *phy_dev;
4567
4568 if (!port->init || port->link == 0) {
Nevo Hed2a428702019-08-15 18:08:44 -04004569 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
4570 dev, port->phy_interface);
Grzegorz Jaszczyk62394832019-08-15 18:08:42 -04004571
4572 /*
4573 * If the phy doesn't match with any existing u-boot drivers the
4574 * phy framework will connect it to generic one which
4575 * uid == 0xffffffff. In this case act as if the phy wouldn't be
4576 * declared in dts. Otherwise in case of 3310 (for which the
4577 * driver doesn't exist) the link will not be correctly
4578 * detected. Removing phy entry from dts in case of 3310 is not
4579 * an option because it is required for the phy_fw_down
4580 * procedure.
4581 */
4582 if (phy_dev &&
4583 phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
Sean Anderson9db60ee2020-09-15 10:44:57 -04004584 dev_warn(port->phy_dev->dev,
4585 "Marking phy as invalid, link will not be checked\n");
Grzegorz Jaszczyk62394832019-08-15 18:08:42 -04004586 /* set phy_addr to invalid value */
4587 port->phyaddr = PHY_MAX_ADDR;
4588 mvpp2_egress_enable(port);
4589 mvpp2_ingress_enable(port);
4590
4591 return;
4592 }
4593
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004594 port->phy_dev = phy_dev;
4595 if (!phy_dev) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004596 dev_err(port->phy_dev->dev, "cannot connect to phy\n");
Stefan Chulski13b725f2019-08-15 18:08:41 -04004597 return;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004598 }
4599 phy_dev->supported &= PHY_GBIT_FEATURES;
4600 phy_dev->advertising = phy_dev->supported;
4601
4602 port->phy_dev = phy_dev;
4603 port->link = 0;
4604 port->duplex = 0;
4605 port->speed = 0;
4606
4607 phy_config(phy_dev);
4608 phy_startup(phy_dev);
Stefan Chulski13b725f2019-08-15 18:08:41 -04004609 if (!phy_dev->link)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004610 printf("%s: No link\n", phy_dev->dev->name);
Stefan Chulski13b725f2019-08-15 18:08:41 -04004611 else
4612 port->init = 1;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004613 } else {
4614 mvpp2_egress_enable(port);
4615 mvpp2_ingress_enable(port);
4616 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004617}
4618
4619static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4620{
4621 unsigned char mac_bcast[ETH_ALEN] = {
4622 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4623 int err;
4624
4625 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4626 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004627 dev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004628 return err;
4629 }
4630 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4631 port->dev_addr, true);
4632 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004633 dev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004634 return err;
4635 }
4636 err = mvpp2_prs_def_flow(port);
4637 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004638 dev_err(dev, "mvpp2_prs_def_flow failed\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004639 return err;
4640 }
4641
4642 /* Allocate the Rx/Tx queues */
4643 err = mvpp2_setup_rxqs(port);
4644 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004645 dev_err(port->phy_dev->dev, "cannot allocate Rx queues\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004646 return err;
4647 }
4648
4649 err = mvpp2_setup_txqs(port);
4650 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04004651 dev_err(port->phy_dev->dev, "cannot allocate Tx queues\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004652 return err;
4653 }
4654
Nevo Hed2a428702019-08-15 18:08:44 -04004655 if (port->phyaddr < PHY_MAX_ADDR) {
Stefan Chulski13b725f2019-08-15 18:08:41 -04004656 mvpp2_phy_connect(dev, port);
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004657 mvpp2_link_event(port);
4658 } else {
4659 mvpp2_egress_enable(port);
4660 mvpp2_ingress_enable(port);
4661 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004662
4663 mvpp2_start_dev(port);
4664
4665 return 0;
4666}
4667
4668/* No Device ops here in U-Boot */
4669
4670/* Driver initialization */
4671
4672static void mvpp2_port_power_up(struct mvpp2_port *port)
4673{
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004674 struct mvpp2 *priv = port->priv;
4675
Stefan Roese31aa1e32017-03-22 15:07:30 +01004676 /* On PPv2.2 the GoP / interface configuration has already been done */
4677 if (priv->hw_version == MVPP21)
4678 mvpp2_port_mii_set(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004679 mvpp2_port_periodic_xon_disable(port);
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01004680 if (priv->hw_version == MVPP21)
4681 mvpp2_port_fc_adv_enable(port);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004682 mvpp2_port_reset(port);
4683}
4684
4685/* Initialize port HW */
4686static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4687{
4688 struct mvpp2 *priv = port->priv;
4689 struct mvpp2_txq_pcpu *txq_pcpu;
4690 int queue, cpu, err;
4691
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01004692 if (port->first_rxq + rxq_number >
4693 MVPP2_MAX_PORTS * priv->max_port_rxqs)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004694 return -EINVAL;
4695
4696 /* Disable port */
4697 mvpp2_egress_disable(port);
Stefan Roese31aa1e32017-03-22 15:07:30 +01004698 if (priv->hw_version == MVPP21)
4699 mvpp2_port_disable(port);
4700 else
4701 gop_port_enable(port, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004702
4703 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4704 GFP_KERNEL);
4705 if (!port->txqs)
4706 return -ENOMEM;
4707
4708 /* Associate physical Tx queues to this port and initialize.
4709 * The mapping is predefined.
4710 */
4711 for (queue = 0; queue < txq_number; queue++) {
4712 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4713 struct mvpp2_tx_queue *txq;
4714
4715 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4716 if (!txq)
4717 return -ENOMEM;
4718
4719 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4720 GFP_KERNEL);
4721 if (!txq->pcpu)
4722 return -ENOMEM;
4723
4724 txq->id = queue_phy_id;
4725 txq->log_id = queue;
4726 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4727 for_each_present_cpu(cpu) {
4728 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4729 txq_pcpu->cpu = cpu;
4730 }
4731
4732 port->txqs[queue] = txq;
4733 }
4734
4735 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4736 GFP_KERNEL);
4737 if (!port->rxqs)
4738 return -ENOMEM;
4739
4740 /* Allocate and initialize Rx queue for this port */
4741 for (queue = 0; queue < rxq_number; queue++) {
4742 struct mvpp2_rx_queue *rxq;
4743
4744 /* Map physical Rx queue to port's logical Rx queue */
4745 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4746 if (!rxq)
4747 return -ENOMEM;
4748 /* Map this Rx queue to a physical queue */
4749 rxq->id = port->first_rxq + queue;
4750 rxq->port = port->id;
4751 rxq->logic_rxq = queue;
4752
4753 port->rxqs[queue] = rxq;
4754 }
4755
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004756
4757 /* Create Rx descriptor rings */
4758 for (queue = 0; queue < rxq_number; queue++) {
4759 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4760
4761 rxq->size = port->rx_ring_size;
4762 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4763 rxq->time_coal = MVPP2_RX_COAL_USEC;
4764 }
4765
4766 mvpp2_ingress_disable(port);
4767
4768 /* Port default configuration */
4769 mvpp2_defaults_set(port);
4770
4771 /* Port's classifier configuration */
4772 mvpp2_cls_oversize_rxq_set(port);
4773 mvpp2_cls_port_config(port);
4774
4775 /* Provide an initial Rx packet size */
4776 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4777
4778 /* Initialize pools for swf */
4779 err = mvpp2_swf_bm_pool_init(port);
4780 if (err)
4781 return err;
4782
4783 return 0;
4784}
4785
Stefan Roese66b11cc2017-03-22 14:11:16 +01004786static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004787{
Stefan Roese66b11cc2017-03-22 14:11:16 +01004788 int port_node = dev_of_offset(dev);
Baruch Siachacce7532018-11-21 13:05:33 +02004789 int phy_node;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004790 u32 id;
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004791 u32 phyaddr = 0;
Stefan Chulski27844002021-05-03 08:08:52 +02004792 int fixed_link = 0;
Nevo Hed2a428702019-08-15 18:08:44 -04004793 int ret;
Baruch Siach21586cd2018-11-21 13:05:34 +02004794
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004795 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
Stefan Chulski27844002021-05-03 08:08:52 +02004796 fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004797
4798 if (phy_node > 0) {
Nevo Hed2a428702019-08-15 18:08:44 -04004799 int parent;
Stefan Chulski27844002021-05-03 08:08:52 +02004800
4801 if (fixed_link != -FDT_ERR_NOTFOUND) {
4802 /* phy_addr is set to invalid value for fixed links */
4803 phyaddr = PHY_MAX_ADDR;
4804 } else {
4805 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
4806 "reg", 0);
4807 if (phyaddr < 0) {
4808 dev_err(dev, "could not find phy address\n");
4809 return -1;
4810 }
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004811 }
Nevo Hed2a428702019-08-15 18:08:44 -04004812 parent = fdt_parent_offset(gd->fdt_blob, phy_node);
4813 ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
4814 &port->mdio_dev);
4815 if (ret)
4816 return ret;
Stefan Chulskie09d0c82017-04-06 15:39:08 +02004817 } else {
Nevo Hed2a428702019-08-15 18:08:44 -04004818 /* phy_addr is set to invalid value */
4819 phyaddr = PHY_MAX_ADDR;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004820 }
4821
Marek Behún123ca112022-04-07 00:33:01 +02004822 port->phy_interface = dev_read_phy_mode(dev);
Marek Behúnffb0f6f2022-04-07 00:33:03 +02004823 if (port->phy_interface == PHY_INTERFACE_MODE_NA) {
Sean Andersonddc48c12020-09-15 10:44:56 -04004824 dev_err(dev, "incorrect phy mode\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004825 return -EINVAL;
4826 }
4827
4828 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4829 if (id == -1) {
Sean Andersonddc48c12020-09-15 10:44:56 -04004830 dev_err(dev, "missing port-id value\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004831 return -EINVAL;
4832 }
4833
Simon Glassbcee8d62019-12-06 21:41:35 -07004834#if CONFIG_IS_ENABLED(DM_GPIO)
Stefan Chulski41893732017-08-09 10:37:43 +03004835 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4836 &port->phy_reset_gpio, GPIOD_IS_OUT);
4837 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4838 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4839#endif
4840
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004841 port->id = id;
Stefan Roese66b11cc2017-03-22 14:11:16 +01004842 if (port->priv->hw_version == MVPP21)
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01004843 port->first_rxq = port->id * rxq_number;
4844 else
Stefan Roese66b11cc2017-03-22 14:11:16 +01004845 port->first_rxq = port->id * port->priv->max_port_rxqs;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004846 port->phyaddr = phyaddr;
4847
Stefan Roese66b11cc2017-03-22 14:11:16 +01004848 return 0;
4849}
Thomas Petazzoni26a52782017-02-16 08:03:37 +01004850
Simon Glassbcee8d62019-12-06 21:41:35 -07004851#if CONFIG_IS_ENABLED(DM_GPIO)
Stefan Chulski41893732017-08-09 10:37:43 +03004852/* Port GPIO initialization */
4853static void mvpp2_gpio_init(struct mvpp2_port *port)
4854{
4855 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
Stefan Chulski41893732017-08-09 10:37:43 +03004856 dm_gpio_set_value(&port->phy_reset_gpio, 1);
Baruch Siach18593fa2018-10-15 13:16:48 +03004857 mdelay(10);
Baruch Siachfa140272018-10-15 13:16:47 +03004858 dm_gpio_set_value(&port->phy_reset_gpio, 0);
Stefan Chulski41893732017-08-09 10:37:43 +03004859 }
4860
4861 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4862 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4863}
4864#endif
4865
Stefan Roese66b11cc2017-03-22 14:11:16 +01004866/* Ports initialization */
4867static int mvpp2_port_probe(struct udevice *dev,
4868 struct mvpp2_port *port,
4869 int port_node,
4870 struct mvpp2 *priv)
4871{
4872 int err;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004873
4874 port->tx_ring_size = MVPP2_MAX_TXD;
4875 port->rx_ring_size = MVPP2_MAX_RXD;
4876
4877 err = mvpp2_port_init(dev, port);
4878 if (err < 0) {
Sean Andersonddc48c12020-09-15 10:44:56 -04004879 dev_err(dev, "failed to init port %d\n", port->id);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004880 return err;
4881 }
4882 mvpp2_port_power_up(port);
4883
Simon Glassbcee8d62019-12-06 21:41:35 -07004884#if CONFIG_IS_ENABLED(DM_GPIO)
Stefan Chulski41893732017-08-09 10:37:43 +03004885 mvpp2_gpio_init(port);
4886#endif
4887
Stefan Roese66b11cc2017-03-22 14:11:16 +01004888 priv->port_list[port->id] = port;
Stefan Chulskibb915c82017-08-09 10:37:46 +03004889 priv->num_ports++;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004890 return 0;
4891}
4892
4893/* Initialize decoding windows */
4894static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4895 struct mvpp2 *priv)
4896{
4897 u32 win_enable;
4898 int i;
4899
4900 for (i = 0; i < 6; i++) {
4901 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4902 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4903
4904 if (i < 4)
4905 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4906 }
4907
4908 win_enable = 0;
4909
4910 for (i = 0; i < dram->num_cs; i++) {
4911 const struct mbus_dram_window *cs = dram->cs + i;
4912
4913 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4914 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4915 dram->mbus_dram_target_id);
4916
4917 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4918 (cs->size - 1) & 0xffff0000);
4919
4920 win_enable |= (1 << i);
4921 }
4922
4923 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4924}
4925
4926/* Initialize Rx FIFO's */
4927static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4928{
4929 int port;
4930
4931 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
Stefan Roeseff572c62017-03-01 13:09:42 +01004932 if (priv->hw_version == MVPP22) {
4933 if (port == 0) {
4934 mvpp2_write(priv,
4935 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4936 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4937 mvpp2_write(priv,
4938 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4939 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4940 } else if (port == 1) {
4941 mvpp2_write(priv,
4942 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4943 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4944 mvpp2_write(priv,
4945 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4946 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4947 } else {
4948 mvpp2_write(priv,
4949 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4950 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4951 mvpp2_write(priv,
4952 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4953 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4954 }
4955 } else {
4956 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4957 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4958 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4959 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4960 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01004961 }
4962
4963 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4964 MVPP2_RX_FIFO_PORT_MIN_PKT);
4965 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4966}
4967
Stefan Roeseff572c62017-03-01 13:09:42 +01004968/* Initialize Tx FIFO's */
4969static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4970{
4971 int port, val;
4972
4973 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4974 /* Port 0 supports 10KB TX FIFO */
4975 if (port == 0) {
4976 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4977 MVPP22_TX_FIFO_SIZE_MASK;
4978 } else {
4979 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4980 MVPP22_TX_FIFO_SIZE_MASK;
4981 }
4982 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4983 }
4984}
4985
Thomas Petazzonicdf77792017-02-16 08:41:07 +01004986static void mvpp2_axi_init(struct mvpp2 *priv)
4987{
4988 u32 val, rdval, wrval;
4989
4990 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4991
4992 /* AXI Bridge Configuration */
4993
4994 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4995 << MVPP22_AXI_ATTR_CACHE_OFFS;
4996 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4997 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4998
4999 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5000 << MVPP22_AXI_ATTR_CACHE_OFFS;
5001 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5002 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5003
5004 /* BM */
5005 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5006 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5007
5008 /* Descriptors */
5009 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5010 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5011 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5012 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5013
5014 /* Buffer Data */
5015 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5016 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5017
5018 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5019 << MVPP22_AXI_CODE_CACHE_OFFS;
5020 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5021 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5022 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5023 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5024
5025 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5026 << MVPP22_AXI_CODE_CACHE_OFFS;
5027 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5028 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5029
5030 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5031
5032 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5033 << MVPP22_AXI_CODE_CACHE_OFFS;
5034 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5035 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5036
5037 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5038}
5039
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005040/* Initialize network controller common part HW */
5041static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
5042{
5043 const struct mbus_dram_target_info *dram_target_info;
5044 int err, i;
5045 u32 val;
5046
5047 /* Checks for hardware constraints (U-Boot uses only one rxq) */
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01005048 if ((rxq_number > priv->max_port_rxqs) ||
5049 (txq_number > MVPP2_MAX_TXQ)) {
Sean Andersonddc48c12020-09-15 10:44:56 -04005050 dev_err(dev, "invalid queue size parameter\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005051 return -EINVAL;
5052 }
5053
Thomas Petazzonicdf77792017-02-16 08:41:07 +01005054 if (priv->hw_version == MVPP22)
5055 mvpp2_axi_init(priv);
Stefan Chulskid4b0e002017-08-09 10:37:48 +03005056 else {
5057 /* MBUS windows configuration */
5058 dram_target_info = mvebu_mbus_dram_info();
5059 if (dram_target_info)
5060 mvpp2_conf_mbus_windows(dram_target_info, priv);
5061 }
Thomas Petazzonicdf77792017-02-16 08:41:07 +01005062
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005063 if (priv->hw_version == MVPP21) {
Stefan Roese3e3cbb42017-03-09 12:01:57 +01005064 /* Disable HW PHY polling */
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005065 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5066 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5067 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5068 } else {
Stefan Roese3e3cbb42017-03-09 12:01:57 +01005069 /* Enable HW PHY polling */
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005070 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
Stefan Roese3e3cbb42017-03-09 12:01:57 +01005071 val |= MVPP22_SMI_POLLING_EN;
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005072 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5073 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005074
5075 /* Allocate and initialize aggregated TXQs */
5076 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5077 sizeof(struct mvpp2_tx_queue),
5078 GFP_KERNEL);
5079 if (!priv->aggr_txqs)
5080 return -ENOMEM;
5081
5082 for_each_present_cpu(i) {
5083 priv->aggr_txqs[i].id = i;
5084 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5085 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5086 MVPP2_AGGR_TXQ_SIZE, i, priv);
5087 if (err < 0)
5088 return err;
5089 }
5090
5091 /* Rx Fifo Init */
5092 mvpp2_rx_fifo_init(priv);
5093
Stefan Roeseff572c62017-03-01 13:09:42 +01005094 /* Tx Fifo Init */
5095 if (priv->hw_version == MVPP22)
5096 mvpp2_tx_fifo_init(priv);
5097
Thomas Petazzoni7c7311f2017-02-20 11:42:51 +01005098 if (priv->hw_version == MVPP21)
5099 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5100 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005101
5102 /* Allow cache snoop when transmiting packets */
5103 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5104
5105 /* Buffer Manager initialization */
5106 err = mvpp2_bm_init(dev, priv);
5107 if (err < 0)
5108 return err;
5109
5110 /* Parser default initialization */
5111 err = mvpp2_prs_default_init(dev, priv);
5112 if (err < 0)
5113 return err;
5114
5115 /* Classifier default initialization */
5116 mvpp2_cls_init(priv);
5117
5118 return 0;
5119}
5120
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005121static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5122{
5123 struct mvpp2_port *port = dev_get_priv(dev);
5124 struct mvpp2_rx_desc *rx_desc;
5125 struct mvpp2_bm_pool *bm_pool;
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005126 dma_addr_t dma_addr;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005127 u32 bm, rx_status;
5128 int pool, rx_bytes, err;
5129 int rx_received;
5130 struct mvpp2_rx_queue *rxq;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005131 u8 *data;
5132
Nevo Hed2a428702019-08-15 18:08:44 -04005133 if (port->phyaddr < PHY_MAX_ADDR)
Stefan Chulski13b725f2019-08-15 18:08:41 -04005134 if (!port->phy_dev->link)
5135 return 0;
5136
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005137 /* Process RX packets */
Stefan Chulski16f18d22017-08-09 10:37:49 +03005138 rxq = port->rxqs[0];
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005139
5140 /* Get number of received packets and clamp the to-do */
5141 rx_received = mvpp2_rxq_received(port, rxq->id);
5142
5143 /* Return if no packets are received */
5144 if (!rx_received)
5145 return 0;
5146
5147 rx_desc = mvpp2_rxq_next_desc_get(rxq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005148 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5149 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5150 rx_bytes -= MVPP2_MH_SIZE;
5151 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005152
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005153 bm = mvpp2_bm_cookie_build(port, rx_desc);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005154 pool = mvpp2_bm_cookie_pool_get(bm);
5155 bm_pool = &port->priv->bm_pools[pool];
5156
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005157 /* In case of an error, release the requested buffer pointer
5158 * to the Buffer Manager. This request process is controlled
5159 * by the hardware, and the information about the buffer is
5160 * comprised by the RX descriptor.
5161 */
5162 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5163 mvpp2_rx_error(port, rx_desc);
5164 /* Return the buffer to the pool */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005165 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005166 return 0;
5167 }
5168
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005169 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005170 if (err) {
Sean Anderson9db60ee2020-09-15 10:44:57 -04005171 dev_err(port->phy_dev->dev, "failed to refill BM pools\n");
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005172 return 0;
5173 }
5174
5175 /* Update Rx queue management counters */
5176 mb();
5177 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5178
5179 /* give packet to stack - skip on first n bytes */
Thomas Petazzoni4dae32e2017-02-20 10:27:51 +01005180 data = (u8 *)dma_addr + 2 + 32;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005181
5182 if (rx_bytes <= 0)
5183 return 0;
5184
5185 /*
5186 * No cache invalidation needed here, since the rx_buffer's are
5187 * located in a uncached memory region
5188 */
5189 *packetp = data;
5190
5191 return rx_bytes;
5192}
5193
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005194static int mvpp2_send(struct udevice *dev, void *packet, int length)
5195{
5196 struct mvpp2_port *port = dev_get_priv(dev);
5197 struct mvpp2_tx_queue *txq, *aggr_txq;
5198 struct mvpp2_tx_desc *tx_desc;
5199 int tx_done;
5200 int timeout;
5201
Nevo Hed2a428702019-08-15 18:08:44 -04005202 if (port->phyaddr < PHY_MAX_ADDR)
Stefan Chulski13b725f2019-08-15 18:08:41 -04005203 if (!port->phy_dev->link)
5204 return 0;
5205
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005206 txq = port->txqs[0];
5207 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5208
5209 /* Get a descriptor for the first part of the packet */
5210 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005211 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5212 mvpp2_txdesc_size_set(port, tx_desc, length);
5213 mvpp2_txdesc_offset_set(port, tx_desc,
5214 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5215 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5216 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005217 /* First and Last descriptor */
Thomas Petazzonicfa414a2017-02-15 15:35:00 +01005218 mvpp2_txdesc_cmd_set(port, tx_desc,
5219 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5220 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005221
5222 /* Flush tx data */
Stefan Roesef811e042017-02-16 13:58:37 +01005223 flush_dcache_range((unsigned long)packet,
5224 (unsigned long)packet + ALIGN(length, PKTALIGN));
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005225
5226 /* Enable transmit */
5227 mb();
5228 mvpp2_aggr_txq_pend_desc_add(port, 1);
5229
5230 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5231
5232 timeout = 0;
5233 do {
5234 if (timeout++ > 10000) {
5235 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5236 return 0;
5237 }
5238 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5239 } while (tx_done);
5240
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005241 timeout = 0;
5242 do {
5243 if (timeout++ > 10000) {
5244 printf("timeout: packet not sent\n");
5245 return 0;
5246 }
5247 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5248 } while (!tx_done);
5249
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005250 return 0;
5251}
5252
5253static int mvpp2_start(struct udevice *dev)
5254{
Simon Glassc69cda22020-12-03 16:55:20 -07005255 struct eth_pdata *pdata = dev_get_plat(dev);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005256 struct mvpp2_port *port = dev_get_priv(dev);
5257
5258 /* Load current MAC address */
5259 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5260
5261 /* Reconfigure parser accept the original MAC address */
5262 mvpp2_prs_update_mac_da(port, port->dev_addr);
5263
Stefan Chulskie09d0c82017-04-06 15:39:08 +02005264 switch (port->phy_interface) {
5265 case PHY_INTERFACE_MODE_RGMII:
5266 case PHY_INTERFACE_MODE_RGMII_ID:
5267 case PHY_INTERFACE_MODE_SGMII:
Marcin Wojtasd24efc62021-05-03 08:08:53 +02005268 case PHY_INTERFACE_MODE_SGMII_2500:
Stefan Chulski8299abc2021-05-03 08:08:46 +02005269 case PHY_INTERFACE_MODE_1000BASEX:
5270 case PHY_INTERFACE_MODE_2500BASEX:
Stefan Chulskie09d0c82017-04-06 15:39:08 +02005271 mvpp2_port_power_up(port);
5272 default:
5273 break;
5274 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005275
5276 mvpp2_open(dev, port);
5277
5278 return 0;
5279}
5280
5281static void mvpp2_stop(struct udevice *dev)
5282{
5283 struct mvpp2_port *port = dev_get_priv(dev);
5284
5285 mvpp2_stop_dev(port);
5286 mvpp2_cleanup_rxqs(port);
5287 mvpp2_cleanup_txqs(port);
5288}
5289
Matt Pellanda37c0822019-07-30 09:40:24 -04005290static int mvpp2_write_hwaddr(struct udevice *dev)
5291{
5292 struct mvpp2_port *port = dev_get_priv(dev);
5293
5294 return mvpp2_prs_update_mac_da(port, port->dev_addr);
5295}
5296
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005297static int mvpp2_base_probe(struct udevice *dev)
5298{
5299 struct mvpp2 *priv = dev_get_priv(dev);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005300 void *bd_space;
5301 u32 size = 0;
5302 int i;
5303
Thomas Petazzoni16a98982017-02-15 14:08:59 +01005304 /* Save hw-version */
5305 priv->hw_version = dev_get_driver_data(dev);
5306
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005307 /*
5308 * U-Boot special buffer handling:
5309 *
5310 * Allocate buffer area for descs and rx_buffers. This is only
5311 * done once for all interfaces. As only one interface can
5312 * be active. Make this area DMA-safe by disabling the D-cache
5313 */
5314
Sven Auhagen3078e032020-07-01 17:43:43 +02005315 if (!buffer_loc_init) {
5316 /* Align buffer area for descs and rx_buffers to 1MiB */
5317 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5318 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5319 BD_SPACE, DCACHE_OFF);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005320
Sven Auhagen3078e032020-07-01 17:43:43 +02005321 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5322 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005323
Sven Auhagen3078e032020-07-01 17:43:43 +02005324 buffer_loc.tx_descs =
5325 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5326 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005327
Sven Auhagen3078e032020-07-01 17:43:43 +02005328 buffer_loc.rx_descs =
5329 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5330 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005331
Sven Auhagen3078e032020-07-01 17:43:43 +02005332 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5333 buffer_loc.bm_pool[i] =
5334 (unsigned long *)((unsigned long)bd_space + size);
5335 if (priv->hw_version == MVPP21)
5336 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5337 else
5338 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5339 }
5340
5341 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5342 buffer_loc.rx_buffer[i] =
5343 (unsigned long *)((unsigned long)bd_space + size);
5344 size += RX_BUFFER_SIZE;
5345 }
5346
5347 /* Clear the complete area so that all descriptors are cleared */
5348 memset(bd_space, 0, size);
5349
5350 buffer_loc_init = 1;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005351 }
5352
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005353 /* Save base addresses for later use */
Simon Glassa821c4a2017-05-17 17:18:05 -06005354 priv->base = (void *)devfdt_get_addr_index(dev, 0);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005355 if (IS_ERR(priv->base))
5356 return PTR_ERR(priv->base);
5357
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005358 if (priv->hw_version == MVPP21) {
Simon Glassa821c4a2017-05-17 17:18:05 -06005359 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005360 if (IS_ERR(priv->lms_base))
5361 return PTR_ERR(priv->lms_base);
5362 } else {
Simon Glassa821c4a2017-05-17 17:18:05 -06005363 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005364 if (IS_ERR(priv->iface_base))
5365 return PTR_ERR(priv->iface_base);
Stefan Roese0a61e9a2017-02-16 08:31:32 +01005366
Stefan Roese31aa1e32017-03-22 15:07:30 +01005367 /* Store common base addresses for all ports */
5368 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5369 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5370 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
Thomas Petazzoni26a52782017-02-16 08:03:37 +01005371 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005372
Thomas Petazzoni09b3f942017-02-16 09:03:16 +01005373 if (priv->hw_version == MVPP21)
5374 priv->max_port_rxqs = 8;
5375 else
5376 priv->max_port_rxqs = 32;
5377
Baruch Siach21586cd2018-11-21 13:05:34 +02005378 return 0;
5379}
5380
5381static int mvpp2_probe(struct udevice *dev)
5382{
5383 struct mvpp2_port *port = dev_get_priv(dev);
5384 struct mvpp2 *priv = dev_get_priv(dev->parent);
Baruch Siach21586cd2018-11-21 13:05:34 +02005385 int err;
5386
5387 /* Only call the probe function for the parent once */
5388 if (!priv->probe_done)
5389 err = mvpp2_base_probe(dev->parent);
5390
Nevo Hed2a428702019-08-15 18:08:44 -04005391 port->priv = priv;
Stefan Roese66b11cc2017-03-22 14:11:16 +01005392
5393 err = phy_info_parse(dev, port);
5394 if (err)
5395 return err;
5396
5397 /*
5398 * We need the port specific io base addresses at this stage, since
5399 * gop_port_init() accesses these registers
5400 */
5401 if (priv->hw_version == MVPP21) {
5402 int priv_common_regs_num = 2;
5403
Simon Glassa821c4a2017-05-17 17:18:05 -06005404 port->base = (void __iomem *)devfdt_get_addr_index(
Stefan Roese66b11cc2017-03-22 14:11:16 +01005405 dev->parent, priv_common_regs_num + port->id);
5406 if (IS_ERR(port->base))
5407 return PTR_ERR(port->base);
5408 } else {
5409 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5410 "gop-port-id", -1);
5411 if (port->id == -1) {
Sean Andersonddc48c12020-09-15 10:44:56 -04005412 dev_err(dev, "missing gop-port-id value\n");
Stefan Roese66b11cc2017-03-22 14:11:16 +01005413 return -EINVAL;
5414 }
5415
5416 port->base = priv->iface_base + MVPP22_PORT_BASE +
5417 port->gop_id * MVPP22_PORT_OFFSET;
Stefan Roese31aa1e32017-03-22 15:07:30 +01005418
5419 /* GoP Init */
5420 gop_port_init(port);
Stefan Roese66b11cc2017-03-22 14:11:16 +01005421 }
5422
Stefan Chulskibb915c82017-08-09 10:37:46 +03005423 if (!priv->probe_done) {
5424 /* Initialize network controller */
5425 err = mvpp2_init(dev, priv);
5426 if (err < 0) {
Sean Andersonddc48c12020-09-15 10:44:56 -04005427 dev_err(dev, "failed to initialize controller\n");
Stefan Chulskibb915c82017-08-09 10:37:46 +03005428 return err;
5429 }
5430 priv->num_ports = 0;
5431 priv->probe_done = 1;
Stefan Roese1fabbd02017-02-16 15:26:06 +01005432 }
5433
Stefan Roese31aa1e32017-03-22 15:07:30 +01005434 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5435 if (err)
5436 return err;
5437
5438 if (priv->hw_version == MVPP22) {
5439 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5440 port->phy_interface);
5441
5442 /* Netcomplex configurations for all ports */
5443 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5444 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5445 }
5446
5447 return 0;
Stefan Roese1fabbd02017-02-16 15:26:06 +01005448}
5449
Stefan Roese2f720f12017-03-23 17:01:59 +01005450/*
5451 * Empty BM pool and stop its activity before the OS is started
5452 */
5453static int mvpp2_remove(struct udevice *dev)
5454{
5455 struct mvpp2_port *port = dev_get_priv(dev);
5456 struct mvpp2 *priv = port->priv;
5457 int i;
5458
Stefan Chulskibb915c82017-08-09 10:37:46 +03005459 priv->num_ports--;
5460
5461 if (priv->num_ports)
5462 return 0;
5463
Stefan Roese2f720f12017-03-23 17:01:59 +01005464 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5465 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5466
5467 return 0;
5468}
5469
Stefan Roese1fabbd02017-02-16 15:26:06 +01005470static const struct eth_ops mvpp2_ops = {
5471 .start = mvpp2_start,
5472 .send = mvpp2_send,
5473 .recv = mvpp2_recv,
5474 .stop = mvpp2_stop,
Matt Pellanda37c0822019-07-30 09:40:24 -04005475 .write_hwaddr = mvpp2_write_hwaddr
Stefan Roese1fabbd02017-02-16 15:26:06 +01005476};
5477
5478static struct driver mvpp2_driver = {
5479 .name = "mvpp2",
5480 .id = UCLASS_ETH,
5481 .probe = mvpp2_probe,
Stefan Roese2f720f12017-03-23 17:01:59 +01005482 .remove = mvpp2_remove,
Stefan Roese1fabbd02017-02-16 15:26:06 +01005483 .ops = &mvpp2_ops,
Simon Glass41575d82020-12-03 16:55:17 -07005484 .priv_auto = sizeof(struct mvpp2_port),
Simon Glasscaa4daa2020-12-03 16:55:18 -07005485 .plat_auto = sizeof(struct eth_pdata),
Stefan Roese2f720f12017-03-23 17:01:59 +01005486 .flags = DM_FLAG_ACTIVE_DMA,
Stefan Roese1fabbd02017-02-16 15:26:06 +01005487};
5488
5489/*
5490 * Use a MISC device to bind the n instances (child nodes) of the
5491 * network base controller in UCLASS_ETH.
5492 */
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005493static int mvpp2_base_bind(struct udevice *parent)
5494{
5495 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -07005496 int node = dev_of_offset(parent);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005497 struct uclass_driver *drv;
5498 struct udevice *dev;
5499 struct eth_pdata *plat;
5500 char *name;
5501 int subnode;
5502 u32 id;
Stefan Roesec9607c92017-02-24 10:12:41 +01005503 int base_id_add;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005504
5505 /* Lookup eth driver */
5506 drv = lists_uclass_lookup(UCLASS_ETH);
5507 if (!drv) {
5508 puts("Cannot find eth driver\n");
5509 return -ENOENT;
5510 }
5511
Stefan Roesec9607c92017-02-24 10:12:41 +01005512 base_id_add = base_id;
5513
Simon Glassdf87e6b2016-10-02 17:59:29 -06005514 fdt_for_each_subnode(subnode, blob, node) {
Stefan Roesec9607c92017-02-24 10:12:41 +01005515 /* Increment base_id for all subnodes, also the disabled ones */
5516 base_id++;
5517
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005518 /* Skip disabled ports */
5519 if (!fdtdec_get_is_enabled(blob, subnode))
5520 continue;
5521
5522 plat = calloc(1, sizeof(*plat));
5523 if (!plat)
5524 return -ENOMEM;
5525
5526 id = fdtdec_get_int(blob, subnode, "port-id", -1);
Stefan Roesec9607c92017-02-24 10:12:41 +01005527 id += base_id_add;
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005528
5529 name = calloc(1, 16);
Heinrich Schuchardtb24b1e42018-03-07 03:39:04 +01005530 if (!name) {
5531 free(plat);
5532 return -ENOMEM;
5533 }
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005534 sprintf(name, "mvpp2-%d", id);
5535
5536 /* Create child device UCLASS_ETH and bind it */
Simon Glassa2703ce2020-11-28 17:50:03 -07005537 device_bind(parent, &mvpp2_driver, name, plat,
5538 offset_to_ofnode(subnode), &dev);
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005539 }
5540
5541 return 0;
5542}
5543
5544static const struct udevice_id mvpp2_ids[] = {
Thomas Petazzoni16a98982017-02-15 14:08:59 +01005545 {
5546 .compatible = "marvell,armada-375-pp2",
5547 .data = MVPP21,
5548 },
Thomas Petazzonia83a6412017-02-20 11:54:31 +01005549 {
5550 .compatible = "marvell,armada-7k-pp22",
5551 .data = MVPP22,
5552 },
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005553 { }
5554};
5555
5556U_BOOT_DRIVER(mvpp2_base) = {
5557 .name = "mvpp2_base",
5558 .id = UCLASS_MISC,
5559 .of_match = mvpp2_ids,
5560 .bind = mvpp2_base_bind,
Simon Glass41575d82020-12-03 16:55:17 -07005561 .priv_auto = sizeof(struct mvpp2),
Stefan Roese99d4c6d2016-02-10 07:22:10 +01005562};