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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ffd4c7c2ecb745586239eb98d5dc0fe5e6ebe3bd / . / arch / arm / dts / am33xx.dtsi
blob: d3dd6a16e70a706f214bf5ab54bdff396ed2c2bc [file] [log] [blame]
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]13#include <dt-bindings/clock/am3.h>
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]14
15/ {
16 compatible = "ti,am33xx";
17 interrupt-parent = <&intc>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]18 #address-cells = <1>;
19 #size-cells = <1>;
20 chosen { };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]21
22 aliases {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]26 serial0 = &uart0;
27 serial1 = &uart1;
28 serial2 = &uart2;
29 serial3 = &uart3;
30 serial4 = &uart4;
31 serial5 = &uart5;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]32 d-can0 = &dcan0;
33 d-can1 = &dcan1;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]34 usb0 = &usb0;
35 usb1 = &usb1;
36 phy0 = &usb0_phy;
37 phy1 = &usb1_phy;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]40 spi0 = &spi0;
41 spi1 = &spi1;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 cpu@0 {
48 compatible = "arm,cortex-a8";
49 device_type = "cpu";
50 reg = <0>;
51
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]52 operating-points-v2 = <&cpu0_opp_table>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]53
54 clocks = <&dpll_mpu_ck>;
55 clock-names = "cpu";
56
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 };
59 };
60
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]61 cpu0_opp_table: opp-table {
62 compatible = "operating-points-v2-ti-cpu";
63 syscon = <&scm_conf>;
64
65 /*
66 * The three following nodes are marked with opp-suspend
67 * because the can not be enabled simultaneously on a
68 * single SoC.
69 */
70 opp50-300000000 {
71 opp-hz = /bits/ 64 <300000000>;
72 opp-microvolt = <950000 931000 969000>;
73 opp-supported-hw = <0x06 0x0010>;
74 opp-suspend;
75 };
76
77 opp100-275000000 {
78 opp-hz = /bits/ 64 <275000000>;
79 opp-microvolt = <1100000 1078000 1122000>;
80 opp-supported-hw = <0x01 0x00FF>;
81 opp-suspend;
82 };
83
84 opp100-300000000 {
85 opp-hz = /bits/ 64 <300000000>;
86 opp-microvolt = <1100000 1078000 1122000>;
87 opp-supported-hw = <0x06 0x0020>;
88 opp-suspend;
89 };
90
91 opp100-500000000 {
92 opp-hz = /bits/ 64 <500000000>;
93 opp-microvolt = <1100000 1078000 1122000>;
94 opp-supported-hw = <0x01 0xFFFF>;
95 };
96
97 opp100-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0040>;
101 };
102
103 opp120-600000000 {
104 opp-hz = /bits/ 64 <600000000>;
105 opp-microvolt = <1200000 1176000 1224000>;
106 opp-supported-hw = <0x01 0xFFFF>;
107 };
108
109 opp120-720000000 {
110 opp-hz = /bits/ 64 <720000000>;
111 opp-microvolt = <1200000 1176000 1224000>;
112 opp-supported-hw = <0x06 0x0080>;
113 };
114
115 oppturbo-720000000 {
116 opp-hz = /bits/ 64 <720000000>;
117 opp-microvolt = <1260000 1234800 1285200>;
118 opp-supported-hw = <0x01 0xFFFF>;
119 };
120
121 oppturbo-800000000 {
122 opp-hz = /bits/ 64 <800000000>;
123 opp-microvolt = <1260000 1234800 1285200>;
124 opp-supported-hw = <0x06 0x0100>;
125 };
126
127 oppnitro-1000000000 {
128 opp-hz = /bits/ 64 <1000000000>;
129 opp-microvolt = <1325000 1298500 1351500>;
130 opp-supported-hw = <0x04 0x0200>;
131 };
132 };
133
134 pmu@4b000000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]135 compatible = "arm,cortex-a8-pmu";
136 interrupts = <3>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]137 reg = <0x4b000000 0x1000000>;
138 ti,hwmods = "debugss";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]139 };
140
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]141 /*
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]142 * The soc node represents the soc top level view. It is used for IPs
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]143 * that are not memory mapped in the MPU view or for the MPU itself.
144 */
145 soc {
146 compatible = "ti,omap-infra";
147 mpu {
148 compatible = "ti,omap3-mpu";
149 ti,hwmods = "mpu";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]150 pm-sram = <&pm_sram_code
151 &pm_sram_data>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]152 };
153 };
154
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]155 /*
156 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]157 * The real AM33XX interconnect network is quite complex. Since
158 * it will not bring real advantage to represent that in DT
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]159 * for the moment, just use a fake OCP bus entry to represent
160 * the whole bus hierarchy.
161 */
162 ocp {
163 compatible = "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges;
167 ti,hwmods = "l3_main";
168
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]169 l4_wkup: l4_wkup@44c00000 {
170 compatible = "ti,am3-l4-wkup", "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0 0x44c00000 0x280000>;
174
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]175 wkup_m3: wkup_m3@100000 {
176 compatible = "ti,am3352-wkup-m3";
177 reg = <0x100000 0x4000>,
178 <0x180000 0x2000>;
179 reg-names = "umem", "dmem";
180 ti,hwmods = "wkup_m3";
181 ti,pm-firmware = "am335x-pm-firmware.elf";
182 };
183
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]184 prcm: prcm@200000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]185 compatible = "ti,am3-prcm", "simple-bus";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]186 reg = <0x200000 0x4000>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]187 #address-cells = <1>;
188 #size-cells = <1>;
189 ranges = <0 0x200000 0x4000>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]190
191 prcm_clocks: clocks {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 };
195
196 prcm_clockdomains: clockdomains {
197 };
198 };
199
200 scm: scm@210000 {
201 compatible = "ti,am3-scm", "simple-bus";
202 reg = <0x210000 0x2000>;
203 #address-cells = <1>;
204 #size-cells = <1>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]205 #pinctrl-cells = <1>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]206 ranges = <0 0x210000 0x2000>;
207
208 am33xx_pinmux: pinmux@800 {
209 compatible = "pinctrl-single";
210 reg = <0x800 0x238>;
211 #address-cells = <1>;
212 #size-cells = <0>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]213 #pinctrl-cells = <1>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]214 pinctrl-single,register-width = <32>;
215 pinctrl-single,function-mask = <0x7f>;
216 };
217
218 scm_conf: scm_conf@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]219 compatible = "syscon", "simple-bus";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]220 reg = <0x0 0x800>;
221 #address-cells = <1>;
222 #size-cells = <1>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]223 ranges = <0 0 0x800>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]224
225 scm_clocks: clocks {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 };
229 };
230
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]231 wkup_m3_ipc: wkup_m3_ipc@1324 {
232 compatible = "ti,am3352-wkup-m3-ipc";
233 reg = <0x1324 0x24>;
234 interrupts = <78>;
235 ti,rproc = <&wkup_m3>;
236 mboxes = <&mailbox &mbox_wkupm3>;
237 };
238
239 edma_xbar: dma-router@f90 {
240 compatible = "ti,am335x-edma-crossbar";
241 reg = <0xf90 0x40>;
242 #dma-cells = <3>;
243 dma-requests = <32>;
244 dma-masters = <&edma>;
245 };
246
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]247 scm_clockdomains: clockdomains {
248 };
249 };
250 };
251
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]252 intc: interrupt-controller@48200000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]253 compatible = "ti,am33xx-intc";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]254 interrupt-controller;
255 #interrupt-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]256 reg = <0x48200000 0x1000>;
257 };
258
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]259 edma: edma@49000000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]260 compatible = "ti,edma3-tpcc";
261 ti,hwmods = "tpcc";
262 reg = <0x49000000 0x10000>;
263 reg-names = "edma3_cc";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]264 interrupts = <12 13 14>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]265 interrupt-names = "edma3_ccint", "edma3_mperr",
266 "edma3_ccerrint";
267 dma-requests = <64>;
268 #dma-cells = <2>;
269
270 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
271 <&edma_tptc2 0>;
272
273 ti,edma-memcpy-channels = <20 21>;
274 };
275
276 edma_tptc0: tptc@49800000 {
277 compatible = "ti,edma3-tptc";
278 ti,hwmods = "tptc0";
279 reg = <0x49800000 0x100000>;
280 interrupts = <112>;
281 interrupt-names = "edma3_tcerrint";
282 };
283
284 edma_tptc1: tptc@49900000 {
285 compatible = "ti,edma3-tptc";
286 ti,hwmods = "tptc1";
287 reg = <0x49900000 0x100000>;
288 interrupts = <113>;
289 interrupt-names = "edma3_tcerrint";
290 };
291
292 edma_tptc2: tptc@49a00000 {
293 compatible = "ti,edma3-tptc";
294 ti,hwmods = "tptc2";
295 reg = <0x49a00000 0x100000>;
296 interrupts = <114>;
297 interrupt-names = "edma3_tcerrint";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]298 };
299
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]300 gpio0: gpio@44e07000 {
301 compatible = "ti,omap4-gpio";
302 ti,hwmods = "gpio1";
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]306 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]307 reg = <0x44e07000 0x1000>;
308 interrupts = <96>;
309 };
310
311 gpio1: gpio@4804c000 {
312 compatible = "ti,omap4-gpio";
313 ti,hwmods = "gpio2";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]317 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]318 reg = <0x4804c000 0x1000>;
319 interrupts = <98>;
320 };
321
322 gpio2: gpio@481ac000 {
323 compatible = "ti,omap4-gpio";
324 ti,hwmods = "gpio3";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]328 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]329 reg = <0x481ac000 0x1000>;
330 interrupts = <32>;
331 };
332
333 gpio3: gpio@481ae000 {
334 compatible = "ti,omap4-gpio";
335 ti,hwmods = "gpio4";
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]339 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]340 reg = <0x481ae000 0x1000>;
341 interrupts = <62>;
342 };
343
344 uart0: serial@44e09000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]345 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]346 ti,hwmods = "uart1";
347 clock-frequency = <48000000>;
348 reg = <0x44e09000 0x2000>;
349 interrupts = <72>;
350 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]351 dmas = <&edma 26 0>, <&edma 27 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]352 dma-names = "tx", "rx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]353 };
354
355 uart1: serial@48022000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]356 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]357 ti,hwmods = "uart2";
358 clock-frequency = <48000000>;
359 reg = <0x48022000 0x2000>;
360 interrupts = <73>;
361 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]362 dmas = <&edma 28 0>, <&edma 29 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]363 dma-names = "tx", "rx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]364 };
365
366 uart2: serial@48024000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]367 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]368 ti,hwmods = "uart3";
369 clock-frequency = <48000000>;
370 reg = <0x48024000 0x2000>;
371 interrupts = <74>;
372 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]373 dmas = <&edma 30 0>, <&edma 31 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]374 dma-names = "tx", "rx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]375 };
376
377 uart3: serial@481a6000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]378 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]379 ti,hwmods = "uart4";
380 clock-frequency = <48000000>;
381 reg = <0x481a6000 0x2000>;
382 interrupts = <44>;
383 status = "disabled";
384 };
385
386 uart4: serial@481a8000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]387 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]388 ti,hwmods = "uart5";
389 clock-frequency = <48000000>;
390 reg = <0x481a8000 0x2000>;
391 interrupts = <45>;
392 status = "disabled";
393 };
394
395 uart5: serial@481aa000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]396 compatible = "ti,am3352-uart", "ti,omap3-uart";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]397 ti,hwmods = "uart6";
398 clock-frequency = <48000000>;
399 reg = <0x481aa000 0x2000>;
400 interrupts = <46>;
401 status = "disabled";
402 };
403
404 i2c0: i2c@44e0b000 {
405 compatible = "ti,omap4-i2c";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 ti,hwmods = "i2c1";
409 reg = <0x44e0b000 0x1000>;
410 interrupts = <70>;
411 status = "disabled";
412 };
413
414 i2c1: i2c@4802a000 {
415 compatible = "ti,omap4-i2c";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "i2c2";
419 reg = <0x4802a000 0x1000>;
420 interrupts = <71>;
421 status = "disabled";
422 };
423
424 i2c2: i2c@4819c000 {
425 compatible = "ti,omap4-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 ti,hwmods = "i2c3";
429 reg = <0x4819c000 0x1000>;
430 interrupts = <30>;
431 status = "disabled";
432 };
433
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]434 mmc1: mmc@48060000 {
435 compatible = "ti,omap4-hsmmc";
436 ti,hwmods = "mmc1";
437 ti,dual-volt;
438 ti,needs-special-reset;
439 ti,needs-special-hs-handling;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]440 dmas = <&edma_xbar 24 0 0
441 &edma_xbar 25 0 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]442 dma-names = "tx", "rx";
443 interrupts = <64>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]444 reg = <0x48060000 0x1000>;
445 status = "disabled";
446 };
447
448 mmc2: mmc@481d8000 {
449 compatible = "ti,omap4-hsmmc";
450 ti,hwmods = "mmc2";
451 ti,needs-special-reset;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]452 dmas = <&edma 2 0
453 &edma 3 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]454 dma-names = "tx", "rx";
455 interrupts = <28>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]456 reg = <0x481d8000 0x1000>;
457 status = "disabled";
458 };
459
460 mmc3: mmc@47810000 {
461 compatible = "ti,omap4-hsmmc";
462 ti,hwmods = "mmc3";
463 ti,needs-special-reset;
464 interrupts = <29>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]465 reg = <0x47810000 0x1000>;
466 status = "disabled";
467 };
468
469 hwspinlock: spinlock@480ca000 {
470 compatible = "ti,omap4-hwspinlock";
471 reg = <0x480ca000 0x1000>;
472 ti,hwmods = "spinlock";
473 #hwlock-cells = <1>;
474 };
475
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]476 wdt2: wdt@44e35000 {
477 compatible = "ti,omap3-wdt";
478 ti,hwmods = "wd_timer2";
479 reg = <0x44e35000 0x1000>;
480 interrupts = <91>;
481 };
482
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]483 dcan0: can@481cc000 {
484 compatible = "ti,am3352-d_can";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]485 ti,hwmods = "d_can0";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]486 reg = <0x481cc000 0x2000>;
487 clocks = <&dcan0_fck>;
488 clock-names = "fck";
489 syscon-raminit = <&scm_conf 0x644 0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]490 interrupts = <52>;
491 status = "disabled";
492 };
493
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]494 dcan1: can@481d0000 {
495 compatible = "ti,am3352-d_can";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]496 ti,hwmods = "d_can1";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]497 reg = <0x481d0000 0x2000>;
498 clocks = <&dcan1_fck>;
499 clock-names = "fck";
500 syscon-raminit = <&scm_conf 0x644 1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]501 interrupts = <55>;
502 status = "disabled";
503 };
504
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]505 mailbox: mailbox@480c8000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]506 compatible = "ti,omap4-mailbox";
507 reg = <0x480C8000 0x200>;
508 interrupts = <77>;
509 ti,hwmods = "mailbox";
510 #mbox-cells = <1>;
511 ti,mbox-num-users = <4>;
512 ti,mbox-num-fifos = <8>;
513 mbox_wkupm3: wkup_m3 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]514 ti,mbox-send-noirq;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]515 ti,mbox-tx = <0 0 0>;
516 ti,mbox-rx = <0 0 3>;
517 };
518 };
519
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]520 timer1: timer@44e31000 {
521 compatible = "ti,am335x-timer-1ms";
522 reg = <0x44e31000 0x400>;
523 interrupts = <67>;
524 ti,hwmods = "timer1";
525 ti,timer-alwon;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]526 clocks = <&timer1_fck>;
527 clock-names = "fck";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]528 };
529
530 timer2: timer@48040000 {
531 compatible = "ti,am335x-timer";
532 reg = <0x48040000 0x400>;
533 interrupts = <68>;
534 ti,hwmods = "timer2";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]535 clocks = <&timer2_fck>;
536 clock-names = "fck";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]537 };
538
539 timer3: timer@48042000 {
540 compatible = "ti,am335x-timer";
541 reg = <0x48042000 0x400>;
542 interrupts = <69>;
543 ti,hwmods = "timer3";
544 };
545
546 timer4: timer@48044000 {
547 compatible = "ti,am335x-timer";
548 reg = <0x48044000 0x400>;
549 interrupts = <92>;
550 ti,hwmods = "timer4";
551 ti,timer-pwm;
552 };
553
554 timer5: timer@48046000 {
555 compatible = "ti,am335x-timer";
556 reg = <0x48046000 0x400>;
557 interrupts = <93>;
558 ti,hwmods = "timer5";
559 ti,timer-pwm;
560 };
561
562 timer6: timer@48048000 {
563 compatible = "ti,am335x-timer";
564 reg = <0x48048000 0x400>;
565 interrupts = <94>;
566 ti,hwmods = "timer6";
567 ti,timer-pwm;
568 };
569
570 timer7: timer@4804a000 {
571 compatible = "ti,am335x-timer";
572 reg = <0x4804a000 0x400>;
573 interrupts = <95>;
574 ti,hwmods = "timer7";
575 ti,timer-pwm;
576 };
577
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]578 rtc: rtc@44e3e000 {
579 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]580 reg = <0x44e3e000 0x1000>;
581 interrupts = <75
582 76>;
583 ti,hwmods = "rtc";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]584 clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
585 clock-names = "int-clk";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]586 };
587
588 spi0: spi@48030000 {
589 compatible = "ti,omap4-mcspi";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x48030000 0x400>;
593 interrupts = <65>;
594 ti,spi-num-cs = <2>;
595 ti,hwmods = "spi0";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]596 dmas = <&edma 16 0
597 &edma 17 0
598 &edma 18 0
599 &edma 19 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]600 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]601 status = "disabled";
602 };
603
604 spi1: spi@481a0000 {
605 compatible = "ti,omap4-mcspi";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 reg = <0x481a0000 0x400>;
609 interrupts = <125>;
610 ti,spi-num-cs = <2>;
611 ti,hwmods = "spi1";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]612 dmas = <&edma 42 0
613 &edma 43 0
614 &edma 44 0
615 &edma 45 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]616 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]617 status = "disabled";
618 };
619
620 usb: usb@47400000 {
621 compatible = "ti,am33xx-usb";
622 reg = <0x47400000 0x1000>;
623 ranges;
624 #address-cells = <1>;
625 #size-cells = <1>;
626 ti,hwmods = "usb_otg_hs";
627 status = "disabled";
628
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]629 usb_ctrl_mod: control@44e10620 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]630 compatible = "ti,am335x-usb-ctrl-module";
631 reg = <0x44e10620 0x10
632 0x44e10648 0x4>;
633 reg-names = "phy_ctrl", "wakeup";
634 status = "disabled";
635 };
636
637 usb0_phy: usb-phy@47401300 {
638 compatible = "ti,am335x-usb-phy";
639 reg = <0x47401300 0x100>;
640 reg-names = "phy";
641 status = "disabled";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]642 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]643 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]644 };
645
646 usb0: usb@47401000 {
647 compatible = "ti,musb-am33xx";
648 status = "disabled";
649 reg = <0x47401400 0x400
650 0x47401000 0x200>;
651 reg-names = "mc", "control";
652
653 interrupts = <18>;
654 interrupt-names = "mc";
655 dr_mode = "otg";
656 mentor,multipoint = <1>;
657 mentor,num-eps = <16>;
658 mentor,ram-bits = <12>;
659 mentor,power = <500>;
660 phys = <&usb0_phy>;
661
662 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
663 &cppi41dma 2 0 &cppi41dma 3 0
664 &cppi41dma 4 0 &cppi41dma 5 0
665 &cppi41dma 6 0 &cppi41dma 7 0
666 &cppi41dma 8 0 &cppi41dma 9 0
667 &cppi41dma 10 0 &cppi41dma 11 0
668 &cppi41dma 12 0 &cppi41dma 13 0
669 &cppi41dma 14 0 &cppi41dma 0 1
670 &cppi41dma 1 1 &cppi41dma 2 1
671 &cppi41dma 3 1 &cppi41dma 4 1
672 &cppi41dma 5 1 &cppi41dma 6 1
673 &cppi41dma 7 1 &cppi41dma 8 1
674 &cppi41dma 9 1 &cppi41dma 10 1
675 &cppi41dma 11 1 &cppi41dma 12 1
676 &cppi41dma 13 1 &cppi41dma 14 1>;
677 dma-names =
678 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
679 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
680 "rx14", "rx15",
681 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
682 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
683 "tx14", "tx15";
684 };
685
686 usb1_phy: usb-phy@47401b00 {
687 compatible = "ti,am335x-usb-phy";
688 reg = <0x47401b00 0x100>;
689 reg-names = "phy";
690 status = "disabled";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]691 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]692 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]693 };
694
695 usb1: usb@47401800 {
696 compatible = "ti,musb-am33xx";
697 status = "disabled";
698 reg = <0x47401c00 0x400
699 0x47401800 0x200>;
700 reg-names = "mc", "control";
701 interrupts = <19>;
702 interrupt-names = "mc";
703 dr_mode = "otg";
704 mentor,multipoint = <1>;
705 mentor,num-eps = <16>;
706 mentor,ram-bits = <12>;
707 mentor,power = <500>;
708 phys = <&usb1_phy>;
709
710 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
711 &cppi41dma 17 0 &cppi41dma 18 0
712 &cppi41dma 19 0 &cppi41dma 20 0
713 &cppi41dma 21 0 &cppi41dma 22 0
714 &cppi41dma 23 0 &cppi41dma 24 0
715 &cppi41dma 25 0 &cppi41dma 26 0
716 &cppi41dma 27 0 &cppi41dma 28 0
717 &cppi41dma 29 0 &cppi41dma 15 1
718 &cppi41dma 16 1 &cppi41dma 17 1
719 &cppi41dma 18 1 &cppi41dma 19 1
720 &cppi41dma 20 1 &cppi41dma 21 1
721 &cppi41dma 22 1 &cppi41dma 23 1
722 &cppi41dma 24 1 &cppi41dma 25 1
723 &cppi41dma 26 1 &cppi41dma 27 1
724 &cppi41dma 28 1 &cppi41dma 29 1>;
725 dma-names =
726 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
727 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
728 "rx14", "rx15",
729 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
730 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
731 "tx14", "tx15";
732 };
733
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]734 cppi41dma: dma-controller@47402000 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]735 compatible = "ti,am3359-cppi41";
736 reg = <0x47400000 0x1000
737 0x47402000 0x1000
738 0x47403000 0x1000
739 0x47404000 0x4000>;
740 reg-names = "glue", "controller", "scheduler", "queuemgr";
741 interrupts = <17>;
742 interrupt-names = "glue";
743 #dma-cells = <2>;
744 #dma-channels = <30>;
745 #dma-requests = <256>;
746 status = "disabled";
747 };
748 };
749
750 epwmss0: epwmss@48300000 {
751 compatible = "ti,am33xx-pwmss";
752 reg = <0x48300000 0x10>;
753 ti,hwmods = "epwmss0";
754 #address-cells = <1>;
755 #size-cells = <1>;
756 status = "disabled";
757 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
758 0x48300180 0x48300180 0x80 /* EQEP */
759 0x48300200 0x48300200 0x80>; /* EHRPWM */
760
761 ecap0: ecap@48300100 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]762 compatible = "ti,am3352-ecap",
763 "ti,am33xx-ecap";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]764 #pwm-cells = <3>;
765 reg = <0x48300100 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]766 clocks = <&l4ls_gclk>;
767 clock-names = "fck";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]768 interrupts = <31>;
769 interrupt-names = "ecap0";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]770 status = "disabled";
771 };
772
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]773 ehrpwm0: pwm@48300200 {
774 compatible = "ti,am3352-ehrpwm",
775 "ti,am33xx-ehrpwm";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]776 #pwm-cells = <3>;
777 reg = <0x48300200 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]778 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
779 clock-names = "tbclk", "fck";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]780 status = "disabled";
781 };
782 };
783
784 epwmss1: epwmss@48302000 {
785 compatible = "ti,am33xx-pwmss";
786 reg = <0x48302000 0x10>;
787 ti,hwmods = "epwmss1";
788 #address-cells = <1>;
789 #size-cells = <1>;
790 status = "disabled";
791 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
792 0x48302180 0x48302180 0x80 /* EQEP */
793 0x48302200 0x48302200 0x80>; /* EHRPWM */
794
795 ecap1: ecap@48302100 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]796 compatible = "ti,am3352-ecap",
797 "ti,am33xx-ecap";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]798 #pwm-cells = <3>;
799 reg = <0x48302100 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]800 clocks = <&l4ls_gclk>;
801 clock-names = "fck";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]802 interrupts = <47>;
803 interrupt-names = "ecap1";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]804 status = "disabled";
805 };
806
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]807 ehrpwm1: pwm@48302200 {
808 compatible = "ti,am3352-ehrpwm",
809 "ti,am33xx-ehrpwm";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]810 #pwm-cells = <3>;
811 reg = <0x48302200 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]812 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
813 clock-names = "tbclk", "fck";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]814 status = "disabled";
815 };
816 };
817
818 epwmss2: epwmss@48304000 {
819 compatible = "ti,am33xx-pwmss";
820 reg = <0x48304000 0x10>;
821 ti,hwmods = "epwmss2";
822 #address-cells = <1>;
823 #size-cells = <1>;
824 status = "disabled";
825 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
826 0x48304180 0x48304180 0x80 /* EQEP */
827 0x48304200 0x48304200 0x80>; /* EHRPWM */
828
829 ecap2: ecap@48304100 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]830 compatible = "ti,am3352-ecap",
831 "ti,am33xx-ecap";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]832 #pwm-cells = <3>;
833 reg = <0x48304100 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]834 clocks = <&l4ls_gclk>;
835 clock-names = "fck";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]836 interrupts = <61>;
837 interrupt-names = "ecap2";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]838 status = "disabled";
839 };
840
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]841 ehrpwm2: pwm@48304200 {
842 compatible = "ti,am3352-ehrpwm",
843 "ti,am33xx-ehrpwm";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]844 #pwm-cells = <3>;
845 reg = <0x48304200 0x80>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]846 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
847 clock-names = "tbclk", "fck";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]848 status = "disabled";
849 };
850 };
851
852 mac: ethernet@4a100000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]853 compatible = "ti,am335x-cpsw","ti,cpsw";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]854 ti,hwmods = "cpgmac0";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]855 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
856 clock-names = "fck", "cpts";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]857 cpdma_channels = <8>;
858 ale_entries = <1024>;
859 bd_ram_size = <0x2000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]860 mac_control = <0x20>;
861 slaves = <2>;
862 active_slave = <0>;
863 cpts_clock_mult = <0x80000000>;
864 cpts_clock_shift = <29>;
865 reg = <0x4a100000 0x800
866 0x4a101200 0x100>;
867 #address-cells = <1>;
868 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]869 /*
870 * c0_rx_thresh_pend
871 * c0_rx_pend
872 * c0_tx_pend
873 * c0_misc_pend
874 */
875 interrupts = <40 41 42 43>;
876 ranges;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]877 syscon = <&scm_conf>;
878 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]879
880 davinci_mdio: mdio@4a101000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]881 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]882 #address-cells = <1>;
883 #size-cells = <0>;
884 ti,hwmods = "davinci_mdio";
885 bus_freq = <1000000>;
886 reg = <0x4a101000 0x100>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]887 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]888 };
889
890 cpsw_emac0: slave@4a100200 {
891 /* Filled in by U-Boot */
892 mac-address = [ 00 00 00 00 00 00 ];
893 };
894
895 cpsw_emac1: slave@4a100300 {
896 /* Filled in by U-Boot */
897 mac-address = [ 00 00 00 00 00 00 ];
898 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]899
900 phy_sel: cpsw-phy-sel@44e10650 {
901 compatible = "ti,am3352-cpsw-phy-sel";
902 reg= <0x44e10650 0x4>;
903 reg-names = "gmii-sel";
904 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]905 };
906
907 ocmcram: ocmcram@40300000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]908 compatible = "mmio-sram";
909 reg = <0x40300000 0x10000>; /* 64k */
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]910 ranges = <0x0 0x40300000 0x10000>;
911 #address-cells = <1>;
912 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]913
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]914 pm_sram_code: pm-sram-code@0 {
915 compatible = "ti,sram";
916 reg = <0x0 0x1000>;
917 protect-exec;
918 };
919
920 pm_sram_data: pm-sram-data@1000 {
921 compatible = "ti,sram";
922 reg = <0x1000 0x1000>;
923 pool;
924 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]925 };
926
927 elm: elm@48080000 {
928 compatible = "ti,am3352-elm";
929 reg = <0x48080000 0x2000>;
930 interrupts = <4>;
931 ti,hwmods = "elm";
932 status = "disabled";
933 };
934
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]935 lcdc: lcdc@4830e000 {
936 compatible = "ti,am33xx-tilcdc";
937 reg = <0x4830e000 0x1000>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]938 interrupts = <36>;
939 ti,hwmods = "lcdc";
940 status = "disabled";
941 };
942
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]943 tscadc: tscadc@44e0d000 {
944 compatible = "ti,am3359-tscadc";
945 reg = <0x44e0d000 0x1000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]946 interrupts = <16>;
947 ti,hwmods = "adc_tsc";
948 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]949 dmas = <&edma 53 0>, <&edma 57 0>;
950 dma-names = "fifo0", "fifo1";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]951
952 tsc {
953 compatible = "ti,am3359-tsc";
954 };
955 am335x_adc: adc {
956 #io-channel-cells = <1>;
957 compatible = "ti,am3359-adc";
958 };
959 };
960
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]961 emif: emif@4c000000 {
962 compatible = "ti,emif-am3352";
963 reg = <0x4c000000 0x1000000>;
964 ti,hwmods = "emif";
965 interrupts = <101>;
966 sram = <&pm_sram_code
967 &pm_sram_data>;
968 ti,no-idle;
969 };
970
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]971 gpmc: gpmc@50000000 {
972 compatible = "ti,am3352-gpmc";
973 ti,hwmods = "gpmc";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]974 ti,no-idle-on-init;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]975 reg = <0x50000000 0x2000>;
976 interrupts = <100>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]977 dmas = <&edma 52 0>;
978 dma-names = "rxtx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]979 gpmc,num-cs = <7>;
980 gpmc,num-waitpins = <2>;
981 #address-cells = <2>;
982 #size-cells = <1>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]983 interrupt-controller;
984 #interrupt-cells = <2>;
985 gpio-controller;
986 #gpio-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]987 status = "disabled";
988 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]989
990 sham: sham@53100000 {
991 compatible = "ti,omap4-sham";
992 ti,hwmods = "sham";
993 reg = <0x53100000 0x200>;
994 interrupts = <109>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]995 dmas = <&edma 36 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]996 dma-names = "rx";
997 };
998
999 aes: aes@53500000 {
1000 compatible = "ti,omap4-aes";
1001 ti,hwmods = "aes";
1002 reg = <0x53500000 0xa0>;
1003 interrupts = <103>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]1004 dmas = <&edma 6 0>,
1005 <&edma 5 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1006 dma-names = "tx", "rx";
1007 };
1008
1009 mcasp0: mcasp@48038000 {
1010 compatible = "ti,am33xx-mcasp-audio";
1011 ti,hwmods = "mcasp0";
1012 reg = <0x48038000 0x2000>,
1013 <0x46000000 0x400000>;
1014 reg-names = "mpu", "dat";
1015 interrupts = <80>, <81>;
1016 interrupt-names = "tx", "rx";
1017 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]1018 dmas = <&edma 8 2>,
1019 <&edma 9 2>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1020 dma-names = "tx", "rx";
1021 };
1022
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]1023 mcasp1: mcasp@4803c000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1024 compatible = "ti,am33xx-mcasp-audio";
1025 ti,hwmods = "mcasp1";
1026 reg = <0x4803C000 0x2000>,
1027 <0x46400000 0x400000>;
1028 reg-names = "mpu", "dat";
1029 interrupts = <82>, <83>;
1030 interrupt-names = "tx", "rx";
1031 status = "disabled";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]1032 dmas = <&edma 10 2>,
1033 <&edma 11 2>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1034 dma-names = "tx", "rx";
1035 };
1036
1037 rng: rng@48310000 {
1038 compatible = "ti,omap4-rng";
1039 ti,hwmods = "rng";
1040 reg = <0x48310000 0x2000>;
1041 interrupts = <111>;
1042 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]1043 };
1044};
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1045
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]1046#include "am33xx-clocks.dtsi"