- e4f6949 riscv: add backtrace support by Ben Dooks · 1 year, 5 months ago
- 0b9441a riscv: Remove common.h usage by Tom Rini · 1 year, 4 months ago
- 6419f8e riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · 1 year, 6 months ago
- 28ff3f1 riscv: setup per-hart stack earlier by Bo Gan · 1 year, 8 months ago
- 3f37baa riscv: spl: Remove relocation sections by Bin Meng · 1 year, 10 months ago
- 3c09ac2 riscv: Avoid updating the link register by Bin Meng · 1 year, 10 months ago
- 485f593 riscv: Change to use positive offset to access relocation entries by Bin Meng · 1 year, 10 months ago
- 0b1a3a2 riscv: Optimize loading relocation type by Bin Meng · 1 year, 10 months ago
- 883f553 riscv: Optimize source end address calculation in start.S by Bin Meng · 1 year, 10 months ago
- e0465f8 riscv: Introduce AVAILABLE_HARTS by Rick Chen · 2 years, 4 months ago
- c2bdf02 spl: introduce SPL_XIP to config by Nikita Shubin · 2 years, 5 months ago
- f451261 riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · 2 years, 8 months ago
- a5041e3 riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · 2 years, 8 months ago
- eaf6ea6 Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · 2 years, 8 months ago
- 2e8d2f8 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · 3 years, 4 months ago
- edd9ad8 riscv: cpu: Add callback to init each core by Green Wan · 3 years, 9 months ago
- fb33eaa riscv: fix the wrong swap value register by Brad Kim · 4 years, 3 months ago
- 924de32 riscv: Add some comments to start.S by Sean Anderson · 4 years, 4 months ago
- 8576813 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · 4 years, 4 months ago
- 309995b riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · 4 years, 4 months ago
- c410454 Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · 4 years, 4 months ago
- e491e15 riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · 4 years, 7 months ago
- 9472630 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · 4 years, 7 months ago
- d4ea649 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · 4 years, 9 months ago
- 191636e riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · 4 years, 10 months ago
- 84dc9d2 riscv: Merge unnecessary SMP ifdefs in start.S by Bin Meng · 4 years, 10 months ago
- 4043397 riscv: Remove unnecessary instruction by Sean Anderson · 5 years ago
- 9413387 common: Move relocate_code() to init.h by Simon Glass · 5 years ago
- 90ae281 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · 5 years ago
- 444c464 riscv: Fix clear bss loop in the start-up code by Rick Chen · 5 years ago
- f6cb427 riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
- c7e1eff riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
- 8c59f20 riscv: add SPL support by Lukas Auer · 5 years ago
- fbfd92b riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
- 4d2583d riscv: Access CSRs using CSR numbers by Bin Meng · 6 years ago
- f9281b8 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
- bdce389 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
- 8ac39e2 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
- e043240 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
- 3dea63c riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
- 1446b26 riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
- 2503ccc riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
- 51ab457 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
- 4b3f5ed riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
- 48cbf62 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago
- d2db2a8 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · 6 years ago
- 52923c6 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
- 5d8b2e7 riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
- 31f9058 riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
- 8bfa231 riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
- c95cafd Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
- 2a23ac6 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
- c55309c riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
- b5369c5 riscv: Make start.S available for all targets by Bin Meng · 6 years ago[Renamed from arch/riscv/cpu/ax25/start.S]
- 6f4dd62 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 7 years ago[Renamed from arch/riscv/cpu/nx25/start.S]
- 83d290c SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
- d58717e riscv: ae250: Support DT provided by the board at runtime by Rick Chen · 7 years ago
- e8e3959 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · 7 years ago