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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5be172819fc870f949c182dbdf7cfd54d0651cb3 / arch / riscv / cpu
  1. 7fe32b3 event: Convert arch_cpu_init_dm() to use events by Simon Glass · 2 years, 9 months ago
  2. c0ffc12 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · 3 years ago
  3. 2e8d2f8 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · 3 years, 1 month ago
  4. 1b2b52f riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · 3 years, 2 months ago
  5. 24ed531 sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · 3 years, 2 months ago
  6. 835210a board: sifive: use ccache driver instead of helper function by Zong Li · 3 years, 3 months ago
  7. 662e300 riscv: cpu: fu740: Fix typo of date by Zong Li · 3 years, 4 months ago
  8. 975e7cf i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · 3 years, 4 months ago
  9. 564d630 riscv: sifive: fu740: Support i2c in spl by Zong Li · 3 years, 5 months ago
  10. e2172aa riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · 3 years, 5 months ago
  11. c552deb riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 6 months ago
  12. d56d79e drivers: clk: add fu740 support by Green Wan · 3 years, 6 months ago
  13. a74e9d8 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · 3 years, 6 months ago
  14. 236f2ec treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · 3 years, 6 months ago
  15. 756eeba riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · 3 years, 6 months ago
  16. a6d7e8c riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · 3 years, 6 months ago
  17. ffdc71b Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · 3 years, 6 months ago
  18. bc8bbb7 riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 7 months ago
  19. edd9ad8 riscv: cpu: Add callback to init each core by Green Wan · 3 years, 7 months ago
  20. 529d5f9 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · 3 years, 8 months ago
  21. 2ae8043 Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · 3 years, 9 months ago
  22. 85c714d riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · 3 years, 10 months ago
  23. 401d1c4 common: Drop asm/global_data.h from common header by Simon Glass · 4 years, 1 month ago
  24. fb33eaa riscv: fix the wrong swap value register by Brad Kim · 4 years ago
  25. f517e5f riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · 4 years ago
  26. 7dbebeb timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · 4 years, 1 month ago
  27. 924de32 riscv: Add some comments to start.S by Sean Anderson · 4 years, 2 months ago
  28. 8576813 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · 4 years, 2 months ago
  29. 309995b riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · 4 years, 2 months ago
  30. 768502e riscv: Clear pending IPIs on initialization by Sean Anderson · 4 years, 2 months ago
  31. c410454 Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · 4 years, 2 months ago
  32. c33efaf riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · 4 years, 2 months ago
  33. 52dc7ae riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · 4 years, 3 months ago
  34. 6a43e3a riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · 4 years, 4 months ago
  35. ff8e88a riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · 4 years, 4 months ago
  36. d6a0170 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · 4 years, 4 months ago
  37. e491e15 riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · 4 years, 5 months ago
  38. ff7d25e env: Enable SPI flash env for SiFive FU540 by Jagan Teki · 4 years, 4 months ago
  39. a0018fc riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · 4 years, 4 months ago
  40. 6e7d7aa Merge branch 'next' by Tom Rini · 4 years, 5 months ago
  41. 5ce5020 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · 4 years, 6 months ago
  42. b8bc120 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · 4 years, 5 months ago
  43. 40686c3 riscv: Clean up IPI initialization code by Sean Anderson · 4 years, 5 months ago
  44. 9472630 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · 4 years, 5 months ago
  45. 01cdef2 riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · 4 years, 6 months ago
  46. 7c45fc9 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · 4 years, 6 months ago
  47. bbb94af riscv: Add _image_binary_end for SPL by Pragnesh Patel · 4 years, 6 months ago
  48. cd93d62 common: Drop linux/bitops.h from common header by Simon Glass · 4 years, 6 months ago
  49. 691d719 common: Drop init.h from common header by Simon Glass · 4 years, 6 months ago
  50. 90526e9 common: Drop net.h from common header by Simon Glass · 4 years, 6 months ago
  51. d4ea649 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · 4 years, 7 months ago
  52. 191636e riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · 4 years, 7 months ago
  53. 84dc9d2 riscv: Merge unnecessary SMP ifdefs in start.S by Bin Meng · 4 years, 7 months ago
  54. ed1475e riscv: qemu: Remove the simple-bus driver for the SoC node by Bin Meng · 4 years, 7 months ago
  55. 5988bb9 riscv: ax25: cache: Remove SPL_RISCV_MMODE config check by Pragnesh Patel · 4 years, 8 months ago
  56. 4043397 riscv: Remove unnecessary instruction by Sean Anderson · 4 years, 10 months ago
  57. fd1f6e9 riscv: Add option to print registers on exception by Sean Anderson · 5 years ago
  58. d9f1cee riscv: Fix breakage caused by linker relaxation by Sean Anderson · 5 years ago
  59. 9413387 common: Move relocate_code() to init.h by Simon Glass · 5 years ago
  60. 90ae281 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · 5 years ago
  61. 444c464 riscv: Fix clear bss loop in the start-up code by Rick Chen · 5 years ago
  62. 8ba595b riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL by Rick Chen · 5 years ago
  63. ca06444 riscv: ax25: add SPL support by Rick Chen · 5 years ago
  64. 67c4e9f common: Move board_get_usable_ram_top() out of common.h by Simon Glass · 5 years ago
  65. 36bf446 common: Move enable/disable_interrupts out of common.h by Simon Glass · 5 years ago
  66. 1eb69ae common: Move ARM cache operations out of common.h by Simon Glass · 5 years ago
  67. 9edefc2 common: Move some cache and MMU functions out of common.h by Simon Glass · 5 years ago
  68. 61ce84b riscv: cache: use CCTL to flush d-cache by Rick Chen · 5 years ago
  69. 7045ed9 riscv: cache: Flush L2 cache before jump to linux by Rick Chen · 5 years ago
  70. a8323d1 riscv: ax25: add imply v5l2 cache controller by Rick Chen · 5 years ago
  71. f6cb427 riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
  72. c7e1eff riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
  73. 8c59f20 riscv: add SPL support by Lukas Auer · 5 years ago
  74. fbfd92b riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  75. 4d2583d riscv: Access CSRs using CSR numbers by Bin Meng · 5 years ago
  76. 1001502 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · 6 years ago
  77. f9281b8 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
  78. bdce389 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
  79. dda00ae riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · 6 years ago
  80. 8848474 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · 6 years ago
  81. 8ac39e2 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
  82. e043240 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
  83. 3dea63c riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
  84. 1446b26 riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
  85. 2503ccc riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
  86. 26f4fd1 riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · 6 years ago
  87. fdff1f9 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · 6 years ago
  88. c905665 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · 6 years ago
  89. 51ab457 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
  90. 10753ef riscv: Return to previous privilege level after trap handling by Bin Meng · 6 years ago
  91. 496262c riscv: Fix context restore before returning from trap handler by Bin Meng · 6 years ago
  92. 4b3f5ed riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
  93. 485e822 riscv: Do some basic architecture level cpu initialization by Bin Meng · 6 years ago
  94. aef59e5 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · 6 years ago
  95. 3c276b2 riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · 6 years ago
  96. 39cad5b riscv: Probe cpus during boot by Bin Meng · 6 years ago
  97. 84304d4 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · 6 years ago
  98. 44fe795 riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · 6 years ago
  99. 27dc2c1 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · 6 years ago
  100. 48cbf62 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago