Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 2 | /* |
| 3 | * PCI emulation device which swaps the case of text |
| 4 | * |
| 5 | * Copyright (c) 2014 Google, Inc |
| 6 | * Written by Simon Glass <sjg@chromium.org> |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <dm.h> |
Simon Glass | 3806882 | 2015-05-04 11:31:08 -0600 | [diff] [blame] | 11 | #include <errno.h> |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 12 | #include <pci.h> |
| 13 | #include <asm/test.h> |
| 14 | #include <linux/ctype.h> |
| 15 | |
| 16 | /** |
| 17 | * struct swap_case_platdata - platform data for this device |
| 18 | * |
| 19 | * @command: Current PCI command value |
| 20 | * @bar: Current base address values |
| 21 | */ |
| 22 | struct swap_case_platdata { |
| 23 | u16 command; |
Simon Glass | fe996ec | 2018-06-12 00:05:02 -0600 | [diff] [blame] | 24 | u32 bar[6]; |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | #define offset_to_barnum(offset) \ |
| 28 | (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32)) |
| 29 | |
| 30 | enum { |
| 31 | MEM_TEXT_SIZE = 0x100, |
| 32 | }; |
| 33 | |
| 34 | enum swap_case_op { |
| 35 | OP_TO_LOWER, |
| 36 | OP_TO_UPPER, |
| 37 | OP_SWAP, |
| 38 | }; |
| 39 | |
| 40 | static struct pci_bar { |
| 41 | int type; |
| 42 | u32 size; |
| 43 | } barinfo[] = { |
| 44 | { PCI_BASE_ADDRESS_SPACE_IO, 1 }, |
| 45 | { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE }, |
| 46 | { 0, 0 }, |
| 47 | { 0, 0 }, |
| 48 | { 0, 0 }, |
| 49 | { 0, 0 }, |
| 50 | }; |
| 51 | |
| 52 | struct swap_case_priv { |
| 53 | enum swap_case_op op; |
| 54 | char mem_text[MEM_TEXT_SIZE]; |
| 55 | }; |
| 56 | |
| 57 | static int sandbox_swap_case_get_devfn(struct udevice *dev) |
| 58 | { |
| 59 | struct pci_child_platdata *plat = dev_get_parent_platdata(dev); |
| 60 | |
| 61 | return plat->devfn; |
| 62 | } |
| 63 | |
| 64 | static int sandbox_swap_case_read_config(struct udevice *emul, uint offset, |
| 65 | ulong *valuep, enum pci_size_t size) |
| 66 | { |
| 67 | struct swap_case_platdata *plat = dev_get_platdata(emul); |
| 68 | |
| 69 | switch (offset) { |
| 70 | case PCI_COMMAND: |
| 71 | *valuep = plat->command; |
| 72 | break; |
| 73 | case PCI_HEADER_TYPE: |
| 74 | *valuep = 0; |
| 75 | break; |
| 76 | case PCI_VENDOR_ID: |
| 77 | *valuep = SANDBOX_PCI_VENDOR_ID; |
| 78 | break; |
| 79 | case PCI_DEVICE_ID: |
| 80 | *valuep = SANDBOX_PCI_DEVICE_ID; |
| 81 | break; |
| 82 | case PCI_CLASS_DEVICE: |
| 83 | if (size == PCI_SIZE_8) { |
| 84 | *valuep = SANDBOX_PCI_CLASS_SUB_CODE; |
| 85 | } else { |
| 86 | *valuep = (SANDBOX_PCI_CLASS_CODE << 8) | |
| 87 | SANDBOX_PCI_CLASS_SUB_CODE; |
| 88 | } |
| 89 | break; |
| 90 | case PCI_CLASS_CODE: |
| 91 | *valuep = SANDBOX_PCI_CLASS_CODE; |
| 92 | break; |
| 93 | case PCI_BASE_ADDRESS_0: |
| 94 | case PCI_BASE_ADDRESS_1: |
| 95 | case PCI_BASE_ADDRESS_2: |
| 96 | case PCI_BASE_ADDRESS_3: |
| 97 | case PCI_BASE_ADDRESS_4: |
| 98 | case PCI_BASE_ADDRESS_5: { |
| 99 | int barnum; |
| 100 | u32 *bar, result; |
| 101 | |
| 102 | barnum = offset_to_barnum(offset); |
| 103 | bar = &plat->bar[barnum]; |
| 104 | |
| 105 | result = *bar; |
| 106 | if (*bar == 0xffffffff) { |
| 107 | if (barinfo[barnum].type) { |
| 108 | result = (~(barinfo[barnum].size - 1) & |
| 109 | PCI_BASE_ADDRESS_IO_MASK) | |
| 110 | PCI_BASE_ADDRESS_SPACE_IO; |
| 111 | } else { |
| 112 | result = (~(barinfo[barnum].size - 1) & |
| 113 | PCI_BASE_ADDRESS_MEM_MASK) | |
| 114 | PCI_BASE_ADDRESS_MEM_TYPE_32; |
| 115 | } |
| 116 | } |
| 117 | debug("r bar %d=%x\n", barnum, result); |
| 118 | *valuep = result; |
| 119 | break; |
| 120 | } |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 121 | case PCI_CAPABILITY_LIST: |
| 122 | *valuep = PCI_CAP_ID_PM_OFFSET; |
| 123 | break; |
| 124 | case PCI_CAP_ID_PM_OFFSET: |
| 125 | *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM; |
| 126 | break; |
Bin Meng | 7a20614 | 2018-10-15 02:21:22 -0700 | [diff] [blame] | 127 | case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT: |
| 128 | *valuep = PCI_CAP_ID_EXP_OFFSET; |
| 129 | break; |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 130 | case PCI_CAP_ID_EXP_OFFSET: |
| 131 | *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP; |
| 132 | break; |
Bin Meng | 7a20614 | 2018-10-15 02:21:22 -0700 | [diff] [blame] | 133 | case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT: |
| 134 | *valuep = PCI_CAP_ID_MSIX_OFFSET; |
| 135 | break; |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 136 | case PCI_CAP_ID_MSIX_OFFSET: |
| 137 | *valuep = PCI_CAP_ID_MSIX; |
| 138 | break; |
Bin Meng | 7a20614 | 2018-10-15 02:21:22 -0700 | [diff] [blame] | 139 | case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT: |
| 140 | *valuep = 0; |
| 141 | break; |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 142 | case PCI_EXT_CAP_ID_ERR_OFFSET: |
| 143 | *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR; |
| 144 | break; |
| 145 | case PCI_EXT_CAP_ID_VC_OFFSET: |
| 146 | *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC; |
| 147 | break; |
| 148 | case PCI_EXT_CAP_ID_DSN_OFFSET: |
| 149 | *valuep = PCI_EXT_CAP_ID_DSN; |
| 150 | break; |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | static int sandbox_swap_case_write_config(struct udevice *emul, uint offset, |
| 157 | ulong value, enum pci_size_t size) |
| 158 | { |
| 159 | struct swap_case_platdata *plat = dev_get_platdata(emul); |
| 160 | |
| 161 | switch (offset) { |
| 162 | case PCI_COMMAND: |
| 163 | plat->command = value; |
| 164 | break; |
| 165 | case PCI_BASE_ADDRESS_0: |
| 166 | case PCI_BASE_ADDRESS_1: { |
| 167 | int barnum; |
| 168 | u32 *bar; |
| 169 | |
| 170 | barnum = offset_to_barnum(offset); |
| 171 | bar = &plat->bar[barnum]; |
| 172 | |
| 173 | debug("w bar %d=%lx\n", barnum, value); |
| 174 | *bar = value; |
Bin Meng | 76330ae | 2018-08-03 01:14:40 -0700 | [diff] [blame] | 175 | /* space indicator (bit#0) is read-only */ |
| 176 | *bar |= barinfo[barnum].type; |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 177 | break; |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr, |
| 185 | int *barnump, unsigned int *offsetp) |
| 186 | { |
| 187 | struct swap_case_platdata *plat = dev_get_platdata(emul); |
| 188 | int barnum; |
| 189 | |
| 190 | for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { |
| 191 | unsigned int size = barinfo[barnum].size; |
Bin Meng | 76330ae | 2018-08-03 01:14:40 -0700 | [diff] [blame] | 192 | u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 193 | |
Bin Meng | 76330ae | 2018-08-03 01:14:40 -0700 | [diff] [blame] | 194 | if (addr >= base && addr < base + size) { |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 195 | *barnump = barnum; |
Bin Meng | 76330ae | 2018-08-03 01:14:40 -0700 | [diff] [blame] | 196 | *offsetp = addr - base; |
Simon Glass | d2cb9b2 | 2015-03-05 12:25:29 -0700 | [diff] [blame] | 197 | return 0; |
| 198 | } |
| 199 | } |
| 200 | *barnump = -1; |
| 201 | |
| 202 | return -ENOENT; |
| 203 | } |
| 204 | |
| 205 | static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len) |
| 206 | { |
| 207 | for (; len > 0; len--, str++) { |
| 208 | switch (op) { |
| 209 | case OP_TO_UPPER: |
| 210 | *str = toupper(*str); |
| 211 | break; |
| 212 | case OP_TO_LOWER: |
| 213 | *str = tolower(*str); |
| 214 | break; |
| 215 | case OP_SWAP: |
| 216 | if (isupper(*str)) |
| 217 | *str = tolower(*str); |
| 218 | else |
| 219 | *str = toupper(*str); |
| 220 | break; |
| 221 | } |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr, |
| 226 | ulong *valuep, enum pci_size_t size) |
| 227 | { |
| 228 | struct swap_case_priv *priv = dev_get_priv(dev); |
| 229 | unsigned int offset; |
| 230 | int barnum; |
| 231 | int ret; |
| 232 | |
| 233 | ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset); |
| 234 | if (ret) |
| 235 | return ret; |
| 236 | |
| 237 | if (barnum == 0 && offset == 0) |
| 238 | *valuep = (*valuep & ~0xff) | priv->op; |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr, |
| 244 | ulong value, enum pci_size_t size) |
| 245 | { |
| 246 | struct swap_case_priv *priv = dev_get_priv(dev); |
| 247 | unsigned int offset; |
| 248 | int barnum; |
| 249 | int ret; |
| 250 | |
| 251 | ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset); |
| 252 | if (ret) |
| 253 | return ret; |
| 254 | if (barnum == 0 && offset == 0) |
| 255 | priv->op = value; |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | static int sandbox_swap_case_map_physmem(struct udevice *dev, |
| 261 | phys_addr_t addr, unsigned long *lenp, void **ptrp) |
| 262 | { |
| 263 | struct swap_case_priv *priv = dev_get_priv(dev); |
| 264 | unsigned int offset, avail; |
| 265 | int barnum; |
| 266 | int ret; |
| 267 | |
| 268 | ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset); |
| 269 | if (ret) |
| 270 | return ret; |
| 271 | if (barnum == 1) { |
| 272 | *ptrp = priv->mem_text + offset; |
| 273 | avail = barinfo[1].size - offset; |
| 274 | if (avail > barinfo[1].size) |
| 275 | *lenp = 0; |
| 276 | else |
| 277 | *lenp = min(*lenp, (ulong)avail); |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | return -ENOENT; |
| 283 | } |
| 284 | |
| 285 | static int sandbox_swap_case_unmap_physmem(struct udevice *dev, |
| 286 | const void *vaddr, unsigned long len) |
| 287 | { |
| 288 | struct swap_case_priv *priv = dev_get_priv(dev); |
| 289 | |
| 290 | sandbox_swap_case_do_op(priv->op, (void *)vaddr, len); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | struct dm_pci_emul_ops sandbox_swap_case_emul_ops = { |
| 296 | .get_devfn = sandbox_swap_case_get_devfn, |
| 297 | .read_config = sandbox_swap_case_read_config, |
| 298 | .write_config = sandbox_swap_case_write_config, |
| 299 | .read_io = sandbox_swap_case_read_io, |
| 300 | .write_io = sandbox_swap_case_write_io, |
| 301 | .map_physmem = sandbox_swap_case_map_physmem, |
| 302 | .unmap_physmem = sandbox_swap_case_unmap_physmem, |
| 303 | }; |
| 304 | |
| 305 | static const struct udevice_id sandbox_swap_case_ids[] = { |
| 306 | { .compatible = "sandbox,swap-case" }, |
| 307 | { } |
| 308 | }; |
| 309 | |
| 310 | U_BOOT_DRIVER(sandbox_swap_case_emul) = { |
| 311 | .name = "sandbox_swap_case_emul", |
| 312 | .id = UCLASS_PCI_EMUL, |
| 313 | .of_match = sandbox_swap_case_ids, |
| 314 | .ops = &sandbox_swap_case_emul_ops, |
| 315 | .priv_auto_alloc_size = sizeof(struct swap_case_priv), |
| 316 | .platdata_auto_alloc_size = sizeof(struct swap_case_platdata), |
| 317 | }; |
Bin Meng | 59a160e | 2018-08-03 01:14:46 -0700 | [diff] [blame] | 318 | |
| 319 | static struct pci_device_id sandbox_swap_case_supported[] = { |
| 320 | { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_DEVICE_ID), SWAP_CASE_DRV_DATA }, |
| 321 | {}, |
| 322 | }; |
| 323 | |
| 324 | U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported); |