blob: 790bb0c4bdcb69536af31e20ea7408eebf05f561 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassd2cb9b22015-03-05 12:25:29 -07002/*
3 * PCI emulation device which swaps the case of text
4 *
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
Simon Glassd2cb9b22015-03-05 12:25:29 -07007 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass38068822015-05-04 11:31:08 -060011#include <errno.h>
Simon Glassd2cb9b22015-03-05 12:25:29 -070012#include <pci.h>
13#include <asm/test.h>
14#include <linux/ctype.h>
15
16/**
17 * struct swap_case_platdata - platform data for this device
18 *
19 * @command: Current PCI command value
20 * @bar: Current base address values
21 */
22struct swap_case_platdata {
23 u16 command;
Simon Glassfe996ec2018-06-12 00:05:02 -060024 u32 bar[6];
Simon Glassd2cb9b22015-03-05 12:25:29 -070025};
26
27#define offset_to_barnum(offset) \
28 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
29
30enum {
31 MEM_TEXT_SIZE = 0x100,
32};
33
34enum swap_case_op {
35 OP_TO_LOWER,
36 OP_TO_UPPER,
37 OP_SWAP,
38};
39
40static struct pci_bar {
41 int type;
42 u32 size;
43} barinfo[] = {
44 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
45 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
46 { 0, 0 },
47 { 0, 0 },
48 { 0, 0 },
49 { 0, 0 },
50};
51
52struct swap_case_priv {
53 enum swap_case_op op;
54 char mem_text[MEM_TEXT_SIZE];
55};
56
57static int sandbox_swap_case_get_devfn(struct udevice *dev)
58{
59 struct pci_child_platdata *plat = dev_get_parent_platdata(dev);
60
61 return plat->devfn;
62}
63
64static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
65 ulong *valuep, enum pci_size_t size)
66{
67 struct swap_case_platdata *plat = dev_get_platdata(emul);
68
69 switch (offset) {
70 case PCI_COMMAND:
71 *valuep = plat->command;
72 break;
73 case PCI_HEADER_TYPE:
74 *valuep = 0;
75 break;
76 case PCI_VENDOR_ID:
77 *valuep = SANDBOX_PCI_VENDOR_ID;
78 break;
79 case PCI_DEVICE_ID:
80 *valuep = SANDBOX_PCI_DEVICE_ID;
81 break;
82 case PCI_CLASS_DEVICE:
83 if (size == PCI_SIZE_8) {
84 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
85 } else {
86 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
87 SANDBOX_PCI_CLASS_SUB_CODE;
88 }
89 break;
90 case PCI_CLASS_CODE:
91 *valuep = SANDBOX_PCI_CLASS_CODE;
92 break;
93 case PCI_BASE_ADDRESS_0:
94 case PCI_BASE_ADDRESS_1:
95 case PCI_BASE_ADDRESS_2:
96 case PCI_BASE_ADDRESS_3:
97 case PCI_BASE_ADDRESS_4:
98 case PCI_BASE_ADDRESS_5: {
99 int barnum;
100 u32 *bar, result;
101
102 barnum = offset_to_barnum(offset);
103 bar = &plat->bar[barnum];
104
105 result = *bar;
106 if (*bar == 0xffffffff) {
107 if (barinfo[barnum].type) {
108 result = (~(barinfo[barnum].size - 1) &
109 PCI_BASE_ADDRESS_IO_MASK) |
110 PCI_BASE_ADDRESS_SPACE_IO;
111 } else {
112 result = (~(barinfo[barnum].size - 1) &
113 PCI_BASE_ADDRESS_MEM_MASK) |
114 PCI_BASE_ADDRESS_MEM_TYPE_32;
115 }
116 }
117 debug("r bar %d=%x\n", barnum, result);
118 *valuep = result;
119 break;
120 }
121 }
122
123 return 0;
124}
125
126static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
127 ulong value, enum pci_size_t size)
128{
129 struct swap_case_platdata *plat = dev_get_platdata(emul);
130
131 switch (offset) {
132 case PCI_COMMAND:
133 plat->command = value;
134 break;
135 case PCI_BASE_ADDRESS_0:
136 case PCI_BASE_ADDRESS_1: {
137 int barnum;
138 u32 *bar;
139
140 barnum = offset_to_barnum(offset);
141 bar = &plat->bar[barnum];
142
143 debug("w bar %d=%lx\n", barnum, value);
144 *bar = value;
Bin Meng76330ae2018-08-03 01:14:40 -0700145 /* space indicator (bit#0) is read-only */
146 *bar |= barinfo[barnum].type;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700147 break;
148 }
149 }
150
151 return 0;
152}
153
154static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
155 int *barnump, unsigned int *offsetp)
156{
157 struct swap_case_platdata *plat = dev_get_platdata(emul);
158 int barnum;
159
160 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
161 unsigned int size = barinfo[barnum].size;
Bin Meng76330ae2018-08-03 01:14:40 -0700162 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700163
Bin Meng76330ae2018-08-03 01:14:40 -0700164 if (addr >= base && addr < base + size) {
Simon Glassd2cb9b22015-03-05 12:25:29 -0700165 *barnump = barnum;
Bin Meng76330ae2018-08-03 01:14:40 -0700166 *offsetp = addr - base;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700167 return 0;
168 }
169 }
170 *barnump = -1;
171
172 return -ENOENT;
173}
174
175static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
176{
177 for (; len > 0; len--, str++) {
178 switch (op) {
179 case OP_TO_UPPER:
180 *str = toupper(*str);
181 break;
182 case OP_TO_LOWER:
183 *str = tolower(*str);
184 break;
185 case OP_SWAP:
186 if (isupper(*str))
187 *str = tolower(*str);
188 else
189 *str = toupper(*str);
190 break;
191 }
192 }
193}
194
195int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
196 ulong *valuep, enum pci_size_t size)
197{
198 struct swap_case_priv *priv = dev_get_priv(dev);
199 unsigned int offset;
200 int barnum;
201 int ret;
202
203 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
204 if (ret)
205 return ret;
206
207 if (barnum == 0 && offset == 0)
208 *valuep = (*valuep & ~0xff) | priv->op;
209
210 return 0;
211}
212
213int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
214 ulong value, enum pci_size_t size)
215{
216 struct swap_case_priv *priv = dev_get_priv(dev);
217 unsigned int offset;
218 int barnum;
219 int ret;
220
221 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
222 if (ret)
223 return ret;
224 if (barnum == 0 && offset == 0)
225 priv->op = value;
226
227 return 0;
228}
229
230static int sandbox_swap_case_map_physmem(struct udevice *dev,
231 phys_addr_t addr, unsigned long *lenp, void **ptrp)
232{
233 struct swap_case_priv *priv = dev_get_priv(dev);
234 unsigned int offset, avail;
235 int barnum;
236 int ret;
237
238 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
239 if (ret)
240 return ret;
241 if (barnum == 1) {
242 *ptrp = priv->mem_text + offset;
243 avail = barinfo[1].size - offset;
244 if (avail > barinfo[1].size)
245 *lenp = 0;
246 else
247 *lenp = min(*lenp, (ulong)avail);
248
249 return 0;
250 }
251
252 return -ENOENT;
253}
254
255static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
256 const void *vaddr, unsigned long len)
257{
258 struct swap_case_priv *priv = dev_get_priv(dev);
259
260 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
261
262 return 0;
263}
264
265struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
266 .get_devfn = sandbox_swap_case_get_devfn,
267 .read_config = sandbox_swap_case_read_config,
268 .write_config = sandbox_swap_case_write_config,
269 .read_io = sandbox_swap_case_read_io,
270 .write_io = sandbox_swap_case_write_io,
271 .map_physmem = sandbox_swap_case_map_physmem,
272 .unmap_physmem = sandbox_swap_case_unmap_physmem,
273};
274
275static const struct udevice_id sandbox_swap_case_ids[] = {
276 { .compatible = "sandbox,swap-case" },
277 { }
278};
279
280U_BOOT_DRIVER(sandbox_swap_case_emul) = {
281 .name = "sandbox_swap_case_emul",
282 .id = UCLASS_PCI_EMUL,
283 .of_match = sandbox_swap_case_ids,
284 .ops = &sandbox_swap_case_emul_ops,
285 .priv_auto_alloc_size = sizeof(struct swap_case_priv),
286 .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
287};
Bin Meng59a160e2018-08-03 01:14:46 -0700288
289static struct pci_device_id sandbox_swap_case_supported[] = {
290 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_DEVICE_ID), SWAP_CASE_DRV_DATA },
291 {},
292};
293
294U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);