blob: 77f66c65c03ecbbce3c55b2df38b50b5351027b6 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunaybc061342018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Patrick Delaunay27a986d2019-04-18 17:32:47 +020020 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
21 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010022 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010023 imply SPL_LIBDISK_SUPPORT
24
25config SYS_SOC
26 default "stm32mp"
27
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020028config SYS_MALLOC_LEN
29 default 0x2000000
30
Patrick Delaunay579a3e72019-04-18 17:32:37 +020031config ENV_SIZE
32 default 0x1000
33
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010034config TARGET_STM32MP1
35 bool "Support stm32mp1xx"
Patrick Delaunayabf26782019-02-12 11:44:39 +010036 select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
Lokesh Vutlaacf15002018-04-26 18:21:26 +053037 select CPU_V7A
Patrick Delaunayabf26782019-02-12 11:44:39 +010038 select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
Patrick Delaunay41c79772018-04-16 10:13:24 +020039 select CPU_V7_HAS_VIRT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010040 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020041 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010042 select STM32_RESET
Andre Przywara7842b6a2018-04-12 04:24:46 +030043 select SYS_ARCH_TIMER
Patrick Delaunay34199822019-04-18 17:32:45 +020044 imply BOOTCOUNT_LIMIT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020045 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020046 imply CMD_BOOTCOUNT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020047 imply CMD_BOOTSTAGE
Patrick Delaunayabf26782019-02-12 11:44:39 +010048 imply SYSRESET_PSCI if STM32MP1_TRUSTED
49 imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010050 help
51 target STMicroelectronics SOC STM32MP1 family
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010052 STM32MP157, STM32MP153 or STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010053 STMicroelectronics MPU with core ARMv7
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010054 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010055
Patrick Delaunayabf26782019-02-12 11:44:39 +010056config STM32MP1_TRUSTED
57 bool "Support trusted boot with TF-A"
58 default y if !SPL
59 select ARM_SMCCC
60 help
61 Say Y here to enable boot with TF-A
62 Trusted boot chain is :
63 BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
64 TF-A monitor provides proprietary smc to manage secure devices
65
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010066config SYS_TEXT_BASE
67 prompt "U-Boot base address"
68 default 0xC0100000
69 help
70 configure the U-Boot base address
71 when DDR driver is used:
72 DDR + 1MB (0xC0100000)
73
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010074config NR_DRAM_BANKS
75 default 1
76
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +010077config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
78 hex "Partition on MMC2 to use to load U-Boot from"
79 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
80 default 1
81 help
82 Partition on the second MMC to load U-Boot from when the MMC is being
83 used in raw mode
84
Patrick Delaunay27a986d2019-04-18 17:32:47 +020085config BOOTSTAGE_STASH_ADDR
86 default 0xC3000000
87
Patrick Delaunay34199822019-04-18 17:32:45 +020088if BOOTCOUNT_LIMIT
89config SYS_BOOTCOUNT_SINGLEWORD
90 default y
91
92# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
93config SYS_BOOTCOUNT_ADDR
94 default 0x5C00A154
95endif
96
Patrick Delaunay320d2662018-05-17 14:50:46 +020097if DEBUG_UART
98
99config DEBUG_UART_BOARD_INIT
100 default y
101
102# debug on UART4 by default
103config DEBUG_UART_BASE
104 default 0x40010000
105
106# clock source is HSI on reset
107config DEBUG_UART_CLOCK
108 default 64000000
109endif
110
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100111source "board/st/stm32mp1/Kconfig"
112
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100113endif