blob: 49afa7cf84e7019b771bdf5049a10c9170eb888b [file] [log] [blame]
Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * CREDITS: Kim Phillips contribute to LIBFDT code
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <common.h>
14#include <i2c.h>
Dave Liu6f8c85e2008-03-26 22:56:36 +080015#include <asm/io.h>
16#include <asm/fsl_serdes.h>
Dave Liu19580e62007-09-18 12:37:57 +080017#include <spd_sdram.h>
Anton Vorontsov1da83a62008-10-02 18:32:25 +040018#include <tsec.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060019#if defined(CONFIG_OF_LIBFDT)
Dave Liu19580e62007-09-18 12:37:57 +080020#include <libfdt.h>
21#endif
22#if defined(CONFIG_PQ_MDS_PIB)
23#include "../common/pq-mds-pib.h"
24#endif
25
26int board_early_init_f(void)
27{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
Dave Liu19580e62007-09-18 12:37:57 +080029
30 /* Enable flash write */
31 bcsr[0x9] &= ~0x04;
32 /* Clear all of the interrupt of BCSR */
33 bcsr[0xe] = 0xff;
34
Dave Liu6f8c85e2008-03-26 22:56:36 +080035#ifdef CONFIG_FSL_SERDES
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
Dave Liu6f8c85e2008-03-26 22:56:36 +080037 u32 spridr = in_be32(&immr->sysconf.spridr);
38
39 /* we check only part num, and don't look for CPU revisions */
Dave Liu5fb5a682008-03-31 17:05:12 +080040 switch (PARTID_NO_E(spridr)) {
Kim Phillipse5c4ade2008-03-28 10:19:07 -050041 case SPR_8377:
Dave Liu6f8c85e2008-03-26 22:56:36 +080042 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
43 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
44 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
45 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
46 break;
Kim Phillipse5c4ade2008-03-28 10:19:07 -050047 case SPR_8378:
Anton Vorontsov1da83a62008-10-02 18:32:25 +040048 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
49 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
Anton Vorontsov55c53192008-10-02 18:31:53 +040050 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
Kim Phillipse5c4ade2008-03-28 10:19:07 -050051 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
52 break;
53 case SPR_8379:
54 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
55 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
56 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
57 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
58 break;
Dave Liu6f8c85e2008-03-26 22:56:36 +080059 default:
60 printf("serdes not configured: unknown CPU part number: "
61 "%04x\n", spridr >> 16);
62 break;
63 }
64#endif /* CONFIG_FSL_SERDES */
Dave Liu19580e62007-09-18 12:37:57 +080065 return 0;
66}
67
Anton Vorontsov1da83a62008-10-02 18:32:25 +040068#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
69int board_eth_init(bd_t *bd)
70{
71 struct tsec_info_struct tsec_info[2];
72 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
73 u32 rcwh = in_be32(&im->reset.rcwh);
74 u32 tsec_mode;
75 int num = 0;
76
77 /* New line after Net: */
78 printf("\n");
79
80#ifdef CONFIG_TSEC1
81 SET_STD_TSEC_INFO(tsec_info[num], 1);
82
83 printf(CONFIG_TSEC1_NAME ": ");
84
85 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
86 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
87 printf("RGMII\n");
88 /* this is default, no need to fixup */
89 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
90 printf("SGMII\n");
91 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
92 tsec_info[num].flags = TSEC_GIGABIT;
93 } else {
94 printf("unsupported PHY type\n");
95 }
96 num++;
97#endif
98#ifdef CONFIG_TSEC2
99 SET_STD_TSEC_INFO(tsec_info[num], 2);
100
101 printf(CONFIG_TSEC2_NAME ": ");
102
103 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
104 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
105 printf("RGMII\n");
106 /* this is default, no need to fixup */
107 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
108 printf("SGMII\n");
109 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
110 tsec_info[num].flags = TSEC_GIGABIT;
111 } else {
112 printf("unsupported PHY type\n");
113 }
114 num++;
115#endif
116 return tsec_eth_init(bd, tsec_info, num);
117}
118
119static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
120 int phy_addr)
121{
122 const char *phy_type = "sgmii";
123 const u32 *ph;
124 int off;
125 int err;
126
127 off = fdt_path_offset(blob, alias);
128 if (off < 0) {
129 printf("WARNING: could not find %s alias: %s.\n", alias,
130 fdt_strerror(off));
131 return;
132 }
133
134 err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
135 strlen(phy_type) + 1);
136 if (err) {
137 printf("WARNING: could not set phy-connection-type for %s: "
138 "%s.\n", alias, fdt_strerror(err));
139 return;
140 }
141
142 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
143 if (!ph) {
144 printf("WARNING: could not get phy-handle for %s.\n",
145 alias);
146 return;
147 }
148
149 off = fdt_node_offset_by_phandle(blob, *ph);
150 if (off < 0) {
151 printf("WARNING: could not get phy node for %s: %s\n", alias,
152 fdt_strerror(off));
153 return;
154 }
155
156 phy_addr = cpu_to_fdt32(phy_addr);
157 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
158 if (err < 0) {
159 printf("WARNING: could not set phy node's reg for %s: "
160 "%s.\n", alias, fdt_strerror(err));
161 return;
162 }
163}
164
165static void ft_tsec_fixup(void *blob, bd_t *bd)
166{
167 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
168 u32 rcwh = in_be32(&im->reset.rcwh);
169 u32 tsec_mode;
170
171#ifdef CONFIG_TSEC1
172 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
173 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
174 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
175#endif
176
177#ifdef CONFIG_TSEC2
178 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
179 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
180 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
181#endif
182}
183#else
184static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
185#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
186
Dave Liu19580e62007-09-18 12:37:57 +0800187int board_early_init_r(void)
188{
189#ifdef CONFIG_PQ_MDS_PIB
190 pib_init();
191#endif
192 return 0;
193}
194
195#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
196extern void ddr_enable_ecc(unsigned int dram_size);
197#endif
198int fixed_sdram(void);
199
Becky Bruce9973e3c2008-06-09 16:03:40 -0500200phys_size_t initdram(int board_type)
Dave Liu19580e62007-09-18 12:37:57 +0800201{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Dave Liu19580e62007-09-18 12:37:57 +0800203 u32 msize = 0;
204
205 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
206 return -1;
207
208#if defined(CONFIG_SPD_EEPROM)
209 msize = spd_sdram();
210#else
211 msize = fixed_sdram();
212#endif
213
214#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
215 /* Initialize DDR ECC byte */
216 ddr_enable_ecc(msize * 1024 * 1024);
217#endif
218
219 /* return total bus DDR size(bytes) */
220 return (msize * 1024 * 1024);
221}
222
223#if !defined(CONFIG_SPD_EEPROM)
224/*************************************************************************
225 * fixed sdram init -- doesn't use serial presence detect.
226 ************************************************************************/
227int fixed_sdram(void)
228{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
230 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Dave Liu19580e62007-09-18 12:37:57 +0800231 u32 msize_log2 = __ilog2(msize);
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Dave Liu19580e62007-09-18 12:37:57 +0800234 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#if (CONFIG_SYS_DDR_SIZE != 512)
Dave Liu19580e62007-09-18 12:37:57 +0800237#warning Currenly any ddr size other than 512 is not supported
238#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Dave Liu19580e62007-09-18 12:37:57 +0800240 udelay(50000);
241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
Dave Liu19580e62007-09-18 12:37:57 +0800243 udelay(1000);
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
246 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
Dave Liu19580e62007-09-18 12:37:57 +0800247 udelay(1000);
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
250 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
251 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
252 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
253 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
254 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
255 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
256 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
257 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Dave Liu19580e62007-09-18 12:37:57 +0800258 __asm__ __volatile__("sync");
259 udelay(1000);
260
261 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
262 udelay(2000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 return CONFIG_SYS_DDR_SIZE;
Dave Liu19580e62007-09-18 12:37:57 +0800264}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#endif /*!CONFIG_SYS_SPD_EEPROM */
Dave Liu19580e62007-09-18 12:37:57 +0800266
267int checkboard(void)
268{
269 puts("Board: Freescale MPC837xEMDS\n");
270 return 0;
271}
272
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400273#ifdef CONFIG_PCI
274int board_pci_host_broken(void)
275{
276 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
277 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
278 const char *pci_ea = getenv("pci_external_arbiter");
279
280 /* It's always OK in case of external arbiter. */
281 if (pci_ea && !strcmp(pci_ea, "yes"))
282 return 0;
283
284 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
285 return 1;
286
287 return 0;
288}
289
290static void ft_pci_fixup(void *blob, bd_t *bd)
291{
292 const char *status = "broken (no arbiter)";
293 int off;
294 int err;
295
296 off = fdt_path_offset(blob, "pci0");
297 if (off < 0) {
298 printf("WARNING: could not find pci0 alias: %s.\n",
299 fdt_strerror(off));
300 return;
301 }
302
303 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
304 if (err) {
305 printf("WARNING: could not set status for pci0: %s.\n",
306 fdt_strerror(err));
307 return;
308 }
309}
310#endif
311
Dave Liu19580e62007-09-18 12:37:57 +0800312#if defined(CONFIG_OF_BOARD_SETUP)
313void ft_board_setup(void *blob, bd_t *bd)
314{
Dave Liu19580e62007-09-18 12:37:57 +0800315 ft_cpu_setup(blob, bd);
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400316 ft_tsec_fixup(blob, bd);
Dave Liu19580e62007-09-18 12:37:57 +0800317#ifdef CONFIG_PCI
318 ft_pci_setup(blob, bd);
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400319 if (board_pci_host_broken())
320 ft_pci_fixup(blob, bd);
Dave Liu19580e62007-09-18 12:37:57 +0800321#endif
322}
323#endif /* CONFIG_OF_BOARD_SETUP */