York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 1 | config SYS_FSL_DDR |
| 2 | bool |
| 3 | help |
| 4 | Select Freescale General DDR driver, shared between most Freescale |
Tom Rini | 1c58857 | 2021-05-14 21:34:26 -0400 | [diff] [blame] | 5 | PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based |
| 6 | Layerscape SoCs (such as ls2080a). |
York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 7 | |
| 8 | config SYS_FSL_MMDC |
| 9 | bool |
| 10 | help |
| 11 | Select Freescale Multi Mode DDR controller (MMDC). |
| 12 | |
| 13 | config SYS_FSL_DDR_BE |
| 14 | bool |
| 15 | help |
| 16 | Access DDR registers in big-endian |
| 17 | |
| 18 | config SYS_FSL_DDR_LE |
| 19 | bool |
| 20 | help |
| 21 | Access DDR registers in little-endian |
| 22 | |
Rajesh Bhagat | 3241312 | 2019-02-01 05:22:01 +0000 | [diff] [blame] | 23 | config FSL_DDR_BIST |
| 24 | bool |
| 25 | |
| 26 | config FSL_DDR_INTERACTIVE |
| 27 | bool |
| 28 | |
| 29 | config FSL_DDR_SYNC_REFRESH |
| 30 | bool |
| 31 | |
| 32 | config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE |
| 33 | bool |
| 34 | |
York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 35 | menu "Freescale DDR controllers" |
| 36 | depends on SYS_FSL_DDR |
| 37 | |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 38 | config SYS_NUM_DDR_CTLRS |
York Sun | 66e399b | 2016-12-28 08:43:44 -0800 | [diff] [blame] | 39 | int "Maximum DDR controllers" |
| 40 | default 3 if ARCH_LS2080A || \ |
| 41 | ARCH_T4240 |
| 42 | default 2 if ARCH_B4860 || \ |
| 43 | ARCH_BSC9132 || \ |
York Sun | 66e399b | 2016-12-28 08:43:44 -0800 | [diff] [blame] | 44 | ARCH_P4080 || \ |
York Sun | 66e399b | 2016-12-28 08:43:44 -0800 | [diff] [blame] | 45 | ARCH_P5040 || \ |
Priyanka Jain | 4909b89 | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 46 | ARCH_LX2160A || \ |
Tom Rini | ec6b37c | 2021-05-23 10:58:05 -0400 | [diff] [blame] | 47 | ARCH_LX2162A |
York Sun | 66e399b | 2016-12-28 08:43:44 -0800 | [diff] [blame] | 48 | default 1 |
| 49 | |
York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 50 | config SYS_FSL_DDR_VER |
| 51 | int |
| 52 | default 50 if SYS_FSL_DDR_VER_50 |
| 53 | default 47 if SYS_FSL_DDR_VER_47 |
| 54 | default 46 if SYS_FSL_DDR_VER_46 |
| 55 | default 44 if SYS_FSL_DDR_VER_44 |
| 56 | |
| 57 | config SYS_FSL_DDR_VER_50 |
| 58 | bool |
| 59 | |
| 60 | config SYS_FSL_DDR_VER_47 |
| 61 | bool |
| 62 | |
| 63 | config SYS_FSL_DDR_VER_46 |
| 64 | bool |
| 65 | |
| 66 | config SYS_FSL_DDR_VER_44 |
| 67 | bool |
| 68 | |
| 69 | config SYS_FSL_DDRC_GEN1 |
| 70 | bool |
| 71 | help |
| 72 | Enable Freescale DDR controller. |
| 73 | |
| 74 | config SYS_FSL_DDRC_GEN2 |
| 75 | bool |
| 76 | depends on !MPC86xx |
| 77 | help |
| 78 | Enable Freescale DDR2 controller. |
| 79 | |
York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 80 | config SYS_FSL_DDRC_GEN3 |
| 81 | bool |
| 82 | depends on PPC |
| 83 | help |
| 84 | Enable Freescale DDR3 controller for PowerPC SoCs. |
| 85 | |
| 86 | config SYS_FSL_DDRC_ARM_GEN3 |
| 87 | bool |
| 88 | depends on ARM |
| 89 | help |
| 90 | Enable Freescale DDR3 controller for ARM SoCs. |
| 91 | |
| 92 | config SYS_FSL_DDRC_GEN4 |
| 93 | bool |
| 94 | help |
| 95 | Enable Freescale DDR4 controller. |
| 96 | |
| 97 | config SYS_FSL_HAS_DDR4 |
| 98 | bool |
| 99 | |
| 100 | config SYS_FSL_HAS_DDR3 |
| 101 | bool |
| 102 | |
| 103 | config SYS_FSL_HAS_DDR2 |
| 104 | bool |
| 105 | |
| 106 | config SYS_FSL_HAS_DDR1 |
| 107 | bool |
| 108 | |
| 109 | choice |
| 110 | prompt "DDR technology" |
| 111 | default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 |
| 112 | default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 |
| 113 | default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 |
| 114 | default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 |
| 115 | |
| 116 | config SYS_FSL_DDR4 |
| 117 | bool "Freescale DDR4 controller" |
| 118 | depends on SYS_FSL_HAS_DDR4 |
| 119 | select SYS_FSL_DDRC_GEN4 |
| 120 | |
| 121 | config SYS_FSL_DDR3 |
| 122 | bool "Freescale DDR3 controller" |
| 123 | depends on SYS_FSL_HAS_DDR3 |
| 124 | select SYS_FSL_DDRC_GEN3 if PPC |
| 125 | select SYS_FSL_DDRC_ARM_GEN3 if ARM |
| 126 | |
| 127 | config SYS_FSL_DDR2 |
| 128 | bool "Freescale DDR2 controller" |
| 129 | depends on SYS_FSL_HAS_DDR2 |
| 130 | select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) |
York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 131 | |
| 132 | config SYS_FSL_DDR1 |
| 133 | bool "Freescale DDR1 controller" |
| 134 | depends on SYS_FSL_HAS_DDR1 |
| 135 | select SYS_FSL_DDRC_GEN1 |
| 136 | |
| 137 | endchoice |
| 138 | |
| 139 | endmenu |
York Sun | ba1b6fb | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 140 | |
| 141 | config SYS_FSL_ERRATUM_A008378 |
| 142 | bool |
| 143 | |
Joakim Tjernlund | 73af094 | 2019-11-20 17:07:34 +0100 | [diff] [blame] | 144 | config SYS_FSL_ERRATUM_A008109 |
| 145 | bool |
| 146 | |
York Sun | ba1b6fb | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 147 | config SYS_FSL_ERRATUM_A008511 |
| 148 | bool |
| 149 | |
| 150 | config SYS_FSL_ERRATUM_A009663 |
| 151 | bool |
| 152 | |
| 153 | config SYS_FSL_ERRATUM_A009801 |
| 154 | bool |
| 155 | |
| 156 | config SYS_FSL_ERRATUM_A009803 |
| 157 | bool |
| 158 | |
| 159 | config SYS_FSL_ERRATUM_A009942 |
| 160 | bool |
| 161 | |
| 162 | config SYS_FSL_ERRATUM_A010165 |
| 163 | bool |
York Sun | 63659ff | 2016-12-28 08:43:43 -0800 | [diff] [blame] | 164 | |
| 165 | config SYS_FSL_ERRATUM_NMG_DDR120 |
| 166 | bool |
| 167 | |
| 168 | config SYS_FSL_ERRATUM_DDR_115 |
| 169 | bool |
| 170 | |
| 171 | config SYS_FSL_ERRATUM_DDR111_DDR134 |
| 172 | bool |
| 173 | |
| 174 | config SYS_FSL_ERRATUM_DDR_A003 |
| 175 | bool |
| 176 | |
| 177 | config SYS_FSL_ERRATUM_DDR_A003474 |
| 178 | bool |