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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Amit Singh Tomara29710c2016-07-06 17:59:44 +05302/*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
Amit Singh Tomara29710c2016-07-06 17:59:44 +05306 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11*/
12
Simon Glass1eb69ae2019-11-14 12:57:39 -070013#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Simon Glass90526e92020-05-10 11:39:56 -060015#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060016#include <asm/global_data.h>
Amit Singh Tomara29710c2016-07-06 17:59:44 +053017#include <asm/io.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/gpio.h>
20#include <common.h>
Jagan Tekid3a2c052019-02-28 00:26:58 +053021#include <clk.h>
Amit Singh Tomara29710c2016-07-06 17:59:44 +053022#include <dm.h>
23#include <fdt_support.h>
Simon Glass336d4612020-02-03 07:36:16 -070024#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060025#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060026#include <linux/delay.h>
Amit Singh Tomara29710c2016-07-06 17:59:44 +053027#include <linux/err.h>
28#include <malloc.h>
29#include <miiphy.h>
30#include <net.h>
Jagan Tekid3a2c052019-02-28 00:26:58 +053031#include <reset.h>
Andre Przywarac0341172018-04-04 01:31:15 +010032#include <dt-bindings/pinctrl/sun4i-a10.h>
Andre Przywaraf20f9462020-07-06 01:40:34 +010033#include <wait_bit.h>
Simon Glassbcee8d62019-12-06 21:41:35 -070034#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich4d555ae2017-02-22 19:46:41 +010035#include <asm-generic/gpio.h>
36#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +053037
Amit Singh Tomara29710c2016-07-06 17:59:44 +053038#define MDIO_CMD_MII_BUSY BIT(0)
39#define MDIO_CMD_MII_WRITE BIT(1)
40
41#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
42#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
43#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
44#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
Andre Przywara4f0278d2020-07-06 01:40:45 +010045#define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
46#define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
47#define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
48#define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
49#define MDIO_CMD_MII_CLK_CSR_SHIFT 20
Amit Singh Tomara29710c2016-07-06 17:59:44 +053050
51#define CONFIG_TX_DESCR_NUM 32
52#define CONFIG_RX_DESCR_NUM 32
Hans de Goede40694372016-07-27 17:31:17 +020053#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
54
55/*
56 * The datasheet says that each descriptor can transfers up to 4096 bytes
57 * But later, the register documentation reduces that value to 2048,
58 * using 2048 cause strange behaviours and even BSP driver use 2047
59 */
60#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
Amit Singh Tomara29710c2016-07-06 17:59:44 +053061
62#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
63#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
64
65#define H3_EPHY_DEFAULT_VALUE 0x58000
66#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
67#define H3_EPHY_ADDR_SHIFT 20
68#define REG_PHY_ADDR_MASK GENMASK(4, 0)
69#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
70#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
71#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
72
73#define SC_RMII_EN BIT(13)
74#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
75#define SC_ETCS_MASK GENMASK(1, 0)
76#define SC_ETCS_EXT_GMII 0x1
77#define SC_ETCS_INT_GMII 0x2
Icenowy Zheng9b16ede2018-11-23 00:37:48 +010078#define SC_ETXDC_MASK GENMASK(12, 10)
79#define SC_ETXDC_OFFSET 10
80#define SC_ERXDC_MASK GENMASK(9, 5)
81#define SC_ERXDC_OFFSET 5
Amit Singh Tomara29710c2016-07-06 17:59:44 +053082
83#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
84
85#define AHB_GATE_OFFSET_EPHY 0
86
Lothar Feltenc6a21d62018-07-13 10:45:27 +020087/* IO mux settings */
88#define SUN8I_IOMUX_H3 2
Andre Przywaraeb5a2b62021-01-11 21:11:49 +010089#define SUN8I_IOMUX_R40 5
90#define SUN8I_IOMUX_H6 5
91#define SUN8I_IOMUX_H616 2
Lothar Feltenc6a21d62018-07-13 10:45:27 +020092#define SUN8I_IOMUX 4
Amit Singh Tomara29710c2016-07-06 17:59:44 +053093
94/* H3/A64 EMAC Register's offset */
95#define EMAC_CTL0 0x00
Andre Przywara4fe86412020-07-06 01:40:36 +010096#define EMAC_CTL0_FULL_DUPLEX BIT(0)
97#define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
98#define EMAC_CTL0_SPEED_10 (0x2 << 2)
99#define EMAC_CTL0_SPEED_100 (0x3 << 2)
100#define EMAC_CTL0_SPEED_1000 (0x0 << 2)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530101#define EMAC_CTL1 0x04
Andre Przywara4fe86412020-07-06 01:40:36 +0100102#define EMAC_CTL1_SOFT_RST BIT(0)
103#define EMAC_CTL1_BURST_LEN_SHIFT 24
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530104#define EMAC_INT_STA 0x08
105#define EMAC_INT_EN 0x0c
106#define EMAC_TX_CTL0 0x10
Andre Przywara4fe86412020-07-06 01:40:36 +0100107#define EMAC_TX_CTL0_TX_EN BIT(31)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530108#define EMAC_TX_CTL1 0x14
Andre Przywara4fe86412020-07-06 01:40:36 +0100109#define EMAC_TX_CTL1_TX_MD BIT(1)
110#define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
111#define EMAC_TX_CTL1_TX_DMA_START BIT(31)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530112#define EMAC_TX_FLOW_CTL 0x1c
113#define EMAC_TX_DMA_DESC 0x20
114#define EMAC_RX_CTL0 0x24
Andre Przywara4fe86412020-07-06 01:40:36 +0100115#define EMAC_RX_CTL0_RX_EN BIT(31)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530116#define EMAC_RX_CTL1 0x28
Andre Przywara4fe86412020-07-06 01:40:36 +0100117#define EMAC_RX_CTL1_RX_MD BIT(1)
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100118#define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
119#define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
Andre Przywara4fe86412020-07-06 01:40:36 +0100120#define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
121#define EMAC_RX_CTL1_RX_DMA_START BIT(31)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530122#define EMAC_RX_DMA_DESC 0x34
123#define EMAC_MII_CMD 0x48
124#define EMAC_MII_DATA 0x4c
125#define EMAC_ADDR0_HIGH 0x50
126#define EMAC_ADDR0_LOW 0x54
127#define EMAC_TX_DMA_STA 0xb0
128#define EMAC_TX_CUR_DESC 0xb4
129#define EMAC_TX_CUR_BUF 0xb8
130#define EMAC_RX_DMA_STA 0xc0
131#define EMAC_RX_CUR_DESC 0xc4
132
Andre Przywara4fe86412020-07-06 01:40:36 +0100133#define EMAC_DESC_OWN_DMA BIT(31)
134#define EMAC_DESC_LAST_DESC BIT(30)
135#define EMAC_DESC_FIRST_DESC BIT(29)
136#define EMAC_DESC_CHAIN_SECOND BIT(24)
137
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100138#define EMAC_DESC_RX_ERROR_MASK 0x400068db
139
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530140DECLARE_GLOBAL_DATA_PTR;
141
142enum emac_variant {
143 A83T_EMAC = 1,
144 H3_EMAC,
145 A64_EMAC,
Lothar Feltene46d73f2018-07-13 10:45:28 +0200146 R40_GMAC,
Samuel Holland99ac8612020-05-07 18:10:51 -0500147 H6_EMAC,
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530148};
149
150struct emac_dma_desc {
151 u32 status;
Andre Przywara4fe86412020-07-06 01:40:36 +0100152 u32 ctl_size;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530153 u32 buf_addr;
154 u32 next;
155} __aligned(ARCH_DMA_MINALIGN);
156
157struct emac_eth_dev {
158 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
159 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
160 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
161 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
162
163 u32 interface;
164 u32 phyaddr;
165 u32 link;
166 u32 speed;
167 u32 duplex;
168 u32 phy_configured;
169 u32 tx_currdescnum;
170 u32 rx_currdescnum;
171 u32 addr;
172 u32 tx_slot;
173 bool use_internal_phy;
174
175 enum emac_variant variant;
176 void *mac_reg;
177 phys_addr_t sysctl_reg;
178 struct phy_device *phydev;
179 struct mii_dev *bus;
Jagan Tekid3a2c052019-02-28 00:26:58 +0530180 struct clk tx_clk;
Jagan Teki23484532019-02-28 00:27:00 +0530181 struct clk ephy_clk;
Jagan Tekid3a2c052019-02-28 00:26:58 +0530182 struct reset_ctl tx_rst;
Jagan Teki23484532019-02-28 00:27:00 +0530183 struct reset_ctl ephy_rst;
Simon Glassbcee8d62019-12-06 21:41:35 -0700184#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100185 struct gpio_desc reset_gpio;
186#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530187};
188
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100189
190struct sun8i_eth_pdata {
191 struct eth_pdata eth_pdata;
192 u32 reset_delays[3];
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100193 int tx_delay_ps;
194 int rx_delay_ps;
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100195};
196
197
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530198static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
199{
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100200 struct udevice *dev = bus->priv;
201 struct emac_eth_dev *priv = dev_get_priv(dev);
Andre Przywaraf20f9462020-07-06 01:40:34 +0100202 u32 mii_cmd;
203 int ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530204
Andre Przywaraf20f9462020-07-06 01:40:34 +0100205 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530206 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
Andre Przywaraf20f9462020-07-06 01:40:34 +0100207 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530208 MDIO_CMD_MII_PHY_ADDR_MASK;
209
Andre Przywara4f0278d2020-07-06 01:40:45 +0100210 /*
211 * The EMAC clock is either 200 or 300 MHz, so we need a divider
212 * of 128 to get the MDIO frequency below the required 2.5 MHz.
213 */
Heinrich Schuchardt02036d92021-06-03 07:52:41 +0000214 if (!priv->use_internal_phy)
215 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
216 MDIO_CMD_MII_CLK_CSR_SHIFT;
Andre Przywara4f0278d2020-07-06 01:40:45 +0100217
Andre Przywaraf20f9462020-07-06 01:40:34 +0100218 mii_cmd |= MDIO_CMD_MII_BUSY;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530219
Andre Przywaraf20f9462020-07-06 01:40:34 +0100220 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530221
Andre Przywaraf20f9462020-07-06 01:40:34 +0100222 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
223 MDIO_CMD_MII_BUSY, false,
224 CONFIG_MDIO_TIMEOUT, true);
225 if (ret < 0)
226 return ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530227
Andre Przywaraf20f9462020-07-06 01:40:34 +0100228 return readl(priv->mac_reg + EMAC_MII_DATA);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530229}
230
231static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
232 u16 val)
233{
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100234 struct udevice *dev = bus->priv;
235 struct emac_eth_dev *priv = dev_get_priv(dev);
Andre Przywaraf20f9462020-07-06 01:40:34 +0100236 u32 mii_cmd;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530237
Andre Przywaraf20f9462020-07-06 01:40:34 +0100238 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530239 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
Andre Przywaraf20f9462020-07-06 01:40:34 +0100240 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530241 MDIO_CMD_MII_PHY_ADDR_MASK;
242
Andre Przywara4f0278d2020-07-06 01:40:45 +0100243 /*
244 * The EMAC clock is either 200 or 300 MHz, so we need a divider
245 * of 128 to get the MDIO frequency below the required 2.5 MHz.
246 */
Heinrich Schuchardt02036d92021-06-03 07:52:41 +0000247 if (!priv->use_internal_phy)
248 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
249 MDIO_CMD_MII_CLK_CSR_SHIFT;
Andre Przywara4f0278d2020-07-06 01:40:45 +0100250
Andre Przywaraf20f9462020-07-06 01:40:34 +0100251 mii_cmd |= MDIO_CMD_MII_WRITE;
252 mii_cmd |= MDIO_CMD_MII_BUSY;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530253
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530254 writel(val, priv->mac_reg + EMAC_MII_DATA);
Andre Przywaraf20f9462020-07-06 01:40:34 +0100255 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530256
Andre Przywaraf20f9462020-07-06 01:40:34 +0100257 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
258 MDIO_CMD_MII_BUSY, false,
259 CONFIG_MDIO_TIMEOUT, true);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530260}
261
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530262static int sun8i_eth_write_hwaddr(struct udevice *dev)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530263{
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530264 struct emac_eth_dev *priv = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700265 struct eth_pdata *pdata = dev_get_plat(dev);
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530266 uchar *mac_id = pdata->enetaddr;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530267 u32 macid_lo, macid_hi;
268
269 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
270 (mac_id[3] << 24);
271 macid_hi = mac_id[4] + (mac_id[5] << 8);
272
273 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
274 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
275
276 return 0;
277}
278
279static void sun8i_adjust_link(struct emac_eth_dev *priv,
280 struct phy_device *phydev)
281{
282 u32 v;
283
284 v = readl(priv->mac_reg + EMAC_CTL0);
285
286 if (phydev->duplex)
Andre Przywara4fe86412020-07-06 01:40:36 +0100287 v |= EMAC_CTL0_FULL_DUPLEX;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530288 else
Andre Przywara4fe86412020-07-06 01:40:36 +0100289 v &= ~EMAC_CTL0_FULL_DUPLEX;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530290
Andre Przywara4fe86412020-07-06 01:40:36 +0100291 v &= ~EMAC_CTL0_SPEED_MASK;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530292
293 switch (phydev->speed) {
294 case 1000:
Andre Przywara4fe86412020-07-06 01:40:36 +0100295 v |= EMAC_CTL0_SPEED_1000;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530296 break;
297 case 100:
Andre Przywara4fe86412020-07-06 01:40:36 +0100298 v |= EMAC_CTL0_SPEED_100;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530299 break;
300 case 10:
Andre Przywara4fe86412020-07-06 01:40:36 +0100301 v |= EMAC_CTL0_SPEED_10;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530302 break;
303 }
304 writel(v, priv->mac_reg + EMAC_CTL0);
305}
306
Andre Przywarab14e5202021-01-11 21:11:45 +0100307static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530308{
309 if (priv->use_internal_phy) {
310 /* H3 based SoC's that has an Internal 100MBit PHY
311 * needs to be configured and powered up before use
312 */
Andre Przywarab14e5202021-01-11 21:11:45 +0100313 reg &= ~H3_EPHY_DEFAULT_MASK;
314 reg |= H3_EPHY_DEFAULT_VALUE;
315 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
316 reg &= ~H3_EPHY_SHUTDOWN;
317 return reg | H3_EPHY_SELECT;
318 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530319
Andre Przywarab14e5202021-01-11 21:11:45 +0100320 /* This is to select External Gigabit PHY on those boards with
321 * an internal PHY. Does not hurt on other SoCs. Linux does
322 * it as well.
323 */
324 return reg & ~H3_EPHY_SELECT;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530325}
326
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100327static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
328 struct emac_eth_dev *priv)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530329{
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530330 u32 reg;
331
Jagan Teki695f6042019-02-28 00:26:51 +0530332 if (priv->variant == R40_GMAC) {
333 /* Select RGMII for R40 */
334 reg = readl(priv->sysctl_reg + 0x164);
Samuel Hollandabdbefb2020-05-07 18:10:50 -0500335 reg |= SC_ETCS_INT_GMII |
336 SC_EPIT |
337 (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530338
Jagan Teki695f6042019-02-28 00:26:51 +0530339 writel(reg, priv->sysctl_reg + 0x164);
Lothar Feltene46d73f2018-07-13 10:45:28 +0200340 return 0;
Jagan Teki695f6042019-02-28 00:26:51 +0530341 }
342
343 reg = readl(priv->sysctl_reg + 0x30);
Lothar Feltene46d73f2018-07-13 10:45:28 +0200344
Andre Przywarab14e5202021-01-11 21:11:45 +0100345 reg = sun8i_emac_set_syscon_ephy(priv, reg);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530346
347 reg &= ~(SC_ETCS_MASK | SC_EPIT);
Samuel Holland99ac8612020-05-07 18:10:51 -0500348 if (priv->variant == H3_EMAC ||
349 priv->variant == A64_EMAC ||
350 priv->variant == H6_EMAC)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530351 reg &= ~SC_RMII_EN;
352
353 switch (priv->interface) {
354 case PHY_INTERFACE_MODE_MII:
355 /* default */
356 break;
357 case PHY_INTERFACE_MODE_RGMII:
Andre Przywara219a5d52020-11-14 17:37:46 +0000358 case PHY_INTERFACE_MODE_RGMII_ID:
359 case PHY_INTERFACE_MODE_RGMII_RXID:
360 case PHY_INTERFACE_MODE_RGMII_TXID:
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530361 reg |= SC_EPIT | SC_ETCS_INT_GMII;
362 break;
363 case PHY_INTERFACE_MODE_RMII:
364 if (priv->variant == H3_EMAC ||
Samuel Holland99ac8612020-05-07 18:10:51 -0500365 priv->variant == A64_EMAC ||
366 priv->variant == H6_EMAC) {
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530367 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
368 break;
369 }
370 /* RMII not supported on A83T */
371 default:
372 debug("%s: Invalid PHY interface\n", __func__);
373 return -EINVAL;
374 }
375
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100376 if (pdata->tx_delay_ps)
377 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
378 & SC_ETXDC_MASK;
379
380 if (pdata->rx_delay_ps)
381 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
382 & SC_ERXDC_MASK;
383
Andre Przywara12afd952018-04-04 01:31:16 +0100384 writel(reg, priv->sysctl_reg + 0x30);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530385
386 return 0;
387}
388
389static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
390{
391 struct phy_device *phydev;
392
393 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
394 if (!phydev)
395 return -ENODEV;
396
397 phy_connect_dev(phydev, dev);
398
399 priv->phydev = phydev;
400 phy_config(priv->phydev);
401
402 return 0;
403}
404
Andre Przywara8c274ec2020-07-06 01:40:40 +0100405#define cache_clean_descriptor(desc) \
406 flush_dcache_range((uintptr_t)(desc), \
407 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
408
409#define cache_inv_descriptor(desc) \
410 invalidate_dcache_range((uintptr_t)(desc), \
411 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
412
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530413static void rx_descs_init(struct emac_eth_dev *priv)
414{
415 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
416 char *rxbuffs = &priv->rxbuffer[0];
417 struct emac_dma_desc *desc_p;
Andre Przywara09501ff2020-07-06 01:40:41 +0100418 int i;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530419
Andre Przywara69853122020-07-06 01:40:37 +0100420 /*
421 * Make sure we don't have dirty cache lines around, which could
422 * be cleaned to DRAM *after* the MAC has already written data to it.
423 */
424 invalidate_dcache_range((uintptr_t)desc_table_p,
425 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
426 invalidate_dcache_range((uintptr_t)rxbuffs,
427 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530428
Andre Przywara09501ff2020-07-06 01:40:41 +0100429 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
430 desc_p = &desc_table_p[i];
431 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
432 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
Andre Przywara69853122020-07-06 01:40:37 +0100433 desc_p->ctl_size = CONFIG_ETH_RXSIZE;
Andre Przywara4fe86412020-07-06 01:40:36 +0100434 desc_p->status = EMAC_DESC_OWN_DMA;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530435 }
436
437 /* Correcting the last pointer of the chain */
438 desc_p->next = (uintptr_t)&desc_table_p[0];
439
440 flush_dcache_range((uintptr_t)priv->rx_chain,
441 (uintptr_t)priv->rx_chain +
442 sizeof(priv->rx_chain));
443
444 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
445 priv->rx_currdescnum = 0;
446}
447
448static void tx_descs_init(struct emac_eth_dev *priv)
449{
450 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
451 char *txbuffs = &priv->txbuffer[0];
452 struct emac_dma_desc *desc_p;
Andre Przywara09501ff2020-07-06 01:40:41 +0100453 int i;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530454
Andre Przywara09501ff2020-07-06 01:40:41 +0100455 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
456 desc_p = &desc_table_p[i];
457 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
458 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
Andre Przywara4fe86412020-07-06 01:40:36 +0100459 desc_p->ctl_size = 0;
Andre Przywarac35380c2020-07-06 01:40:33 +0100460 desc_p->status = 0;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530461 }
462
463 /* Correcting the last pointer of the chain */
464 desc_p->next = (uintptr_t)&desc_table_p[0];
465
Andre Przywaraed909de2020-07-06 01:40:38 +0100466 /* Flush the first TX buffer descriptor we will tell the MAC about. */
Andre Przywara8c274ec2020-07-06 01:40:40 +0100467 cache_clean_descriptor(desc_table_p);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530468
469 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
470 priv->tx_currdescnum = 0;
471}
472
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530473static int sun8i_emac_eth_start(struct udevice *dev)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530474{
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530475 struct emac_eth_dev *priv = dev_get_priv(dev);
Andre Przywara2808cf62020-07-06 01:40:32 +0100476 int ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530477
Andre Przywara2c5600c2020-07-06 01:40:42 +0100478 /* Soft reset MAC */
479 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
480 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
481 EMAC_CTL1_SOFT_RST, false, 10, true);
482 if (ret) {
483 printf("%s: Timeout\n", __func__);
484 return ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530485 }
486
487 /* Rewrite mac address after reset */
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530488 sun8i_eth_write_hwaddr(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530489
Andre Przywara4fe86412020-07-06 01:40:36 +0100490 /* transmission starts after the full frame arrived in TX DMA FIFO */
491 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530492
Andre Przywara4fe86412020-07-06 01:40:36 +0100493 /*
494 * RX DMA reads data from RX DMA FIFO to host memory after a
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530495 * complete frame has been written to RX DMA FIFO
496 */
Andre Przywara4fe86412020-07-06 01:40:36 +0100497 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530498
Andre Przywara4fe86412020-07-06 01:40:36 +0100499 /* DMA burst length */
500 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530501
502 /* Initialize rx/tx descriptors */
503 rx_descs_init(priv);
504 tx_descs_init(priv);
505
506 /* PHY Start Up */
Andre Przywara2808cf62020-07-06 01:40:32 +0100507 ret = phy_startup(priv->phydev);
508 if (ret)
509 return ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530510
511 sun8i_adjust_link(priv, priv->phydev);
512
Andre Przywara4fe86412020-07-06 01:40:36 +0100513 /* Start RX/TX DMA */
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100514 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
515 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
Andre Przywara4fe86412020-07-06 01:40:36 +0100516 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530517
518 /* Enable RX/TX */
Andre Przywara4fe86412020-07-06 01:40:36 +0100519 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
520 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530521
522 return 0;
523}
524
525static int parse_phy_pins(struct udevice *dev)
526{
527 int offset;
528 const char *pin_name;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100529 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100530 u32 iomux;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530531
Simon Glasse160f7d2017-01-17 16:52:55 -0700532 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530533 "pinctrl-0");
534 if (offset < 0) {
535 printf("WARNING: emac: cannot find pinctrl-0 node\n");
536 return offset;
537 }
538
539 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
Andre Przywarac0341172018-04-04 01:31:15 +0100540 "drive-strength", ~0);
541 if (drive != ~0) {
542 if (drive <= 10)
543 drive = SUN4I_PINCTRL_10_MA;
544 else if (drive <= 20)
545 drive = SUN4I_PINCTRL_20_MA;
546 else if (drive <= 30)
547 drive = SUN4I_PINCTRL_30_MA;
548 else
549 drive = SUN4I_PINCTRL_40_MA;
Andre Przywarac0341172018-04-04 01:31:15 +0100550 }
551
552 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
553 pull = SUN4I_PINCTRL_PULL_UP;
Andre Przywarac0341172018-04-04 01:31:15 +0100554 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
555 pull = SUN4I_PINCTRL_PULL_DOWN;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100556
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100557 /*
558 * The GPIO pinmux value is an integration choice, so depends on the
559 * SoC, not the EMAC variant.
560 */
Andre Przywara4e26bc62021-04-16 00:53:17 +0100561 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100562 iomux = SUN8I_IOMUX_H3;
563 else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
564 iomux = SUN8I_IOMUX_R40;
565 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
566 iomux = SUN8I_IOMUX_H6;
567 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
568 iomux = SUN8I_IOMUX_H616;
Andre Przywara4e26bc62021-04-16 00:53:17 +0100569 else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100570 iomux = SUN8I_IOMUX;
Andre Przywara4e26bc62021-04-16 00:53:17 +0100571 else if (IS_ENABLED(CONFIG_MACH_SUN50I))
572 iomux = SUN8I_IOMUX;
573 else
574 BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100575
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530576 for (i = 0; ; i++) {
577 int pin;
578
Simon Glassb02e4042016-10-02 17:59:28 -0600579 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100580 "pins", i, NULL);
581 if (!pin_name)
582 break;
Andre Przywarac0341172018-04-04 01:31:15 +0100583
584 pin = sunxi_name_to_gpio(pin_name);
585 if (pin < 0)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530586 continue;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530587
Andre Przywaraeb5a2b62021-01-11 21:11:49 +0100588 sunxi_gpio_set_cfgpin(pin, iomux);
Lothar Feltenc6a21d62018-07-13 10:45:27 +0200589
Andre Przywarac0341172018-04-04 01:31:15 +0100590 if (drive != ~0)
591 sunxi_gpio_set_drv(pin, drive);
592 if (pull != ~0)
593 sunxi_gpio_set_pull(pin, pull);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530594 }
595
596 if (!i) {
Andre Przywarac0341172018-04-04 01:31:15 +0100597 printf("WARNING: emac: cannot find pins property\n");
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530598 return -2;
599 }
600
601 return 0;
602}
603
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530604static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530605{
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530606 struct emac_eth_dev *priv = dev_get_priv(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530607 u32 status, desc_num = priv->rx_currdescnum;
608 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100609 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
610 int length;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530611
612 /* Invalidate entire buffer descriptor */
Andre Przywara8c274ec2020-07-06 01:40:40 +0100613 cache_inv_descriptor(desc_p);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530614
615 status = desc_p->status;
616
617 /* Check for DMA own bit */
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100618 if (status & EMAC_DESC_OWN_DMA)
619 return -EAGAIN;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530620
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100621 length = (status >> 16) & 0x3fff;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530622
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100623 /* make sure we read from DRAM, not our cache */
624 invalidate_dcache_range(data_start,
625 data_start + roundup(length, ARCH_DMA_MINALIGN));
626
627 if (status & EMAC_DESC_RX_ERROR_MASK) {
628 debug("RX: packet error: 0x%x\n",
629 status & EMAC_DESC_RX_ERROR_MASK);
630 return 0;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530631 }
Andre Przywara7edcb4e2020-07-06 01:40:43 +0100632 if (length < 0x40) {
633 debug("RX: Bad Packet (runt)\n");
634 return 0;
635 }
636
637 if (length > CONFIG_ETH_RXSIZE) {
638 debug("RX: Too large packet (%d bytes)\n", length);
639 return 0;
640 }
641
642 *packetp = (uchar *)(ulong)desc_p->buf_addr;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530643
644 return length;
645}
646
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530647static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530648{
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530649 struct emac_eth_dev *priv = dev_get_priv(dev);
Andre Przywara4fe86412020-07-06 01:40:36 +0100650 u32 desc_num = priv->tx_currdescnum;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530651 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530652 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
653 uintptr_t data_end = data_start +
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530654 roundup(length, ARCH_DMA_MINALIGN);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530655
Andre Przywara4fe86412020-07-06 01:40:36 +0100656 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530657
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530658 memcpy((void *)data_start, packet, length);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530659
660 /* Flush data to be sent */
661 flush_dcache_range(data_start, data_end);
662
Andre Przywara4fe86412020-07-06 01:40:36 +0100663 /* frame begin and end */
664 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
665 desc_p->status = EMAC_DESC_OWN_DMA;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530666
Andre Przywara8c274ec2020-07-06 01:40:40 +0100667 /* make sure the MAC reads the actual data from DRAM */
668 cache_clean_descriptor(desc_p);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530669
670 /* Move to next Descriptor and wrap around */
671 if (++desc_num >= CONFIG_TX_DESCR_NUM)
672 desc_num = 0;
673 priv->tx_currdescnum = desc_num;
674
675 /* Start the DMA */
Andre Przywara4fe86412020-07-06 01:40:36 +0100676 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
677
678 /*
679 * Since we copied the data above, we return here without waiting
680 * for the packet to be actually send out.
681 */
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530682
683 return 0;
684}
685
Sean Andersonef043692020-09-15 10:45:00 -0400686static int sun8i_emac_board_setup(struct udevice *dev,
687 struct emac_eth_dev *priv)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530688{
Jagan Tekid3a2c052019-02-28 00:26:58 +0530689 int ret;
690
691 ret = clk_enable(&priv->tx_clk);
692 if (ret) {
693 dev_err(dev, "failed to enable TX clock\n");
694 return ret;
695 }
696
697 if (reset_valid(&priv->tx_rst)) {
698 ret = reset_deassert(&priv->tx_rst);
699 if (ret) {
700 dev_err(dev, "failed to deassert TX reset\n");
701 goto err_tx_clk;
702 }
703 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530704
Jagan Teki23484532019-02-28 00:27:00 +0530705 /* Only H3/H5 have clock controls for internal EPHY */
706 if (clk_valid(&priv->ephy_clk)) {
707 ret = clk_enable(&priv->ephy_clk);
708 if (ret) {
709 dev_err(dev, "failed to enable EPHY TX clock\n");
710 return ret;
711 }
712 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530713
Jagan Teki23484532019-02-28 00:27:00 +0530714 if (reset_valid(&priv->ephy_rst)) {
715 ret = reset_deassert(&priv->ephy_rst);
716 if (ret) {
717 dev_err(dev, "failed to deassert EPHY TX clock\n");
718 return ret;
Lothar Feltenc6a21d62018-07-13 10:45:27 +0200719 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530720 }
721
Jagan Tekid3a2c052019-02-28 00:26:58 +0530722 return 0;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530723
Jagan Tekid3a2c052019-02-28 00:26:58 +0530724err_tx_clk:
725 clk_disable(&priv->tx_clk);
726 return ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530727}
728
Simon Glassbcee8d62019-12-06 21:41:35 -0700729#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100730static int sun8i_mdio_reset(struct mii_dev *bus)
731{
732 struct udevice *dev = bus->priv;
733 struct emac_eth_dev *priv = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700734 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100735 int ret;
736
737 if (!dm_gpio_is_valid(&priv->reset_gpio))
738 return 0;
739
740 /* reset the phy */
741 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
742 if (ret)
743 return ret;
744
745 udelay(pdata->reset_delays[0]);
746
747 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
748 if (ret)
749 return ret;
750
751 udelay(pdata->reset_delays[1]);
752
753 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
754 if (ret)
755 return ret;
756
757 udelay(pdata->reset_delays[2]);
758
759 return 0;
760}
761#endif
762
763static int sun8i_mdio_init(const char *name, struct udevice *priv)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530764{
765 struct mii_dev *bus = mdio_alloc();
766
767 if (!bus) {
768 debug("Failed to allocate MDIO bus\n");
769 return -ENOMEM;
770 }
771
772 bus->read = sun8i_mdio_read;
773 bus->write = sun8i_mdio_write;
774 snprintf(bus->name, sizeof(bus->name), name);
775 bus->priv = (void *)priv;
Simon Glassbcee8d62019-12-06 21:41:35 -0700776#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100777 bus->reset = sun8i_mdio_reset;
778#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530779
780 return mdio_register(bus);
781}
782
Andre Przywaraa5b2a992020-10-21 23:21:42 +0530783static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
784 int length)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530785{
786 struct emac_eth_dev *priv = dev_get_priv(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530787 u32 desc_num = priv->rx_currdescnum;
788 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530789
Andre Przywara8c274ec2020-07-06 01:40:40 +0100790 /* give the current descriptor back to the MAC */
Andre Przywara4fe86412020-07-06 01:40:36 +0100791 desc_p->status |= EMAC_DESC_OWN_DMA;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530792
793 /* Flush Status field of descriptor */
Andre Przywara8c274ec2020-07-06 01:40:40 +0100794 cache_clean_descriptor(desc_p);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530795
796 /* Move to next desc and wrap-around condition. */
797 if (++desc_num >= CONFIG_RX_DESCR_NUM)
798 desc_num = 0;
799 priv->rx_currdescnum = desc_num;
800
801 return 0;
802}
803
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530804static void sun8i_emac_eth_stop(struct udevice *dev)
805{
806 struct emac_eth_dev *priv = dev_get_priv(dev);
807
808 /* Stop Rx/Tx transmitter */
Andre Przywara4fe86412020-07-06 01:40:36 +0100809 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
810 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530811
Andre Przywara4fe86412020-07-06 01:40:36 +0100812 /* Stop RX/TX DMA */
813 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
814 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530815
816 phy_shutdown(priv->phydev);
817}
818
819static int sun8i_emac_eth_probe(struct udevice *dev)
820{
Simon Glassc69cda22020-12-03 16:55:20 -0700821 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100822 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530823 struct emac_eth_dev *priv = dev_get_priv(dev);
Jagan Tekid3a2c052019-02-28 00:26:58 +0530824 int ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530825
826 priv->mac_reg = (void *)pdata->iobase;
827
Sean Andersonef043692020-09-15 10:45:00 -0400828 ret = sun8i_emac_board_setup(dev, priv);
Jagan Tekid3a2c052019-02-28 00:26:58 +0530829 if (ret)
830 return ret;
831
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100832 sun8i_emac_set_syscon(sun8i_pdata, priv);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530833
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100834 sun8i_mdio_init(dev->name, dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530835 priv->bus = miiphy_get_dev_by_name(dev->name);
836
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530837 return sun8i_phy_init(priv, dev);
838}
839
840static const struct eth_ops sun8i_emac_eth_ops = {
841 .start = sun8i_emac_eth_start,
842 .write_hwaddr = sun8i_eth_write_hwaddr,
843 .send = sun8i_emac_eth_send,
844 .recv = sun8i_emac_eth_recv,
845 .free_pkt = sun8i_eth_free_pkt,
846 .stop = sun8i_emac_eth_stop,
847};
848
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530849static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
Jagan Teki23484532019-02-28 00:27:00 +0530850{
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530851 struct ofnode_phandle_args phandle;
852 int ret;
Emmanuel Vadotd53e5222019-07-19 22:26:38 +0200853
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530854 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
855 NULL, 0, 0, &phandle);
856 if (ret)
857 return ret;
Jagan Teki23484532019-02-28 00:27:00 +0530858
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530859 /* If the PHY node is not a child of the internal MDIO bus, we are
860 * using some external PHY.
861 */
862 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
863 "allwinner,sun8i-h3-mdio-internal"))
Emmanuel Vadotd53e5222019-07-19 22:26:38 +0200864 return 0;
865
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530866 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
Jagan Teki23484532019-02-28 00:27:00 +0530867 if (ret) {
868 dev_err(dev, "failed to get EPHY TX clock\n");
869 return ret;
870 }
871
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530872 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
Jagan Teki23484532019-02-28 00:27:00 +0530873 if (ret) {
874 dev_err(dev, "failed to get EPHY TX reset\n");
875 return ret;
876 }
877
878 priv->use_internal_phy = true;
879
880 return 0;
881}
882
Simon Glassd1998a92020-12-03 16:55:21 -0700883static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530884{
Simon Glassc69cda22020-12-03 16:55:20 -0700885 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100886 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530887 struct emac_eth_dev *priv = dev_get_priv(dev);
888 const char *phy_mode;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100889 const fdt32_t *reg;
Simon Glasse160f7d2017-01-17 16:52:55 -0700890 int node = dev_of_offset(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530891 int offset = 0;
Simon Glassbcee8d62019-12-06 21:41:35 -0700892#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100893 int reset_flags = GPIOD_IS_OUT;
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100894#endif
Jagan Tekid3a2c052019-02-28 00:26:58 +0530895 int ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530896
Masahiro Yamada25484932020-07-17 14:36:48 +0900897 pdata->iobase = dev_read_addr(dev);
Andre Przywara12afd952018-04-04 01:31:16 +0100898 if (pdata->iobase == FDT_ADDR_T_NONE) {
899 debug("%s: Cannot find MAC base address\n", __func__);
900 return -EINVAL;
901 }
902
Lothar Feltene46d73f2018-07-13 10:45:28 +0200903 priv->variant = dev_get_driver_data(dev);
904
905 if (!priv->variant) {
906 printf("%s: Missing variant\n", __func__);
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100907 return -EINVAL;
Andre Przywara12afd952018-04-04 01:31:16 +0100908 }
Lothar Feltene46d73f2018-07-13 10:45:28 +0200909
Jagan Tekid3a2c052019-02-28 00:26:58 +0530910 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
911 if (ret) {
912 dev_err(dev, "failed to get TX clock\n");
913 return ret;
914 }
915
916 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
917 if (ret && ret != -ENOENT) {
918 dev_err(dev, "failed to get TX reset\n");
919 return ret;
920 }
921
Jagan Teki695f6042019-02-28 00:26:51 +0530922 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
923 if (offset < 0) {
924 debug("%s: cannot find syscon node\n", __func__);
925 return -EINVAL;
926 }
927
928 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
929 if (!reg) {
930 debug("%s: cannot find reg property in syscon node\n",
931 __func__);
932 return -EINVAL;
933 }
934 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
935 offset, reg);
936 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
937 debug("%s: Cannot find syscon base address\n", __func__);
938 return -EINVAL;
Andre Przywara12afd952018-04-04 01:31:16 +0100939 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530940
941 pdata->phy_interface = -1;
942 priv->phyaddr = -1;
943 priv->use_internal_phy = false;
944
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100945 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
Andre Przywara12afd952018-04-04 01:31:16 +0100946 if (offset < 0) {
947 debug("%s: Cannot find PHY address\n", __func__);
948 return -EINVAL;
949 }
950 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530951
Simon Glasse160f7d2017-01-17 16:52:55 -0700952 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530953
954 if (phy_mode)
955 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
956 printf("phy interface%d\n", pdata->phy_interface);
957
958 if (pdata->phy_interface == -1) {
959 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
960 return -EINVAL;
961 }
962
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530963 if (priv->variant == H3_EMAC) {
Andre Przywara88ae8fb2020-10-21 23:27:32 +0530964 ret = sun8i_handle_internal_phy(dev, priv);
Jagan Teki23484532019-02-28 00:27:00 +0530965 if (ret)
966 return ret;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530967 }
968
969 priv->interface = pdata->phy_interface;
970
971 if (!priv->use_internal_phy)
972 parse_phy_pins(dev);
973
Icenowy Zheng9b16ede2018-11-23 00:37:48 +0100974 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
975 "allwinner,tx-delay-ps", 0);
976 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
977 printf("%s: Invalid TX delay value %d\n", __func__,
978 sun8i_pdata->tx_delay_ps);
979
980 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
981 "allwinner,rx-delay-ps", 0);
982 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
983 printf("%s: Invalid RX delay value %d\n", __func__,
984 sun8i_pdata->rx_delay_ps);
985
Simon Glassbcee8d62019-12-06 21:41:35 -0700986#if CONFIG_IS_ENABLED(DM_GPIO)
Simon Glassda409cc2017-05-17 17:18:09 -0600987 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100988 "snps,reset-active-low"))
989 reset_flags |= GPIOD_ACTIVE_LOW;
990
991 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
992 &priv->reset_gpio, reset_flags);
993
994 if (ret == 0) {
Simon Glassda409cc2017-05-17 17:18:09 -0600995 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100996 "snps,reset-delays-us",
997 sun8i_pdata->reset_delays, 3);
998 } else if (ret == -ENOENT) {
999 ret = 0;
1000 }
1001#endif
1002
Amit Singh Tomara29710c2016-07-06 17:59:44 +05301003 return 0;
1004}
1005
1006static const struct udevice_id sun8i_emac_eth_ids[] = {
1007 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1008 {.compatible = "allwinner,sun50i-a64-emac",
1009 .data = (uintptr_t)A64_EMAC },
1010 {.compatible = "allwinner,sun8i-a83t-emac",
1011 .data = (uintptr_t)A83T_EMAC },
Lothar Feltene46d73f2018-07-13 10:45:28 +02001012 {.compatible = "allwinner,sun8i-r40-gmac",
1013 .data = (uintptr_t)R40_GMAC },
Samuel Holland99ac8612020-05-07 18:10:51 -05001014 {.compatible = "allwinner,sun50i-h6-emac",
1015 .data = (uintptr_t)H6_EMAC },
Amit Singh Tomara29710c2016-07-06 17:59:44 +05301016 { }
1017};
1018
1019U_BOOT_DRIVER(eth_sun8i_emac) = {
1020 .name = "eth_sun8i_emac",
1021 .id = UCLASS_ETH,
1022 .of_match = sun8i_emac_eth_ids,
Simon Glassd1998a92020-12-03 16:55:21 -07001023 .of_to_plat = sun8i_emac_eth_of_to_plat,
Amit Singh Tomara29710c2016-07-06 17:59:44 +05301024 .probe = sun8i_emac_eth_probe,
1025 .ops = &sun8i_emac_eth_ops,
Simon Glass41575d82020-12-03 16:55:17 -07001026 .priv_auto = sizeof(struct emac_eth_dev),
Simon Glasscaa4daa2020-12-03 16:55:18 -07001027 .plat_auto = sizeof(struct sun8i_eth_pdata),
Amit Singh Tomara29710c2016-07-06 17:59:44 +05301028 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1029};