blob: d0ae923ec3e7bf5d2f96956141cda2020d979e7d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Timur Tabi2ad6b512006-10-31 18:44:42 -06002/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06004 */
5
6/*
Timur Tabi7a78f142007-01-31 15:54:29 -06007 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -06008
9 Memory map:
10
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060017 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060018 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060019 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060022
23 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010024 Align. Board
25 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060026 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010027 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060028
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010029 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060035
36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
37*/
38
39#ifndef __CONFIG_H
40#define __CONFIG_H
41
Timur Tabi89c77842008-02-08 13:15:55 -060042#define CONFIG_MISC_INIT_F
Timur Tabi7a78f142007-01-31 15:54:29 -060043
Timur Tabi89c77842008-02-08 13:15:55 -060044/*
45 * On-board devices
46 */
Timur Tabi7a78f142007-01-31 15:54:29 -060047
Mario Six4cb06d32019-01-21 09:17:44 +010048#ifdef CONFIG_TARGET_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -050049/* The CF card interface on the back of the board */
50#define CONFIG_COMPACT_FLASH
Timur Tabi89c77842008-02-08 13:15:55 -060051#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +030052#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060053#endif
54
Timur Tabi2ad6b512006-10-31 18:44:42 -060055#define CONFIG_RTC_DS1337
Heiko Schocher00f792e2012-10-24 13:48:22 +020056#define CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -060057
58/*
59 * Device configurations
60 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060061
62/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020063#ifdef CONFIG_SYS_I2C
64#define CONFIG_SYS_I2C_FSL
65#define CONFIG_SYS_FSL_I2C_SPEED 400000
66#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
67#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
68#define CONFIG_SYS_FSL_I2C2_SPEED 400000
69#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
70#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi2ad6b512006-10-31 18:44:42 -060071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +020073#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -060074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
76#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
77#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
78#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
79#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger396abba2011-10-11 23:57:15 -050080#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
81#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -060082
Timur Tabi2ad6b512006-10-31 18:44:42 -060083/* Don't probe these addresses: */
Joe Hershberger396abba2011-10-11 23:57:15 -050084#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
86 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger396abba2011-10-11 23:57:15 -050087 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi2ad6b512006-10-31 18:44:42 -060088/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger396abba2011-10-11 23:57:15 -050089 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
90#define I2C_8574_REVISION 0x03
Timur Tabi2ad6b512006-10-31 18:44:42 -060091#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
92#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
93#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
94#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
95
Timur Tabi2ad6b512006-10-31 18:44:42 -060096#endif
97
Timur Tabi7a78f142007-01-31 15:54:29 -060098/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -060099#ifdef CONFIG_COMPACT_FLASH
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_IDE_MAXBUS 1
102#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
105#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
106#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
107#define CONFIG_SYS_ATA_REG_OFFSET 0
108#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
109#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600110
Joe Hershberger396abba2011-10-11 23:57:15 -0500111/* If a CF card is not inserted, time out quickly */
112#define ATA_RESET_TIME 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600113
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200114#endif
115
116/*
117 * SATA
118 */
119#ifdef CONFIG_SATA_SIL3114
120
121#define CONFIG_SYS_SATA_MAX_DEVICE 4
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200122#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600123
Timur Tabi7a78f142007-01-31 15:54:29 -0600124#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600125
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300126#ifdef CONFIG_SYS_USB_HOST
127/*
128 * Support USB
129 */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300130#define CONFIG_USB_EHCI_FSL
131
132/* Current USB implementation supports the only USB controller,
133 * so we have to choose between the MPH or the DR ones */
134#if 1
135#define CONFIG_HAS_FSL_MPH_USB
136#else
137#define CONFIG_HAS_FSL_DR_USB
138#endif
139
140#endif
141
Timur Tabi7a78f142007-01-31 15:54:29 -0600142/*
143 * DDR Setup
144 */
Mario Six8a81bfd2019-01-21 09:18:15 +0100145#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger396abba2011-10-11 23:57:15 -0500147#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600149
Joe Hershberger396abba2011-10-11 23:57:15 -0500150#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
151 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500152
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200153#define CONFIG_VERY_BIG_RAM
154#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
155
Heiko Schocher00f792e2012-10-24 13:48:22 +0200156#ifdef CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -0600157#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
158#endif
159
Joe Hershberger396abba2011-10-11 23:57:15 -0500160/* No SPD? Then manually set up DDR parameters */
161#ifndef CONFIG_SPD_EEPROM
162 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500163 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger396abba2011-10-11 23:57:15 -0500164 | CSCONFIG_ROW_BIT_13 \
165 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
168 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600169#endif
170
171/*
172 *Flash on the Local Bus
173 */
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
176#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger396abba2011-10-11 23:57:15 -0500177/* 127 64KB sectors + 8 8KB sectors per device */
178#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600182
183/* The ITX has two flash chips, but the ITX-GP has only one. To support both
184boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger396abba2011-10-11 23:57:15 -0500186#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
187#define CONFIG_SYS_FLASH_BANKS_LIST \
188 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
189#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Timur Tabi7a78f142007-01-31 15:54:29 -0600190
Timur Tabi89c77842008-02-08 13:15:55 -0600191/* Vitesse 7385 */
192
193#ifdef CONFIG_VSC7385_ENET
194
195#define CONFIG_TSEC2
196
197/* The flash address and size of the VSC7385 firmware image */
198#define CONFIG_VSC7385_IMAGE 0xFEFFE000
199#define CONFIG_VSC7385_IMAGE_SIZE 8192
200
201#endif
202
Timur Tabi7a78f142007-01-31 15:54:29 -0600203/*
204 * BRx, ORx, LBLAWBARx, and LBLAWARx
205 */
206
Timur Tabi7a78f142007-01-31 15:54:29 -0600207
Timur Tabi7a78f142007-01-31 15:54:29 -0600208/* Vitesse 7385 */
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600211
Joe Hershberger396abba2011-10-11 23:57:15 -0500212#define CONFIG_SYS_LED_BASE 0xF9000000
Mario Sixa8f97532019-01-21 09:18:01 +0100213
Timur Tabi7a78f142007-01-31 15:54:29 -0600214
215/* Compact Flash */
216
217#ifdef CONFIG_COMPACT_FLASH
218
Joe Hershberger396abba2011-10-11 23:57:15 -0500219#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600220
Timur Tabi7a78f142007-01-31 15:54:29 -0600221
Timur Tabi7a78f142007-01-31 15:54:29 -0600222#endif
223
224/*
225 * U-Boot memory configuration
226 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
230#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600231#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600233#endif
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger396abba2011-10-11 23:57:15 -0500236#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
237#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600238
Joe Hershberger396abba2011-10-11 23:57:15 -0500239#define CONFIG_SYS_GBL_DATA_OFFSET \
240 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao16c8c172016-07-08 11:25:14 +0800244#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500245#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600246
247/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600248 * Serial Port
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_NS16550_SERIAL
251#define CONFIG_SYS_NS16550_REG_SIZE 1
252#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger396abba2011-10-11 23:57:15 -0500255 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi7a78f142007-01-31 15:54:29 -0600256
Simon Glass83302fb2016-10-17 20:12:38 -0600257#define CONSOLE ttyS0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
260#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600261
Timur Tabi7a78f142007-01-31 15:54:29 -0600262/*
263 * PCI
264 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600265#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000266#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600267
268#define CONFIG_MPC83XX_PCI2
269
270/*
271 * General PCI
272 * Addresses are mapped 1-1.
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
275#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
276#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500277#define CONFIG_SYS_PCI1_MMIO_BASE \
278 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
280#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500281#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
282#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
283#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600284
285#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500286#define CONFIG_SYS_PCI2_MEM_BASE \
287 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
289#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500290#define CONFIG_SYS_PCI2_MMIO_BASE \
291 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
293#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500294#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
295#define CONFIG_SYS_PCI2_IO_PHYS \
296 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
297#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600298#endif
299
Timur Tabi2ad6b512006-10-31 18:44:42 -0600300#ifndef CONFIG_PCI_PNP
301 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600303 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
304#endif
305
306#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
307
308#endif
309
310/* TSEC */
311
312#ifdef CONFIG_TSEC_ENET
Kim Phillips255a35772007-05-16 16:52:19 -0500313#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600314
Kim Phillips255a35772007-05-16 16:52:19 -0500315#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500316#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500317#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100319#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600320#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500321#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600322#endif
323
Kim Phillips255a35772007-05-16 16:52:19 -0500324#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600325#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500326#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600328
Timur Tabi2ad6b512006-10-31 18:44:42 -0600329#define TSEC2_PHY_ADDR 4
330#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500331#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600332#endif
333
334#define CONFIG_ETHPRIME "Freescale TSEC"
335
336#endif
337
Timur Tabi2ad6b512006-10-31 18:44:42 -0600338/*
339 * Environment
340 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600341#define CONFIG_ENV_OVERWRITE
342
Timur Tabi2ad6b512006-10-31 18:44:42 -0600343#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600345
Jon Loeliger8ea54992007-07-04 22:30:06 -0500346/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500347 * BOOTP options
348 */
349#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger659e2f62007-07-10 09:10:49 -0500350
Timur Tabi2ad6b512006-10-31 18:44:42 -0600351/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600352#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600353
354/*
355 * Miscellaneous configurable options
356 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips05f91a62009-08-26 21:27:37 -0500359#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600360
Timur Tabi2ad6b512006-10-31 18:44:42 -0600361/*
362 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700363 * have to be in the first 256 MB of memory, since this is
Timur Tabi2ad6b512006-10-31 18:44:42 -0600364 * the maximum mapped by the Linux kernel during initialization.
365 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500366 /* Initial Memory map for Linux*/
367#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800368#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600369
Timur Tabi7a78f142007-01-31 15:54:29 -0600370/*
371 * System performance
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
374#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300375#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
376#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600377
Timur Tabi7a78f142007-01-31 15:54:29 -0600378/*
379 * System IO Config
380 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500381/* Needed for gigabit to work on TSEC 1 */
382#define CONFIG_SYS_SICRH SICRH_TSOBI1
383 /* USB DR as device + USB MPH as host */
384#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600385
Jon Loeliger8ea54992007-07-04 22:30:06 -0500386#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600387#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600388#endif
389
Timur Tabi2ad6b512006-10-31 18:44:42 -0600390/*
391 * Environment Configuration
392 */
393#define CONFIG_ENV_OVERWRITE
394
Joe Hershberger396abba2011-10-11 23:57:15 -0500395#define CONFIG_NETDEV "eth0"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600396
Timur Tabi7a78f142007-01-31 15:54:29 -0600397/* Default path and filenames */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000398#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000399#define CONFIG_BOOTFILE "uImage"
Joe Hershberger396abba2011-10-11 23:57:15 -0500400 /* U-Boot image on TFTP server */
401#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600402
Mario Six4cb06d32019-01-21 09:17:44 +0100403#ifdef CONFIG_TARGET_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500404#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600405#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500406#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600407#endif
408
Timur Tabi7a78f142007-01-31 15:54:29 -0600409
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100410#define CONFIG_EXTRA_ENV_SETTINGS \
Simon Glass83302fb2016-10-17 20:12:38 -0600411 "console=" __stringify(CONSOLE) "\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500412 "netdev=" CONFIG_NETDEV "\0" \
413 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200414 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200415 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
416 " +$filesize; " \
417 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
418 " +$filesize; " \
419 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
420 " $filesize; " \
421 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
422 " +$filesize; " \
423 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
424 " $filesize\0" \
Kim Phillips05f91a62009-08-26 21:27:37 -0500425 "fdtaddr=780000\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500426 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600427
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100428#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600429 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500430 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi7a78f142007-01-31 15:54:29 -0600431 " console=$console,$baudrate $othbootargs; " \
432 "tftp $loadaddr $bootfile;" \
433 "tftp $fdtaddr $fdtfile;" \
434 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600435
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100436#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600437 "setenv bootargs root=/dev/ram rw" \
438 " console=$console,$baudrate $othbootargs; " \
439 "tftp $ramdiskaddr $ramdiskfile;" \
440 "tftp $loadaddr $bootfile;" \
441 "tftp $fdtaddr $fdtfile;" \
442 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600443
Timur Tabi2ad6b512006-10-31 18:44:42 -0600444#endif