Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 2 | /* |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 3 | * (C) Copyright 2010-2015 |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 4 | * NVIDIA Corporation <www.nvidia.com> |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 9edefc2 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 9b4a205 | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 12 | #include <ns16550.h> |
Simon Glass | 537e967 | 2015-05-13 07:02:29 -0600 | [diff] [blame] | 13 | #include <spl.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <asm/cache.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 15 | #include <asm/global_data.h> |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 16 | #include <asm/io.h> |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 17 | #if IS_ENABLED(CONFIG_TEGRA_CLKRST) |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 18 | #include <asm/arch/clock.h> |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 19 | #endif |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 20 | #if IS_ENABLED(CONFIG_TEGRA_PINCTRL) |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 21 | #include <asm/arch/funcmux.h> |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 22 | #endif |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 23 | #if IS_ENABLED(CONFIG_TEGRA_MC) |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 24 | #include <asm/arch/mc.h> |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 25 | #endif |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 26 | #include <asm/arch/tegra.h> |
Stephen Warren | 73c3893 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 27 | #include <asm/arch-tegra/ap.h> |
Lucas Stach | 516f00b | 2012-09-29 10:02:08 +0000 | [diff] [blame] | 28 | #include <asm/arch-tegra/board.h> |
Thierry Reding | a0dbc13 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 29 | #include <asm/arch-tegra/cboot.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 30 | #include <asm/arch-tegra/pmc.h> |
| 31 | #include <asm/arch-tegra/sys_proto.h> |
| 32 | #include <asm/arch-tegra/warmboot.h> |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 33 | |
Tom Warren | 659a075 | 2015-07-08 08:05:35 -0700 | [diff] [blame] | 34 | void save_boot_params_ret(void); |
| 35 | |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 38 | enum { |
| 39 | /* UARTs which we can enable */ |
| 40 | UARTA = 1 << 0, |
| 41 | UARTB = 1 << 1, |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 42 | UARTC = 1 << 2, |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 43 | UARTD = 1 << 3, |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 44 | UARTE = 1 << 4, |
| 45 | UART_COUNT = 5, |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 46 | }; |
| 47 | |
Marek BehĂșn | 236f2ec | 2021-05-20 13:23:52 +0200 | [diff] [blame] | 48 | static bool from_spl __section(".data"); |
Simon Glass | 537e967 | 2015-05-13 07:02:29 -0600 | [diff] [blame] | 49 | |
| 50 | #ifndef CONFIG_SPL_BUILD |
Thierry Reding | 8f60d18 | 2019-04-15 11:32:23 +0200 | [diff] [blame] | 51 | void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, |
| 52 | unsigned long r3) |
Simon Glass | 537e967 | 2015-05-13 07:02:29 -0600 | [diff] [blame] | 53 | { |
| 54 | from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; |
Thierry Reding | a0dbc13 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * The logic for this is somewhat indirect. The purpose of the marker |
| 58 | * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot |
| 59 | * was loaded from a read-only instance of itself, which is something |
| 60 | * that can happen in secure boot setups. So basically the presence |
| 61 | * of the marker is an indication that U-Boot was loaded by one such |
| 62 | * special variant of U-Boot. Conversely, the absence of the marker |
| 63 | * indicates that this instance of U-Boot was loaded by something |
| 64 | * other than a special U-Boot. This could be SPL, but it could just |
| 65 | * as well be one of any number of other first stage bootloaders. |
| 66 | */ |
| 67 | if (from_spl) |
| 68 | cboot_save_boot_params(r0, r1, r2, r3); |
| 69 | |
Simon Glass | 537e967 | 2015-05-13 07:02:29 -0600 | [diff] [blame] | 70 | save_boot_params_ret(); |
| 71 | } |
| 72 | #endif |
| 73 | |
| 74 | bool spl_was_boot_source(void) |
| 75 | { |
| 76 | return from_spl; |
| 77 | } |
| 78 | |
Stephen Warren | 73c3893 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 79 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
| 80 | #if !defined(CONFIG_TEGRA124) |
| 81 | #error tegra_cpu_is_non_secure has only been validated on Tegra124 |
| 82 | #endif |
| 83 | bool tegra_cpu_is_non_secure(void) |
| 84 | { |
| 85 | /* |
| 86 | * This register reads 0xffffffff in non-secure mode. This register |
| 87 | * only implements bits 31:20, so the lower bits will always read 0 in |
| 88 | * secure mode. Thus, the lower bits are an indicator for secure vs. |
| 89 | * non-secure mode. |
| 90 | */ |
| 91 | struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; |
| 92 | uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); |
| 93 | return (mc_s_cfg0 & 1) == 1; |
| 94 | } |
| 95 | #endif |
| 96 | |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 97 | #if IS_ENABLED(CONFIG_TEGRA_MC) |
Stephen Warren | aeb3fcb | 2014-07-02 14:12:30 -0600 | [diff] [blame] | 98 | /* Read the RAM size directly from the memory controller */ |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 99 | static phys_size_t query_sdram_size(void) |
Stephen Warren | aeb3fcb | 2014-07-02 14:12:30 -0600 | [diff] [blame] | 100 | { |
| 101 | struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 102 | u32 emem_cfg; |
| 103 | phys_size_t size_bytes; |
Stephen Warren | aeb3fcb | 2014-07-02 14:12:30 -0600 | [diff] [blame] | 104 | |
Stephen Warren | 3a2cab5 | 2014-12-23 10:34:50 -0700 | [diff] [blame] | 105 | emem_cfg = readl(&mc->mc_emem_cfg); |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 106 | #if defined(CONFIG_TEGRA20) |
Stephen Warren | 3a2cab5 | 2014-12-23 10:34:50 -0700 | [diff] [blame] | 107 | debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); |
| 108 | size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 109 | #else |
Stephen Warren | 3a2cab5 | 2014-12-23 10:34:50 -0700 | [diff] [blame] | 110 | debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 111 | #ifndef CONFIG_PHYS_64BIT |
Stephen Warren | 56519c4 | 2014-12-23 10:34:51 -0700 | [diff] [blame] | 112 | /* |
| 113 | * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits |
| 114 | * and will wrap. Clip the reported size to the maximum that a 32-bit |
| 115 | * variable can represent (rounded to a page). |
| 116 | */ |
| 117 | if (emem_cfg >= 4096) { |
| 118 | size_bytes = U32_MAX & ~(0x1000 - 1); |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 119 | } else |
| 120 | #endif |
| 121 | { |
Stephen Warren | 56519c4 | 2014-12-23 10:34:51 -0700 | [diff] [blame] | 122 | /* RAM size EMC is programmed to. */ |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 123 | size_bytes = (phys_size_t)emem_cfg * 1024 * 1024; |
| 124 | #ifndef CONFIG_ARM64 |
Stephen Warren | 56519c4 | 2014-12-23 10:34:51 -0700 | [diff] [blame] | 125 | /* |
| 126 | * If all RAM fits within 32-bits, it can be accessed without |
| 127 | * LPAE, so go test the RAM size. Otherwise, we can't access |
| 128 | * all the RAM, and get_ram_size() would get confused, so |
| 129 | * avoid using it. There's no reason we should need this |
| 130 | * validation step anyway. |
| 131 | */ |
| 132 | if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) |
| 133 | size_bytes = get_ram_size((void *)PHYS_SDRAM_1, |
| 134 | size_bytes); |
Stephen Warren | a5fc3d0 | 2015-08-07 16:12:44 -0600 | [diff] [blame] | 135 | #endif |
Stephen Warren | 56519c4 | 2014-12-23 10:34:51 -0700 | [diff] [blame] | 136 | } |
Stephen Warren | aeb3fcb | 2014-07-02 14:12:30 -0600 | [diff] [blame] | 137 | #endif |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 138 | |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 139 | #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) |
| 140 | /* External memory limited to 2047 MB due to IROM/HI-VEC */ |
Stephen Warren | 3a2cab5 | 2014-12-23 10:34:50 -0700 | [diff] [blame] | 141 | if (size_bytes == SZ_2G) |
| 142 | size_bytes -= SZ_1M; |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 143 | #endif |
| 144 | |
Stephen Warren | 3a2cab5 | 2014-12-23 10:34:50 -0700 | [diff] [blame] | 145 | return size_bytes; |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 146 | } |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 147 | #endif |
Marcel Ziswiler | 8c33ba7 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 148 | |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 149 | int dram_init(void) |
| 150 | { |
Thierry Reding | a0dbc13 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 151 | int err; |
| 152 | |
| 153 | /* try to initialize DRAM from cboot DTB first */ |
| 154 | err = cboot_dram_init(); |
| 155 | if (err == 0) |
| 156 | return 0; |
| 157 | |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 158 | #if IS_ENABLED(CONFIG_TEGRA_MC) |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 159 | /* We do not initialise DRAM here. We just query the size */ |
Simon Glass | 7f8c070 | 2011-11-05 03:56:57 +0000 | [diff] [blame] | 160 | gd->ram_size = query_sdram_size(); |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 161 | #endif |
| 162 | |
Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 163 | return 0; |
| 164 | } |
| 165 | |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 166 | #if IS_ENABLED(CONFIG_TEGRA_PINCTRL) |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 167 | static int uart_configs[] = { |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 168 | #if defined(CONFIG_TEGRA20) |
| 169 | #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 170 | FUNCMUX_UART1_UAA_UAB, |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 171 | #elif defined(CONFIG_TEGRA_UARTA_GPU) |
Stephen Warren | e21649b | 2012-05-16 05:59:59 +0000 | [diff] [blame] | 172 | FUNCMUX_UART1_GPU, |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 173 | #elif defined(CONFIG_TEGRA_UARTA_SDIO1) |
Lucas Stach | a2cfe63 | 2012-05-16 08:21:02 +0000 | [diff] [blame] | 174 | FUNCMUX_UART1_SDIO1, |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 175 | #else |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 176 | FUNCMUX_UART1_IRRX_IRTX, |
Stephen Warren | 4727a13 | 2013-01-22 06:20:08 +0000 | [diff] [blame] | 177 | #endif |
| 178 | FUNCMUX_UART2_UAD, |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 179 | -1, |
| 180 | FUNCMUX_UART4_GMC, |
| 181 | -1, |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 182 | #elif defined(CONFIG_TEGRA30) |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 183 | FUNCMUX_UART1_ULPI, /* UARTA */ |
| 184 | -1, |
| 185 | -1, |
| 186 | -1, |
| 187 | -1, |
Tom Warren | 2f5dac9 | 2014-01-24 12:46:16 -0700 | [diff] [blame] | 188 | #elif defined(CONFIG_TEGRA114) |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 189 | -1, |
| 190 | -1, |
| 191 | -1, |
| 192 | FUNCMUX_UART4_GMI, /* UARTD */ |
| 193 | -1, |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 194 | #elif defined(CONFIG_TEGRA124) |
Tom Warren | 2f5dac9 | 2014-01-24 12:46:16 -0700 | [diff] [blame] | 195 | FUNCMUX_UART1_KBC, /* UARTA */ |
| 196 | -1, |
| 197 | -1, |
| 198 | FUNCMUX_UART4_GPIO, /* UARTD */ |
| 199 | -1, |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 200 | #else /* Tegra210 */ |
| 201 | FUNCMUX_UART1_UART1, /* UARTA */ |
| 202 | -1, |
| 203 | -1, |
| 204 | FUNCMUX_UART4_UART4, /* UARTD */ |
| 205 | -1, |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 206 | #endif |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 207 | }; |
| 208 | |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 209 | /** |
| 210 | * Set up the specified uarts |
| 211 | * |
| 212 | * @param uarts_ids Mask containing UARTs to init (UARTx) |
| 213 | */ |
| 214 | static void setup_uarts(int uart_ids) |
| 215 | { |
| 216 | static enum periph_id id_for_uart[] = { |
| 217 | PERIPH_ID_UART1, |
| 218 | PERIPH_ID_UART2, |
| 219 | PERIPH_ID_UART3, |
| 220 | PERIPH_ID_UART4, |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 221 | PERIPH_ID_UART5, |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 222 | }; |
| 223 | size_t i; |
| 224 | |
| 225 | for (i = 0; i < UART_COUNT; i++) { |
| 226 | if (uart_ids & (1 << i)) { |
| 227 | enum periph_id id = id_for_uart[i]; |
| 228 | |
Stephen Warren | b9607e7 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 229 | funcmux_select(id, uart_configs[i]); |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 230 | clock_ll_start_uart(id); |
| 231 | } |
| 232 | } |
| 233 | } |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 234 | #endif |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 235 | |
| 236 | void board_init_uart_f(void) |
| 237 | { |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 238 | #if IS_ENABLED(CONFIG_TEGRA_PINCTRL) |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 239 | int uart_ids = 0; /* bit mask of which UART ids to enable */ |
| 240 | |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 241 | #ifdef CONFIG_TEGRA_ENABLE_UARTA |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 242 | uart_ids |= UARTA; |
| 243 | #endif |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 244 | #ifdef CONFIG_TEGRA_ENABLE_UARTB |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 245 | uart_ids |= UARTB; |
| 246 | #endif |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 247 | #ifdef CONFIG_TEGRA_ENABLE_UARTC |
| 248 | uart_ids |= UARTC; |
| 249 | #endif |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 250 | #ifdef CONFIG_TEGRA_ENABLE_UARTD |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 251 | uart_ids |= UARTD; |
| 252 | #endif |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 253 | #ifdef CONFIG_TEGRA_ENABLE_UARTE |
| 254 | uart_ids |= UARTE; |
| 255 | #endif |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 256 | setup_uarts(uart_ids); |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 257 | #endif |
Simon Glass | bb6997f | 2011-11-28 15:04:39 +0000 | [diff] [blame] | 258 | } |
Simon Glass | bd29cb0 | 2012-01-09 13:22:15 +0000 | [diff] [blame] | 259 | |
Simon Glass | 878a3ed | 2015-12-04 08:58:39 -0700 | [diff] [blame] | 260 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 261 | static struct ns16550_plat ns16550_com1_pdata = { |
Tom Rini | 9109213 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 262 | .base = CFG_SYS_NS16550_COM1, |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 263 | .reg_shift = 2, |
Tom Rini | 9109213 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 264 | .clock = CFG_SYS_NS16550_CLK, |
Heiko Schocher | 17fa032 | 2017-01-18 08:05:49 +0100 | [diff] [blame] | 265 | .fcr = UART_FCR_DEFVAL, |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 266 | }; |
| 267 | |
Simon Glass | 20e442a | 2020-12-28 20:34:54 -0700 | [diff] [blame] | 268 | U_BOOT_DRVINFO(ns16550_com1) = { |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 269 | "ns16550_serial", &ns16550_com1_pdata |
| 270 | }; |
| 271 | #endif |
| 272 | |
Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 273 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) |
Simon Glass | bd29cb0 | 2012-01-09 13:22:15 +0000 | [diff] [blame] | 274 | void enable_caches(void) |
| 275 | { |
| 276 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 277 | dcache_enable(); |
| 278 | } |
| 279 | #endif |