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Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +02001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +02006 */
7
8#include <common.h>
9#include <asm/system.h>
R Sricharan96fdbec2013-03-04 20:04:44 +000010#include <asm/cache.h>
11#include <linux/compiler.h>
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020012
Aneesh Ve47f2db2011-06-16 23:30:48 +000013#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
Heiko Schocher880eff52010-09-17 13:10:29 +020014
Heiko Schocher880eff52010-09-17 13:10:29 +020015DECLARE_GLOBAL_DATA_PTR;
16
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020017__weak void arm_init_before_mmu(void)
Aneesh Vc2dd0d42011-06-16 23:30:49 +000018{
19}
Aneesh Vc2dd0d42011-06-16 23:30:49 +000020
R Sricharande63ac22013-03-04 20:04:45 +000021__weak void arm_init_domains(void)
22{
23}
24
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020025static void cp_delay (void)
26{
27 volatile int i;
28
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
31 nop();
Heiko Schocher880eff52010-09-17 13:10:29 +020032 asm volatile("" : : : "memory");
33}
34
Simon Glass0dde7f52012-10-17 13:24:53 +000035void set_section_dcache(int section, enum dcache_option option)
Heiko Schocherf1d2b312010-09-17 13:10:39 +020036{
Simon Glass34fd5d22012-12-13 20:48:39 +000037 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Simon Glass0dde7f52012-10-17 13:24:53 +000038 u32 value;
39
40 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
41 value |= option;
42 page_table[section] = value;
43}
44
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020045__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
Simon Glass0dde7f52012-10-17 13:24:53 +000046{
47 debug("%s: Warning: not implemented\n", __func__);
48}
49
Thierry Reding25026fa2014-08-26 17:34:21 +020050void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
Simon Glass0dde7f52012-10-17 13:24:53 +000051 enum dcache_option option)
52{
Simon Glass34fd5d22012-12-13 20:48:39 +000053 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Thierry Reding25026fa2014-08-26 17:34:21 +020054 unsigned long upto, end;
Simon Glass0dde7f52012-10-17 13:24:53 +000055
56 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
57 start = start >> MMU_SECTION_SHIFT;
Thierry Reding25026fa2014-08-26 17:34:21 +020058 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
Simon Glass0dde7f52012-10-17 13:24:53 +000059 option);
60 for (upto = start; upto < end; upto++)
61 set_section_dcache(upto, option);
62 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
63}
64
R Sricharan96fdbec2013-03-04 20:04:44 +000065__weak void dram_bank_mmu_setup(int bank)
Simon Glass0dde7f52012-10-17 13:24:53 +000066{
Heiko Schocherf1d2b312010-09-17 13:10:39 +020067 bd_t *bd = gd->bd;
68 int i;
69
70 debug("%s: bank: %d\n", __func__, bank);
71 for (i = bd->bi_dram[bank].start >> 20;
Marek Vasut221a49d2014-08-04 01:45:46 +020072 i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
Heiko Schocherf1d2b312010-09-17 13:10:39 +020073 i++) {
Simon Glass0dde7f52012-10-17 13:24:53 +000074#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
75 set_section_dcache(i, DCACHE_WRITETHROUGH);
Marek Vasutff7e9702014-09-15 02:44:36 +020076#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
77 set_section_dcache(i, DCACHE_WRITEALLOC);
Simon Glass0dde7f52012-10-17 13:24:53 +000078#else
79 set_section_dcache(i, DCACHE_WRITEBACK);
80#endif
Heiko Schocherf1d2b312010-09-17 13:10:39 +020081 }
82}
Heiko Schocherf1d2b312010-09-17 13:10:39 +020083
84/* to activate the MMU we need to set up virtual memory: use 1M areas */
Heiko Schocher880eff52010-09-17 13:10:29 +020085static inline void mmu_setup(void)
86{
Heiko Schocherf1d2b312010-09-17 13:10:39 +020087 int i;
Heiko Schocher880eff52010-09-17 13:10:29 +020088 u32 reg;
89
Aneesh Vc2dd0d42011-06-16 23:30:49 +000090 arm_init_before_mmu();
Heiko Schocher880eff52010-09-17 13:10:29 +020091 /* Set up an identity-mapping for all 4GB, rw for everyone */
92 for (i = 0; i < 4096; i++)
Simon Glass0dde7f52012-10-17 13:24:53 +000093 set_section_dcache(i, DCACHE_OFF);
Heiko Schocherf1d2b312010-09-17 13:10:39 +020094
Heiko Schocherf1d2b312010-09-17 13:10:39 +020095 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
96 dram_bank_mmu_setup(i);
97 }
Heiko Schocher880eff52010-09-17 13:10:29 +020098
99 /* Copy the page table address to cp15 */
100 asm volatile("mcr p15, 0, %0, c2, c0, 0"
Simon Glass34fd5d22012-12-13 20:48:39 +0000101 : : "r" (gd->arch.tlb_addr) : "memory");
Heiko Schocher880eff52010-09-17 13:10:29 +0200102 /* Set the access control to all-supervisor */
103 asm volatile("mcr p15, 0, %0, c3, c0, 0"
104 : : "r" (~0));
R Sricharande63ac22013-03-04 20:04:45 +0000105
106 arm_init_domains();
107
Heiko Schocher880eff52010-09-17 13:10:29 +0200108 /* and enable the mmu */
109 reg = get_cr(); /* get control reg. */
110 cp_delay();
111 set_cr(reg | CR_M);
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200112}
113
Aneesh Ve05f0072011-06-16 23:30:50 +0000114static int mmu_enabled(void)
115{
116 return get_cr() & CR_M;
117}
118
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200119/* cache_bit must be either CR_I or CR_C */
120static void cache_enable(uint32_t cache_bit)
121{
122 uint32_t reg;
123
Heiko Schocher880eff52010-09-17 13:10:29 +0200124 /* The data cache is not active unless the mmu is enabled too */
Aneesh Ve05f0072011-06-16 23:30:50 +0000125 if ((cache_bit == CR_C) && !mmu_enabled())
Heiko Schocher880eff52010-09-17 13:10:29 +0200126 mmu_setup();
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200127 reg = get_cr(); /* get control reg. */
128 cp_delay();
129 set_cr(reg | cache_bit);
130}
131
132/* cache_bit must be either CR_I or CR_C */
133static void cache_disable(uint32_t cache_bit)
134{
135 uint32_t reg;
136
SRICHARAN Rd702b082012-05-16 23:52:54 +0000137 reg = get_cr();
138 cp_delay();
139
Heiko Schocher880eff52010-09-17 13:10:29 +0200140 if (cache_bit == CR_C) {
Heiko Schocherf1d2b312010-09-17 13:10:39 +0200141 /* if cache isn;t enabled no need to disable */
Heiko Schocherf1d2b312010-09-17 13:10:39 +0200142 if ((reg & CR_C) != CR_C)
143 return;
Heiko Schocher880eff52010-09-17 13:10:29 +0200144 /* if disabling data cache, disable mmu too */
145 cache_bit |= CR_M;
Heiko Schocher880eff52010-09-17 13:10:29 +0200146 }
Arun Mankuzhi44df5e82012-11-30 13:01:14 +0000147 reg = get_cr();
148 cp_delay();
149 if (cache_bit == (CR_C | CR_M))
150 flush_dcache_all();
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200151 set_cr(reg & ~cache_bit);
152}
153#endif
154
Aneesh Ve47f2db2011-06-16 23:30:48 +0000155#ifdef CONFIG_SYS_ICACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200156void icache_enable (void)
157{
158 return;
159}
160
161void icache_disable (void)
162{
163 return;
164}
165
166int icache_status (void)
167{
168 return 0; /* always off */
169}
170#else
171void icache_enable(void)
172{
173 cache_enable(CR_I);
174}
175
176void icache_disable(void)
177{
178 cache_disable(CR_I);
179}
180
181int icache_status(void)
182{
183 return (get_cr() & CR_I) != 0;
184}
185#endif
186
Aneesh Ve47f2db2011-06-16 23:30:48 +0000187#ifdef CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200188void dcache_enable (void)
189{
190 return;
191}
192
193void dcache_disable (void)
194{
195 return;
196}
197
198int dcache_status (void)
199{
200 return 0; /* always off */
201}
202#else
203void dcache_enable(void)
204{
205 cache_enable(CR_C);
206}
207
208void dcache_disable(void)
209{
210 cache_disable(CR_C);
211}
212
213int dcache_status(void)
214{
215 return (get_cr() & CR_C) != 0;
216}
217#endif