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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergera26cd042015-05-12 14:46:23 -050021 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022
Ian Campbellc3be2792014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020038 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020039 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010040
Ian Campbellc3be2792014-10-24 21:20:45 +010041config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 bool "sun7i (Allwinner A20)"
43 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010044 select CPU_V7_HAS_NONSEC
45 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020046 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010047 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020048 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010049
Hans de Goede5e6bacd2015-04-06 20:55:39 +020050config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010051 bool "sun8i (Allwinner A23)"
52 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010054 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010055
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053056config MACH_SUN8I_A33
57 bool "sun8i (Allwinner A33)"
58 select CPU_V7
59 select SUNXI_GEN_SUN6I
60 select SUPPORT_SPL
61
Hans de Goede1871a8c2015-01-13 19:25:06 +010062config MACH_SUN9I
63 bool "sun9i (Allwinner A80)"
64 select CPU_V7
65 select SUNXI_GEN_SUN6I
66
Ian Campbell2c7e3b92014-10-24 21:20:44 +010067endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080068
Hans de Goede5e6bacd2015-04-06 20:55:39 +020069# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
70config MACH_SUN8I
71 bool
72 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
73
74
Hans de Goede37781a12014-11-15 19:46:39 +010075config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010076 int "sunxi dram clock speed"
77 default 312 if MACH_SUN6I || MACH_SUN8I
78 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010079 ---help---
80 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +010081 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +010082
Siarhei Siamashka47e35012015-02-01 00:27:06 +020083if MACH_SUN5I || MACH_SUN7I
84config DRAM_MBUS_CLK
85 int "sunxi mbus clock speed"
86 default 300
87 ---help---
88 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
89
90endif
91
Hans de Goede37781a12014-11-15 19:46:39 +010092config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +010093 int "sunxi dram zq value"
94 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
95 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010096 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010097 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +010098
Hans de Goede8975cdf2015-05-13 15:00:46 +020099config DRAM_ODT_EN
100 bool "sunxi dram odt enable"
101 default n if !MACH_SUN8I_A23
102 default y if MACH_SUN8I_A23
103 ---help---
104 Select this to enable dram odt (on die termination).
105
Hans de Goede8ffc4872015-01-17 14:24:55 +0100106if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
107config DRAM_EMR1
108 int "sunxi dram emr1 value"
109 default 0 if MACH_SUN4I
110 default 4 if MACH_SUN5I || MACH_SUN7I
111 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100112 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200113
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200114config DRAM_TPR3
115 hex "sunxi dram tpr3 value"
116 default 0
117 ---help---
118 Set the dram controller tpr3 parameter. This parameter configures
119 the delay on the command lane and also phase shifts, which are
120 applied for sampling incoming read data. The default value 0
121 means that no phase/delay adjustments are necessary. Properly
122 configuring this parameter increases reliability at high DRAM
123 clock speeds.
124
125config DRAM_DQS_GATING_DELAY
126 hex "sunxi dram dqs_gating_delay value"
127 default 0
128 ---help---
129 Set the dram controller dqs_gating_delay parmeter. Each byte
130 encodes the DQS gating delay for each byte lane. The delay
131 granularity is 1/4 cycle. For example, the value 0x05060606
132 means that the delay is 5 quarter-cycles for one lane (1.25
133 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
134 The default value 0 means autodetection. The results of hardware
135 autodetection are not very reliable and depend on the chip
136 temperature (sometimes producing different results on cold start
137 and warm reboot). But the accuracy of hardware autodetection
138 is usually good enough, unless running at really high DRAM
139 clocks speeds (up to 600MHz). If unsure, keep as 0.
140
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200141choice
142 prompt "sunxi dram timings"
143 default DRAM_TIMINGS_VENDOR_MAGIC
144 ---help---
145 Select the timings of the DDR3 chips.
146
147config DRAM_TIMINGS_VENDOR_MAGIC
148 bool "Magic vendor timings from Android"
149 ---help---
150 The same DRAM timings as in the Allwinner boot0 bootloader.
151
152config DRAM_TIMINGS_DDR3_1066F_1333H
153 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
154 ---help---
155 Use the timings of the standard JEDEC DDR3-1066F speed bin for
156 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
157 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
158 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
159 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
160 that down binning to DDR3-1066F is supported (because DDR3-1066F
161 uses a bit faster timings than DDR3-1333H).
162
163config DRAM_TIMINGS_DDR3_800E_1066G_1333J
164 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
165 ---help---
166 Use the timings of the slowest possible JEDEC speed bin for the
167 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
168 DDR3-800E, DDR3-1066G or DDR3-1333J.
169
170endchoice
171
Hans de Goede37781a12014-11-15 19:46:39 +0100172endif
173
Hans de Goede8975cdf2015-05-13 15:00:46 +0200174if MACH_SUN8I_A23
175config DRAM_ODT_CORRECTION
176 int "sunxi dram odt correction value"
177 default 0
178 ---help---
179 Set the dram odt correction value (range -255 - 255). In allwinner
180 fex files, this option is found in bits 8-15 of the u32 odt_en variable
181 in the [dram] section. When bit 31 of the odt_en variable is set
182 then the correction is negative. Usually the value for this is 0.
183endif
184
Iain Patone71b4222015-03-28 10:26:38 +0000185config SYS_CLK_FREQ
186 default 912000000 if MACH_SUN7I
187 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
188
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800189config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100190 default "sun4i" if MACH_SUN4I
191 default "sun5i" if MACH_SUN5I
192 default "sun6i" if MACH_SUN6I
193 default "sun7i" if MACH_SUN7I
194 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100195 default "sun9i" if MACH_SUN9I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200196
Masahiro Yamadadd840582014-07-30 14:08:14 +0900197config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900198 default "sunxi"
199
200config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900201 default "sunxi"
202
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200203config UART0_PORT_F
204 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200205 default n
206 ---help---
207 Repurpose the SD card slot for getting access to the UART0 serial
208 console. Primarily useful only for low level u-boot debugging on
209 tablets, where normal UART0 is difficult to access and requires
210 device disassembly and/or soldering. As the SD card can't be used
211 at the same time, the system can be only booted in the FEL mode.
212 Only enable this if you really know what you are doing.
213
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200214config OLD_SUNXI_KERNEL_COMPAT
215 boolean "Enable workarounds for booting old kernels"
216 default n
217 ---help---
218 Set this to enable various workarounds for old kernels, this results in
219 sub-optimal settings for newer kernels, only enable if needed.
220
Hans de Goedecd821132014-10-02 20:29:26 +0200221config MMC0_CD_PIN
222 string "Card detect pin for mmc0"
223 default ""
224 ---help---
225 Set the card detect pin for mmc0, leave empty to not use cd. This
226 takes a string in the format understood by sunxi_name_to_gpio, e.g.
227 PH1 for pin 1 of port H.
228
229config MMC1_CD_PIN
230 string "Card detect pin for mmc1"
231 default ""
232 ---help---
233 See MMC0_CD_PIN help text.
234
235config MMC2_CD_PIN
236 string "Card detect pin for mmc2"
237 default ""
238 ---help---
239 See MMC0_CD_PIN help text.
240
241config MMC3_CD_PIN
242 string "Card detect pin for mmc3"
243 default ""
244 ---help---
245 See MMC0_CD_PIN help text.
246
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100247config MMC1_PINS
248 string "Pins for mmc1"
249 default ""
250 ---help---
251 Set the pins used for mmc1, when applicable. This takes a string in the
252 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
253
254config MMC2_PINS
255 string "Pins for mmc2"
256 default ""
257 ---help---
258 See MMC1_PINS help text.
259
260config MMC3_PINS
261 string "Pins for mmc3"
262 default ""
263 ---help---
264 See MMC1_PINS help text.
265
Hans de Goede2ccfac02014-10-02 20:43:50 +0200266config MMC_SUNXI_SLOT_EXTRA
267 int "mmc extra slot number"
268 default -1
269 ---help---
270 sunxi builds always enable mmc0, some boards also have a second sdcard
271 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
272 support for this.
273
Hans de Goede4458b7a2015-01-07 15:26:06 +0100274config USB0_VBUS_PIN
275 string "Vbus enable pin for usb0 (otg)"
276 default ""
277 ---help---
278 Set the Vbus enable pin for usb0 (otg). This takes a string in the
279 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
280
Hans de Goede52defe82015-02-16 22:13:43 +0100281config USB0_VBUS_DET
282 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100283 default ""
284 ---help---
285 Set the Vbus detect pin for usb0 (otg). This takes a string in the
286 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
287
Hans de Goede115200c2014-11-07 16:09:00 +0100288config USB1_VBUS_PIN
289 string "Vbus enable pin for usb1 (ehci0)"
290 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100291 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100292 ---help---
293 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
294 a string in the format understood by sunxi_name_to_gpio, e.g.
295 PH1 for pin 1 of port H.
296
297config USB2_VBUS_PIN
298 string "Vbus enable pin for usb2 (ehci1)"
299 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100300 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100301 ---help---
302 See USB1_VBUS_PIN help text.
303
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200304config I2C0_ENABLE
305 bool "Enable I2C/TWI controller 0"
306 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
307 default n if MACH_SUN6I || MACH_SUN8I
308 ---help---
309 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
310 its clock and setting up the bus. This is especially useful on devices
311 with slaves connected to the bus or with pins exposed through e.g. an
312 expansion port/header.
313
314config I2C1_ENABLE
315 bool "Enable I2C/TWI controller 1"
316 default n
317 ---help---
318 See I2C0_ENABLE help text.
319
320config I2C2_ENABLE
321 bool "Enable I2C/TWI controller 2"
322 default n
323 ---help---
324 See I2C0_ENABLE help text.
325
326if MACH_SUN6I || MACH_SUN7I
327config I2C3_ENABLE
328 bool "Enable I2C/TWI controller 3"
329 default n
330 ---help---
331 See I2C0_ENABLE help text.
332endif
333
334if MACH_SUN7I
335config I2C4_ENABLE
336 bool "Enable I2C/TWI controller 4"
337 default n
338 ---help---
339 See I2C0_ENABLE help text.
340endif
341
Hans de Goede2fcf0332015-04-25 17:25:14 +0200342config AXP_GPIO
343 boolean "Enable support for gpio-s on axp PMICs"
344 default n
345 ---help---
346 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
347
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200348config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100349 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200350 default y
351 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100352 Say Y here to add support for using a cfb console on the HDMI, LCD
353 or VGA output found on most sunxi devices. See doc/README.video for
354 info on how to select the video output and mode.
355
Hans de Goede2fbf0912014-12-23 23:04:35 +0100356config VIDEO_HDMI
357 boolean "HDMI output support"
358 depends on VIDEO && !MACH_SUN8I
359 default y
360 ---help---
361 Say Y here to add support for outputting video over HDMI.
362
Hans de Goeded9786d22014-12-25 13:58:06 +0100363config VIDEO_VGA
364 boolean "VGA output support"
365 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
366 default n
367 ---help---
368 Say Y here to add support for outputting video over VGA.
369
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100370config VIDEO_VGA_VIA_LCD
371 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800372 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100373 default n
374 ---help---
375 Say Y here to add support for external DACs connected to the parallel
376 LCD interface driving a VGA connector, such as found on the
377 Olimex A13 boards.
378
Hans de Goedefb75d972015-01-25 15:33:07 +0100379config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
380 boolean "Force sync active high for VGA via LCD controller support"
381 depends on VIDEO_VGA_VIA_LCD
382 default n
383 ---help---
384 Say Y here if you've a board which uses opendrain drivers for the vga
385 hsync and vsync signals. Opendrain drivers cannot generate steep enough
386 positive edges for a stable video output, so on boards with opendrain
387 drivers the sync signals must always be active high.
388
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800389config VIDEO_VGA_EXTERNAL_DAC_EN
390 string "LCD panel power enable pin"
391 depends on VIDEO_VGA_VIA_LCD
392 default ""
393 ---help---
394 Set the enable pin for the external VGA DAC. This takes a string in the
395 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
396
Hans de Goede2dae8002014-12-21 16:28:32 +0100397config VIDEO_LCD_MODE
398 string "LCD panel timing details"
399 depends on VIDEO
400 default ""
401 ---help---
402 LCD panel timing details string, leave empty if there is no LCD panel.
403 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
404 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
405
Hans de Goede65150322015-01-13 13:21:46 +0100406config VIDEO_LCD_DCLK_PHASE
407 int "LCD panel display clock phase"
408 depends on VIDEO
409 default 1
410 ---help---
411 Select LCD panel display clock phase shift, range 0-3.
412
Hans de Goede2dae8002014-12-21 16:28:32 +0100413config VIDEO_LCD_POWER
414 string "LCD panel power enable pin"
415 depends on VIDEO
416 default ""
417 ---help---
418 Set the power enable pin for the LCD panel. This takes a string in the
419 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
420
Hans de Goede242e3d82015-02-16 17:26:41 +0100421config VIDEO_LCD_RESET
422 string "LCD panel reset pin"
423 depends on VIDEO
424 default ""
425 ---help---
426 Set the reset pin for the LCD panel. This takes a string in the format
427 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
428
Hans de Goede2dae8002014-12-21 16:28:32 +0100429config VIDEO_LCD_BL_EN
430 string "LCD panel backlight enable pin"
431 depends on VIDEO
432 default ""
433 ---help---
434 Set the backlight enable pin for the LCD panel. This takes a string in the
435 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
436 port H.
437
438config VIDEO_LCD_BL_PWM
439 string "LCD panel backlight pwm pin"
440 depends on VIDEO
441 default ""
442 ---help---
443 Set the backlight pwm pin for the LCD panel. This takes a string in the
444 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200445
Hans de Goedea7403ae2015-01-22 21:02:42 +0100446config VIDEO_LCD_BL_PWM_ACTIVE_LOW
447 bool "LCD panel backlight pwm is inverted"
448 depends on VIDEO
449 default y
450 ---help---
451 Set this if the backlight pwm output is active low.
452
Hans de Goede55410082015-02-16 17:23:25 +0100453config VIDEO_LCD_PANEL_I2C
454 bool "LCD panel needs to be configured via i2c"
455 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100456 default n
Hans de Goede55410082015-02-16 17:23:25 +0100457 ---help---
458 Say y here if the LCD panel needs to be configured via i2c. This
459 will add a bitbang i2c controller using gpios to talk to the LCD.
460
461config VIDEO_LCD_PANEL_I2C_SDA
462 string "LCD panel i2c interface SDA pin"
463 depends on VIDEO_LCD_PANEL_I2C
464 default "PG12"
465 ---help---
466 Set the SDA pin for the LCD i2c interface. This takes a string in the
467 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
468
469config VIDEO_LCD_PANEL_I2C_SCL
470 string "LCD panel i2c interface SCL pin"
471 depends on VIDEO_LCD_PANEL_I2C
472 default "PG10"
473 ---help---
474 Set the SCL pin for the LCD i2c interface. This takes a string in the
475 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
476
Hans de Goede213480e2015-01-01 22:04:34 +0100477
478# Note only one of these may be selected at a time! But hidden choices are
479# not supported by Kconfig
480config VIDEO_LCD_IF_PARALLEL
481 bool
482
483config VIDEO_LCD_IF_LVDS
484 bool
485
486
487choice
488 prompt "LCD panel support"
489 depends on VIDEO
490 ---help---
491 Select which type of LCD panel to support.
492
493config VIDEO_LCD_PANEL_PARALLEL
494 bool "Generic parallel interface LCD panel"
495 select VIDEO_LCD_IF_PARALLEL
496
497config VIDEO_LCD_PANEL_LVDS
498 bool "Generic lvds interface LCD panel"
499 select VIDEO_LCD_IF_LVDS
500
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200501config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
502 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
503 select VIDEO_LCD_SSD2828
504 select VIDEO_LCD_IF_PARALLEL
505 ---help---
506 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
507
Hans de Goede27515b22015-01-20 09:23:36 +0100508config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
509 bool "Hitachi tx18d42vm LCD panel"
510 select VIDEO_LCD_HITACHI_TX18D42VM
511 select VIDEO_LCD_IF_LVDS
512 ---help---
513 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
514
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100515config VIDEO_LCD_TL059WV5C0
516 bool "tl059wv5c0 LCD panel"
517 select VIDEO_LCD_PANEL_I2C
518 select VIDEO_LCD_IF_PARALLEL
519 ---help---
520 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
521 Aigo M60/M608/M606 tablets.
522
Hans de Goede213480e2015-01-01 22:04:34 +0100523endchoice
524
525
Hans de Goede1a800f72015-01-11 17:17:00 +0100526config USB_MUSB_SUNXI
527 bool "Enable sunxi OTG / DRC USB controller in host mode"
528 default n
529 ---help---
530 Say y here to enable support for the sunxi OTG / DRC USB controller
531 used on almost all sunxi boards. Note currently u-boot can only have
532 one usb host controller enabled at a time, so enabling this on boards
533 which also use the ehci host controller will result in build errors.
534
Hans de Goede86b49092014-09-18 21:03:34 +0200535config USB_KEYBOARD
536 boolean "Enable USB keyboard support"
537 default y
538 ---help---
539 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede2dae8002014-12-21 16:28:32 +0100540 in combination with a graphical console).
Hans de Goede86b49092014-09-18 21:03:34 +0200541
Hans de Goedec13f60d2015-01-25 12:10:48 +0100542config GMAC_TX_DELAY
543 int "GMAC Transmit Clock Delay Chain"
544 default 0
545 ---help---
546 Set the GMAC Transmit Clock Delay Chain value.
547
Hans de Goedef9b08fb2015-05-05 12:49:36 +0200548config SYS_MALLOC_CLEAR_ON_INIT
549 default n
550
Hans de Goedeb6006ba2015-04-15 20:46:48 +0200551config NET
552 default y
553
554config NETDEVICES
555 default y
556
557config DM_ETH
558 default y
559
560config DM_SERIAL
561 default y
562
Hans de Goede8d837a12015-05-10 14:10:26 +0200563config DM_USB
564 default y if !USB_MUSB_SUNXI
565
Masahiro Yamadadd840582014-07-30 14:08:14 +0900566endif