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Lei Wenaf62a552011-06-28 21:50:06 +00001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00006 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10
11#include <common.h>
12#include <malloc.h>
13#include <mmc.h>
14#include <sdhci.h>
15
16void *aligned_buffer;
17
18static void sdhci_reset(struct sdhci_host *host, u8 mask)
19{
20 unsigned long timeout;
21
22 /* Wait max 100 ms */
23 timeout = 100;
24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
26 if (timeout == 0) {
27 printf("Reset 0x%x never completed.\n", (int)mask);
28 return;
29 }
30 timeout--;
31 udelay(1000);
32 }
33}
34
35static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
36{
37 int i;
38 if (cmd->resp_type & MMC_RSP_136) {
39 /* CRC is stripped so we need to do some shifting. */
40 for (i = 0; i < 4; i++) {
41 cmd->response[i] = sdhci_readl(host,
42 SDHCI_RESPONSE + (3-i)*4) << 8;
43 if (i != 3)
44 cmd->response[i] |= sdhci_readb(host,
45 SDHCI_RESPONSE + (3-i)*4-1);
46 }
47 } else {
48 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
49 }
50}
51
52static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
53{
54 int i;
55 char *offs;
56 for (i = 0; i < data->blocksize; i += 4) {
57 offs = data->dest + i;
58 if (data->flags == MMC_DATA_READ)
59 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
60 else
61 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
62 }
63}
64
65static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
66 unsigned int start_addr)
67{
Lei Wena004abd2011-10-08 04:14:57 +000068 unsigned int stat, rdy, mask, timeout, block = 0;
Jaehoon Chung804c7f42012-09-20 20:31:55 +000069#ifdef CONFIG_MMC_SDMA
70 unsigned char ctrl;
71 ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
72 ctrl &= ~SDHCI_CTRL_DMA_MASK;
73 ctrl |= SDHCI_CTRL_SDMA;
74 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
75#endif
Lei Wenaf62a552011-06-28 21:50:06 +000076
Jaehoon Chung5d48e422012-09-20 20:31:54 +000077 timeout = 1000000;
Lei Wenaf62a552011-06-28 21:50:06 +000078 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
79 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
80 do {
81 stat = sdhci_readl(host, SDHCI_INT_STATUS);
82 if (stat & SDHCI_INT_ERROR) {
83 printf("Error detected in status(0x%X)!\n", stat);
84 return -1;
85 }
86 if (stat & rdy) {
87 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
88 continue;
89 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
90 sdhci_transfer_pio(host, data);
91 data->dest += data->blocksize;
92 if (++block >= data->blocks)
93 break;
94 }
95#ifdef CONFIG_MMC_SDMA
96 if (stat & SDHCI_INT_DMA_END) {
97 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Lei Wen3e81c772011-10-08 04:14:58 +000098 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
Lei Wenaf62a552011-06-28 21:50:06 +000099 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
100 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
101 }
102#endif
Lei Wena004abd2011-10-08 04:14:57 +0000103 if (timeout-- > 0)
104 udelay(10);
105 else {
106 printf("Transfer data timeout\n");
107 return -1;
108 }
Lei Wenaf62a552011-06-28 21:50:06 +0000109 } while (!(stat & SDHCI_INT_DATA_END));
110 return 0;
111}
112
113int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
114 struct mmc_data *data)
115{
116 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
117 unsigned int stat = 0;
118 int ret = 0;
119 int trans_bytes = 0, is_aligned = 1;
120 u32 mask, flags, mode;
121 unsigned int timeout, start_addr = 0;
Jaehoon Chung3a638322012-04-23 02:36:25 +0000122 unsigned int retry = 10000;
Lei Wenaf62a552011-06-28 21:50:06 +0000123
124 /* Wait max 10 ms */
125 timeout = 10;
126
127 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
128 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
129
130 /* We shouldn't wait for data inihibit for stop commands, even
131 though they might use busy signaling */
132 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
133 mask &= ~SDHCI_DATA_INHIBIT;
134
135 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
136 if (timeout == 0) {
137 printf("Controller never released inhibit bit(s).\n");
138 return COMM_ERR;
139 }
140 timeout--;
141 udelay(1000);
142 }
143
144 mask = SDHCI_INT_RESPONSE;
145 if (!(cmd->resp_type & MMC_RSP_PRESENT))
146 flags = SDHCI_CMD_RESP_NONE;
147 else if (cmd->resp_type & MMC_RSP_136)
148 flags = SDHCI_CMD_RESP_LONG;
149 else if (cmd->resp_type & MMC_RSP_BUSY) {
150 flags = SDHCI_CMD_RESP_SHORT_BUSY;
151 mask |= SDHCI_INT_DATA_END;
152 } else
153 flags = SDHCI_CMD_RESP_SHORT;
154
155 if (cmd->resp_type & MMC_RSP_CRC)
156 flags |= SDHCI_CMD_CRC;
157 if (cmd->resp_type & MMC_RSP_OPCODE)
158 flags |= SDHCI_CMD_INDEX;
159 if (data)
160 flags |= SDHCI_CMD_DATA;
161
162 /*Set Transfer mode regarding to data flag*/
163 if (data != 0) {
164 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
165 mode = SDHCI_TRNS_BLK_CNT_EN;
166 trans_bytes = data->blocks * data->blocksize;
167 if (data->blocks > 1)
168 mode |= SDHCI_TRNS_MULTI;
169
170 if (data->flags == MMC_DATA_READ)
171 mode |= SDHCI_TRNS_READ;
172
173#ifdef CONFIG_MMC_SDMA
174 if (data->flags == MMC_DATA_READ)
175 start_addr = (unsigned int)data->dest;
176 else
177 start_addr = (unsigned int)data->src;
178 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
179 (start_addr & 0x7) != 0x0) {
180 is_aligned = 0;
181 start_addr = (unsigned int)aligned_buffer;
182 if (data->flags != MMC_DATA_READ)
183 memcpy(aligned_buffer, data->src, trans_bytes);
184 }
185
186 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
187 mode |= SDHCI_TRNS_DMA;
188#endif
189 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
190 data->blocksize),
191 SDHCI_BLOCK_SIZE);
192 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
193 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
194 }
195
196 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
197#ifdef CONFIG_MMC_SDMA
Lei Wen2c2ec4c2011-10-08 04:14:54 +0000198 flush_cache(start_addr, trans_bytes);
Lei Wenaf62a552011-06-28 21:50:06 +0000199#endif
200 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
201 do {
202 stat = sdhci_readl(host, SDHCI_INT_STATUS);
203 if (stat & SDHCI_INT_ERROR)
204 break;
Jaehoon Chung3a638322012-04-23 02:36:25 +0000205 if (--retry == 0)
206 break;
Lei Wenaf62a552011-06-28 21:50:06 +0000207 } while ((stat & mask) != mask);
208
Jaehoon Chung3a638322012-04-23 02:36:25 +0000209 if (retry == 0) {
210 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
211 return 0;
212 else {
213 printf("Timeout for status update!\n");
214 return TIMEOUT;
215 }
216 }
217
Lei Wenaf62a552011-06-28 21:50:06 +0000218 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
219 sdhci_cmd_done(host, cmd);
220 sdhci_writel(host, mask, SDHCI_INT_STATUS);
221 } else
222 ret = -1;
223
224 if (!ret && data)
225 ret = sdhci_transfer_data(host, data, start_addr);
226
Tushar Behera13243f22012-09-20 20:31:57 +0000227 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
228 udelay(1000);
229
Lei Wenaf62a552011-06-28 21:50:06 +0000230 stat = sdhci_readl(host, SDHCI_INT_STATUS);
231 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
232 if (!ret) {
233 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
234 !is_aligned && (data->flags == MMC_DATA_READ))
235 memcpy(data->dest, aligned_buffer, trans_bytes);
236 return 0;
237 }
238
239 sdhci_reset(host, SDHCI_RESET_CMD);
240 sdhci_reset(host, SDHCI_RESET_DATA);
241 if (stat & SDHCI_INT_TIMEOUT)
242 return TIMEOUT;
243 else
244 return COMM_ERR;
245}
246
247static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
248{
249 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
250 unsigned int div, clk, timeout;
251
252 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
253
254 if (clock == 0)
255 return 0;
256
Joe Hershberger073cfd12012-08-17 10:18:54 +0000257 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
Lei Wenaf62a552011-06-28 21:50:06 +0000258 /* Version 3.00 divisors must be a multiple of 2. */
259 if (mmc->f_max <= clock)
260 div = 1;
261 else {
262 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
263 if ((mmc->f_max / div) <= clock)
264 break;
265 }
266 }
267 } else {
268 /* Version 2.00 divisors must be a power of 2. */
269 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
270 if ((mmc->f_max / div) <= clock)
271 break;
272 }
273 }
274 div >>= 1;
275
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000276 if (host->set_clock)
277 host->set_clock(host->index, div);
278
Lei Wenaf62a552011-06-28 21:50:06 +0000279 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
280 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
281 << SDHCI_DIVIDER_HI_SHIFT;
282 clk |= SDHCI_CLOCK_INT_EN;
283 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
284
285 /* Wait max 20 ms */
286 timeout = 20;
287 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
288 & SDHCI_CLOCK_INT_STABLE)) {
289 if (timeout == 0) {
290 printf("Internal clock never stabilised.\n");
291 return -1;
292 }
293 timeout--;
294 udelay(1000);
295 }
296
297 clk |= SDHCI_CLOCK_CARD_EN;
298 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
299 return 0;
300}
301
302static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
303{
304 u8 pwr = 0;
305
306 if (power != (unsigned short)-1) {
307 switch (1 << power) {
308 case MMC_VDD_165_195:
309 pwr = SDHCI_POWER_180;
310 break;
311 case MMC_VDD_29_30:
312 case MMC_VDD_30_31:
313 pwr = SDHCI_POWER_300;
314 break;
315 case MMC_VDD_32_33:
316 case MMC_VDD_33_34:
317 pwr = SDHCI_POWER_330;
318 break;
319 }
320 }
321
322 if (pwr == 0) {
323 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
324 return;
325 }
326
Mela Custodio688c2d12012-11-03 17:40:16 +0000327 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
328 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
329
Lei Wenaf62a552011-06-28 21:50:06 +0000330 pwr |= SDHCI_POWER_ON;
331
332 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
333}
334
335void sdhci_set_ios(struct mmc *mmc)
336{
337 u32 ctrl;
338 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
339
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000340 if (host->set_control_reg)
341 host->set_control_reg(host);
342
Lei Wenaf62a552011-06-28 21:50:06 +0000343 if (mmc->clock != host->clock)
344 sdhci_set_clock(mmc, mmc->clock);
345
346 /* Set bus width */
347 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
348 if (mmc->bus_width == 8) {
349 ctrl &= ~SDHCI_CTRL_4BITBUS;
Joe Hershberger073cfd12012-08-17 10:18:54 +0000350 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
Lei Wenaf62a552011-06-28 21:50:06 +0000351 ctrl |= SDHCI_CTRL_8BITBUS;
352 } else {
Joe Hershberger073cfd12012-08-17 10:18:54 +0000353 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
Lei Wenaf62a552011-06-28 21:50:06 +0000354 ctrl &= ~SDHCI_CTRL_8BITBUS;
355 if (mmc->bus_width == 4)
356 ctrl |= SDHCI_CTRL_4BITBUS;
357 else
358 ctrl &= ~SDHCI_CTRL_4BITBUS;
359 }
360
361 if (mmc->clock > 26000000)
362 ctrl |= SDHCI_CTRL_HISPD;
363 else
364 ctrl &= ~SDHCI_CTRL_HISPD;
365
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000366 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
367 ctrl &= ~SDHCI_CTRL_HISPD;
368
Lei Wenaf62a552011-06-28 21:50:06 +0000369 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
370}
371
372int sdhci_init(struct mmc *mmc)
373{
374 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
375
376 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
377 aligned_buffer = memalign(8, 512*1024);
378 if (!aligned_buffer) {
379 printf("Aligned buffer alloc failed!!!");
380 return -1;
381 }
382 }
383
Joe Hershberger470dcc72012-08-17 10:18:55 +0000384 sdhci_set_power(host, fls(mmc->voltages) - 1);
385
386 if (host->quirks & SDHCI_QUIRK_NO_CD) {
387 unsigned int status;
388
389 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
390 SDHCI_HOST_CONTROL);
391
392 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
393 while ((!(status & SDHCI_CARD_PRESENT)) ||
394 (!(status & SDHCI_CARD_STATE_STABLE)) ||
395 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
396 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
397 }
398
Ɓukasz Majewskice0c1bc2013-01-11 05:08:54 +0000399 /* Enable only interrupts served by the SD controller */
400 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
401 , SDHCI_INT_ENABLE);
402 /* Mask all sdhci interrupt sources */
403 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wenaf62a552011-06-28 21:50:06 +0000404
Lei Wenaf62a552011-06-28 21:50:06 +0000405 return 0;
406}
407
408int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
409{
410 struct mmc *mmc;
411 unsigned int caps;
412
413 mmc = malloc(sizeof(struct mmc));
414 if (!mmc) {
415 printf("mmc malloc fail!\n");
416 return -1;
417 }
418
419 mmc->priv = host;
Lei Wen6cf1b172011-10-08 04:14:56 +0000420 host->mmc = mmc;
Lei Wenaf62a552011-06-28 21:50:06 +0000421
422 sprintf(mmc->name, "%s", host->name);
423 mmc->send_cmd = sdhci_send_command;
424 mmc->set_ios = sdhci_set_ios;
425 mmc->init = sdhci_init;
Thierry Reding48972d92012-01-02 01:15:37 +0000426 mmc->getcd = NULL;
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000427 mmc->getwp = NULL;
Lei Wenaf62a552011-06-28 21:50:06 +0000428
429 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
430#ifdef CONFIG_MMC_SDMA
431 if (!(caps & SDHCI_CAN_DO_SDMA)) {
432 printf("Your controller don't support sdma!!\n");
433 return -1;
434 }
435#endif
436
437 if (max_clk)
438 mmc->f_max = max_clk;
439 else {
Joe Hershberger073cfd12012-08-17 10:18:54 +0000440 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
Lei Wenaf62a552011-06-28 21:50:06 +0000441 mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
442 >> SDHCI_CLOCK_BASE_SHIFT;
443 else
444 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
445 >> SDHCI_CLOCK_BASE_SHIFT;
446 mmc->f_max *= 1000000;
447 }
448 if (mmc->f_max == 0) {
449 printf("Hardware doesn't specify base clock frequency\n");
450 return -1;
451 }
452 if (min_clk)
453 mmc->f_min = min_clk;
454 else {
Joe Hershberger073cfd12012-08-17 10:18:54 +0000455 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
Lei Wenaf62a552011-06-28 21:50:06 +0000456 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
457 else
458 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
459 }
460
461 mmc->voltages = 0;
462 if (caps & SDHCI_CAN_VDD_330)
463 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
464 if (caps & SDHCI_CAN_VDD_300)
465 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
466 if (caps & SDHCI_CAN_VDD_180)
467 mmc->voltages |= MMC_VDD_165_195;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000468
469 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
470 mmc->voltages |= host->voltages;
471
Lei Wenaf62a552011-06-28 21:50:06 +0000472 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
Jagannadha Sutradharudu Teki1695b292013-05-21 15:01:36 +0530473 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
474 if (caps & SDHCI_CAN_DO_8BIT)
475 mmc->host_caps |= MMC_MODE_8BIT;
476 }
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000477 if (host->host_caps)
478 mmc->host_caps |= host->host_caps;
Lei Wenaf62a552011-06-28 21:50:06 +0000479
480 sdhci_reset(host, SDHCI_RESET_ALL);
481 mmc_register(mmc);
482
483 return 0;
484}