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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2036621a611222173ea9f9882c7e1d5e4d2b3575 / . / arch / arm / dts / k3-j721e-common-proc-board-u-boot.dtsi
blob: c638af63c18080cffab2b27965710b18afb26dfe [file] [log] [blame]
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Neha Malcom Francis17717862023-07-22 00:14:28 +0530[diff] [blame]6#include "k3-j721e-binman.dtsi"
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +0530[diff] [blame]7
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]8&cbass_main {
9 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]10};
11
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]12&main_navss {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]14};
15
16&cbass_mcu_wakeup {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]18
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]19 chipid@43000014 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Lokesh Vutla70e16742021-02-01 11:26:40 +0530[diff] [blame]21 };
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]22};
23
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]24&mcu_navss {
25 bootph-pre-ram;
26};
27
28&mcu_ringacc {
29 bootph-pre-ram;
30};
31
32&mcu_udmap {
33 reg = <0x0 0x285c0000 0x0 0x100>,
34 <0x0 0x284c0000 0x0 0x4000>,
35 <0x0 0x2a800000 0x0 0x40000>,
36 <0x0 0x284a0000 0x0 0x4000>,
37 <0x0 0x2aa00000 0x0 0x40000>,
38 <0x0 0x28400000 0x0 0x2000>;
39 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
40 "tchanrt", "rflow";
41 bootph-pre-ram;
42};
43
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]44&secure_proxy_main {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]46};
47
48&dmsc {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]50 k3_sysreset: sysreset-controller {
51 compatible = "ti,sci-sysreset";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]53 };
54};
55
56&k3_pds {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]58};
59
60&k3_clks {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]62};
63
64&k3_reset {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]66};
67
68&wkup_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]70};
71
72&main_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]74};
75
76&main_uart0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]78};
79
80&mcu_uart0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]82};
83
84&main_sdhci0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]86};
87
88&main_sdhci1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530[diff] [blame]90};
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +0530[diff] [blame]91
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]92&main_uart0_pins_default {
93 bootph-pre-ram;
Kishon Vijay Abraham Iad256cc2021-07-21 21:28:40 +0530[diff] [blame]94};
95
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]96&main_usbss0_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]98};
99
100&usbss0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]102};
103
104&usb0 {
105 dr_mode = "peripheral";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]107};
108
Faiz Abbasccc855e2020-01-16 19:42:21 +0530[diff] [blame]109&main_mmc1_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Faiz Abbasccc855e2020-01-16 19:42:21 +0530[diff] [blame]111};
Andreas Dannenbergc44fb272020-01-07 13:15:56 +0530[diff] [blame]112
113&wkup_i2c0_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Andreas Dannenbergc44fb272020-01-07 13:15:56 +0530[diff] [blame]115};
116
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]117&wkup_uart0 {
118 bootph-pre-ram;
119 status = "okay";
120};
121
Andreas Dannenbergc44fb272020-01-07 13:15:56 +0530[diff] [blame]122&wkup_i2c0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]124 status = "okay";
Andreas Dannenbergc44fb272020-01-07 13:15:56 +0530[diff] [blame]125};
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530[diff] [blame]126
127&main_i2c0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530[diff] [blame]129};
130
131&main_i2c0_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530[diff] [blame]133};
134
Neha Malcom Francis69b19ca2023-09-27 18:39:56 +0530[diff] [blame]135&main_esm {
136 bootph-pre-ram;
137};
138
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530[diff] [blame]139&exp2 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530[diff] [blame]141};
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]142
143&mcu_fss0_ospi0_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]145};
146
147&fss {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]148 bootph-pre-ram;
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]149};
150
Vaishnav Achathfa4f5aa2022-05-09 11:50:12 +0530[diff] [blame]151&wkup_gpio0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]152 bootph-pre-ram;
Vaishnav Achathfa4f5aa2022-05-09 11:50:12 +0530[diff] [blame]153};
154
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]155&ospi0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]156 bootph-pre-ram;
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]157
158 flash@0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]160 };
161};
Keerthy896cf0e2020-03-04 10:09:59 +0530[diff] [blame]162
163&ospi1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]164 bootph-pre-ram;
Keerthy896cf0e2020-03-04 10:09:59 +0530[diff] [blame]165
166 flash@0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]167 bootph-pre-ram;
Keerthy896cf0e2020-03-04 10:09:59 +0530[diff] [blame]168 };
169};
170
Vaishnav Achathfa4f5aa2022-05-09 11:50:12 +0530[diff] [blame]171&mcu_fss0_hpb0_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]172 bootph-pre-ram;
Vaishnav Achathfa4f5aa2022-05-09 11:50:12 +0530[diff] [blame]173};
174
175&wkup_gpio_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]176 bootph-pre-ram;
Vaishnav Achathfa4f5aa2022-05-09 11:50:12 +0530[diff] [blame]177};
178
Keerthy896cf0e2020-03-04 10:09:59 +0530[diff] [blame]179&mcu_fss0_ospi1_pins_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]180 bootph-pre-ram;
Keerthy896cf0e2020-03-04 10:09:59 +0530[diff] [blame]181};