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wdenk4d75a502003-03-25 16:50:56 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk716c1dc2005-09-25 18:49:35 +02005 * Copyright (c) 2005 MontaVista Software, Inc.
Wolfgang Denk1972dc02005-09-25 16:27:55 +02006 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
8 *
wdenk4d75a502003-03-25 16:50:56 +00009 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29
30#ifdef CONFIG_PCI
31
32#include <pci.h>
wdenk5d232d02003-05-22 22:52:13 +000033#include <mpc8260.h>
wdenk4d75a502003-03-25 16:50:56 +000034#include <asm/m8260_pci.h>
wdenk3c74e322004-02-22 23:46:08 +000035#include <asm/io.h>
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +040036#ifdef CONFIG_OF_LIBFDT
37#include <libfdt.h>
38#include <fdt_support.h>
39#endif
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040
Wolfgang Denk392c2522006-05-30 23:32:44 +020041#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
Wolfgang Denkd87080b2006-03-31 18:32:53 +020042DECLARE_GLOBAL_DATA_PTR;
43#endif
44
wdenk4d75a502003-03-25 16:50:56 +000045/*
wdenk3c74e322004-02-22 23:46:08 +000046 * Local->PCI map (from CPU) controlled by
wdenk4d75a502003-03-25 16:50:56 +000047 * MPC826x master window
48 *
wdenk3c74e322004-02-22 23:46:08 +000049 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
50 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
wdenk8bde7f72003-06-27 21:31:46 +000051 *
wdenk3c74e322004-02-22 23:46:08 +000052 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
53 * PCI Mem with prefetch
wdenk5d232d02003-05-22 22:52:13 +000054 *
wdenk3c74e322004-02-22 23:46:08 +000055 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
56 * PCI Mem w/o prefetch
wdenk5d232d02003-05-22 22:52:13 +000057 *
wdenk3c74e322004-02-22 23:46:08 +000058 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
59 * 32-bit PCI IO
wdenk8bde7f72003-06-27 21:31:46 +000060 *
wdenk4d75a502003-03-25 16:50:56 +000061 * PCI->Local map (from PCI)
wdenk3c74e322004-02-22 23:46:08 +000062 * MPC826x slave window controlled by
wdenk4d75a502003-03-25 16:50:56 +000063 *
wdenk3c74e322004-02-22 23:46:08 +000064 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
65 * MPC826x local memory
wdenk4d75a502003-03-25 16:50:56 +000066 */
67
wdenk8bde7f72003-06-27 21:31:46 +000068/*
69 * Slave window that allows PCI masters to access MPC826x local memory.
wdenk4d75a502003-03-25 16:50:56 +000070 * This window is set up using the first set of Inbound ATU registers
71 */
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
74#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000075#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
wdenk5d232d02003-05-22 22:52:13 +000077#endif
78
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +000080#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +000081#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
wdenk5d232d02003-05-22 22:52:13 +000083#endif
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +000086#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +000087 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +000088#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
wdenk5d232d02003-05-22 22:52:13 +000090#endif
wdenk4d75a502003-03-25 16:50:56 +000091
wdenk8bde7f72003-06-27 21:31:46 +000092/*
wdenk5d232d02003-05-22 22:52:13 +000093 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +000094 * All three PCI master windows, which allow the CPU to access PCI
95 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +000096 * these windows.
wdenk4d75a502003-03-25 16:50:56 +000097 */
98
wdenk5d232d02003-05-22 22:52:13 +000099/* PCIBR0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000101#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000102#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000104#endif
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#ifndef CONFIG_SYS_PCIMSK0_MASK
wdenk3c74e322004-02-22 23:46:08 +0000107#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000108#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
wdenk5d232d02003-05-22 22:52:13 +0000110#endif
111
112/* PCIBR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000114#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000115#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000117#endif
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#ifndef CONFIG_SYS_PCIMSK1_MASK
wdenk3c74e322004-02-22 23:46:08 +0000120#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
wdenk5d232d02003-05-22 22:52:13 +0000123#endif
wdenk4d75a502003-03-25 16:50:56 +0000124
wdenk8bde7f72003-06-27 21:31:46 +0000125/*
wdenk4d75a502003-03-25 16:50:56 +0000126 * Master window that allows the CPU to access PCI Memory (prefetch).
127 * This window will be setup with the first set of Outbound ATU registers
128 * in the bridge.
129 */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000132#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
wdenk5d232d02003-05-22 22:52:13 +0000133#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000135#endif
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +0000138#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +0000139#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
wdenk5d232d02003-05-22 22:52:13 +0000141#endif
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#ifndef CONFIG_SYS_CPU_PCI_MEM_START
wdenk5d232d02003-05-22 22:52:13 +0000144#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
145#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
wdenk5d232d02003-05-22 22:52:13 +0000147#endif
148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000150#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
wdenk5d232d02003-05-22 22:52:13 +0000151#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000153#endif
154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +0000156#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000157#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
wdenk5d232d02003-05-22 22:52:13 +0000159#endif
wdenk4d75a502003-03-25 16:50:56 +0000160
wdenk8bde7f72003-06-27 21:31:46 +0000161/*
wdenk4d75a502003-03-25 16:50:56 +0000162 * Master window that allows the CPU to access PCI Memory (non-prefetch).
163 * This window will be setup with the second set of Outbound ATU registers
164 * in the bridge.
165 */
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000168#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000169#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000171#endif
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000174#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000175#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000177#endif
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
wdenk8bde7f72003-06-27 21:31:46 +0000180#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
wdenk5d232d02003-05-22 22:52:13 +0000183#endif
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000186#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
wdenk8bde7f72003-06-27 21:31:46 +0000187#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000189#endif
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000192#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000193#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
wdenk5d232d02003-05-22 22:52:13 +0000195#endif
wdenk4d75a502003-03-25 16:50:56 +0000196
wdenk8bde7f72003-06-27 21:31:46 +0000197/*
wdenk4d75a502003-03-25 16:50:56 +0000198 * Master window that allows the CPU to access PCI IO space.
199 * This window will be setup with the third set of Outbound ATU registers
200 * in the bridge.
201 */
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000204#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000205#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
wdenk66fd3d12003-05-18 11:30:09 +0000207#endif
wdenk5d232d02003-05-22 22:52:13 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000210#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000213#endif
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#ifndef CONFIG_SYS_CPU_PCI_IO_START
wdenk8bde7f72003-06-27 21:31:46 +0000216#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
217#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
wdenk5d232d02003-05-22 22:52:13 +0000219#endif
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000222#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
wdenk8bde7f72003-06-27 21:31:46 +0000223#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000225#endif
226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000228#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
wdenk5d232d02003-05-22 22:52:13 +0000231#endif
wdenk4d75a502003-03-25 16:50:56 +0000232
233/* PCI bus configuration registers.
234 */
235
236#define PCI_CLASS_BRIDGE_CTLR 0x06
237
238
wdenk3c74e322004-02-22 23:46:08 +0000239static inline void pci_outl (u32 addr, u32 data)
wdenk4d75a502003-03-25 16:50:56 +0000240{
wdenk3c74e322004-02-22 23:46:08 +0000241 *(volatile u32 *) addr = cpu_to_le32 (data);
wdenk4d75a502003-03-25 16:50:56 +0000242}
243
wdenk3c74e322004-02-22 23:46:08 +0000244void pci_mpc8250_init (struct pci_controller *hose)
wdenk4d75a502003-03-25 16:50:56 +0000245{
wdenk3c74e322004-02-22 23:46:08 +0000246 u16 tempShort;
wdenk4d75a502003-03-25 16:50:56 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk3c74e322004-02-22 23:46:08 +0000249 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
wdenk4d75a502003-03-25 16:50:56 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
252 CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
wdenk3c74e322004-02-22 23:46:08 +0000253
254 /*
255 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
256 */
wdenk5d232d02003-05-22 22:52:13 +0000257#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000258 immap->im_siu_conf.sc_siumcr =
259 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
260 | SIUMCR_LBPC01;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200261#elif defined CONFIG_MPC8272
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200262 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
263 ~SIUMCR_BBD &
264 ~SIUMCR_ESE &
265 ~SIUMCR_PBSE &
266 ~SIUMCR_CDIS &
267 ~SIUMCR_DPPC11 &
268 ~SIUMCR_L2CPC11 &
269 ~SIUMCR_LBPC11 &
270 ~SIUMCR_APPC11 &
271 ~SIUMCR_CS10PC11 &
272 ~SIUMCR_BCTLC11 &
273 ~SIUMCR_MMR11)
274 | SIUMCR_DPPC11
275 | SIUMCR_L2CPC01
276 | SIUMCR_LBPC00
277 | SIUMCR_APPC10
278 | SIUMCR_CS10PC00
279 | SIUMCR_BCTLC00
280 | SIUMCR_MMR11;
Heiko Schocherfa230442006-12-21 17:17:02 +0100281#elif defined(CONFIG_TQM8272)
Heiko Schocher07e82cb2007-03-21 08:45:17 +0100282/* nothing to do for this Board here */
wdenk5d232d02003-05-22 22:52:13 +0000283#else
wdenk3c74e322004-02-22 23:46:08 +0000284 /*
285 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
286 * and local bus for PCI (SIUMCR [LBPC]).
287 */
288 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
289 ~SIUMCR_LBPC11 &
wdenk8bde7f72003-06-27 21:31:46 +0000290 ~SIUMCR_CS10PC11 &
wdenk3c74e322004-02-22 23:46:08 +0000291 ~SIUMCR_LBPC11) |
292 SIUMCR_LBPC01 |
293 SIUMCR_CS10PC01 |
294 SIUMCR_APPC10;
wdenk5d232d02003-05-22 22:52:13 +0000295#endif
wdenk4d75a502003-03-25 16:50:56 +0000296
wdenk3c74e322004-02-22 23:46:08 +0000297 /* Make PCI lowest priority */
298 /* Each 4 bits is a device bus request and the MS 4bits
299 is highest priority */
300 /* Bus 4bit value
301 --- ----------
302 CPM high 0b0000
303 CPM middle 0b0001
304 CPM low 0b0010
305 PCI reguest 0b0011
306 Reserved 0b0100
307 Reserved 0b0101
308 Internal Core 0b0110
309 External Master 1 0b0111
310 External Master 2 0b1000
311 External Master 3 0b1001
312 The rest are reserved */
313 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
wdenk4d75a502003-03-25 16:50:56 +0000314
wdenk3c74e322004-02-22 23:46:08 +0000315 /* Park bus on core while modifying PCI Bus accesses */
316 immap->im_siu_conf.sc_ppc_acr = 0x6;
wdenk4d75a502003-03-25 16:50:56 +0000317
wdenk3c74e322004-02-22 23:46:08 +0000318 /*
319 * Set up master windows that allow the CPU to access PCI space. These
320 * windows are set up using the two SIU PCIBR registers.
321 */
322 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
323 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
wdenk5d232d02003-05-22 22:52:13 +0000324
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200325#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenkd4326ac2004-04-18 21:17:30 +0000326 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
327 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
wdenk8bde7f72003-06-27 21:31:46 +0000328#endif
wdenk4d75a502003-03-25 16:50:56 +0000329
wdenk3c74e322004-02-22 23:46:08 +0000330 /* Release PCI RST (by default the PCI RST signal is held low) */
331 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
wdenk4d75a502003-03-25 16:50:56 +0000332
wdenk3c74e322004-02-22 23:46:08 +0000333 /* give it some time */
334 {
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200335#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk8bde7f72003-06-27 21:31:46 +0000336 /* Give the PCI cards more time to initialize before query
wdenk3c74e322004-02-22 23:46:08 +0000337 This might be good for other boards also
338 */
339 int i;
340
341 for (i = 0; i < 1000; ++i)
wdenk5d232d02003-05-22 22:52:13 +0000342#endif
wdenk3c74e322004-02-22 23:46:08 +0000343 udelay (1000);
344 }
wdenk4d75a502003-03-25 16:50:56 +0000345
wdenk3c74e322004-02-22 23:46:08 +0000346 /*
347 * Set up master window that allows the CPU to access PCI Memory (prefetch)
348 * space. This window is set up using the first set of Outbound ATU registers.
349 */
350 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
351 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
352 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000353
wdenk3c74e322004-02-22 23:46:08 +0000354 /*
355 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
356 * space. This window is set up using the second set of Outbound ATU registers.
357 */
358 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
359 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
360 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
wdenk8bde7f72003-06-27 21:31:46 +0000361
wdenk3c74e322004-02-22 23:46:08 +0000362 /*
363 * Set up master window that allows the CPU to access PCI IO space. This window
364 * is set up using the third set of Outbound ATU registers.
365 */
366 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
367 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
368 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000369
wdenk3c74e322004-02-22 23:46:08 +0000370 /*
371 * Set up slave window that allows PCI masters to access MPC826x local memory.
372 * This window is set up using the first set of Inbound ATU registers
373 */
374 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
375 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
376 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000377
wdenk3c74e322004-02-22 23:46:08 +0000378 /* See above for description - puts PCI request as highest priority */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200379#ifdef CONFIG_MPC8272
380 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
381#else
wdenk3c74e322004-02-22 23:46:08 +0000382 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200383#endif
wdenk4d75a502003-03-25 16:50:56 +0000384
wdenk3c74e322004-02-22 23:46:08 +0000385 /* Park the bus on the PCI */
386 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
wdenk4d75a502003-03-25 16:50:56 +0000387
wdenk3c74e322004-02-22 23:46:08 +0000388 /* Host mode - specify the bridge as a host-PCI bridge */
wdenk4d75a502003-03-25 16:50:56 +0000389
wdenk3c74e322004-02-22 23:46:08 +0000390 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
391 PCI_CLASS_BRIDGE_CTLR);
wdenk4d75a502003-03-25 16:50:56 +0000392
wdenk3c74e322004-02-22 23:46:08 +0000393 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
394 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
395 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
396 tempShort | PCI_COMMAND_MASTER |
397 PCI_COMMAND_MEMORY);
wdenk4d75a502003-03-25 16:50:56 +0000398
wdenk7a8e9bed2003-05-31 18:35:21 +0000399 /* do some bridge init, should be done on all 8260 based bridges */
wdenk3c74e322004-02-22 23:46:08 +0000400 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
401 0x08);
402 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
403 0xF8);
wdenk7a8e9bed2003-05-31 18:35:21 +0000404
wdenk3c74e322004-02-22 23:46:08 +0000405 hose->first_busno = 0;
406 hose->last_busno = 0xff;
wdenk4d75a502003-03-25 16:50:56 +0000407
wdenk3c74e322004-02-22 23:46:08 +0000408 /* System memory space */
Wolfgang Denk392c2522006-05-30 23:32:44 +0200409#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
wdenk3c74e322004-02-22 23:46:08 +0000410 pci_set_region (hose->regions + 0,
411 PCI_SLV_MEM_BUS,
412 PCI_SLV_MEM_LOCAL,
413 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000414#else
wdenk3c74e322004-02-22 23:46:08 +0000415 pci_set_region (hose->regions + 0,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 CONFIG_SYS_SDRAM_BASE,
417 CONFIG_SYS_SDRAM_BASE,
wdenk3c74e322004-02-22 23:46:08 +0000418 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000419#endif
wdenk4d75a502003-03-25 16:50:56 +0000420
wdenk3c74e322004-02-22 23:46:08 +0000421 /* PCI memory space */
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200422#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000423 pci_set_region (hose->regions + 1,
424 PCI_MSTR_MEMIO_BUS,
425 PCI_MSTR_MEMIO_LOCAL,
426 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000427#else
wdenk3c74e322004-02-22 23:46:08 +0000428 pci_set_region (hose->regions + 1,
429 PCI_MSTR_MEM_BUS,
430 PCI_MSTR_MEM_LOCAL,
431 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000432#endif
wdenk4d75a502003-03-25 16:50:56 +0000433
wdenk3c74e322004-02-22 23:46:08 +0000434 /* PCI I/O space */
435 pci_set_region (hose->regions + 2,
436 PCI_MSTR_IO_BUS,
437 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
wdenk4d75a502003-03-25 16:50:56 +0000438
wdenk3c74e322004-02-22 23:46:08 +0000439 hose->region_count = 3;
wdenk4d75a502003-03-25 16:50:56 +0000440
wdenk3c74e322004-02-22 23:46:08 +0000441 pci_register_hose (hose);
442 /* Mask off master abort machine checks */
443 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
444 eieio ();
wdenk4d75a502003-03-25 16:50:56 +0000445
wdenk3c74e322004-02-22 23:46:08 +0000446 hose->last_busno = pci_hose_scan (hose);
447
448
449 /* clear the error in the error status register */
450 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
451
452 /* unmask master abort machine checks */
453 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
wdenk4d75a502003-03-25 16:50:56 +0000454}
455
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +0400456#if defined(CONFIG_OF_LIBFDT)
457void ft_pci_setup(void *blob, bd_t *bd)
458{
459 do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
Wolfgang Denk52b047a2008-08-12 12:10:11 +0200460 "clock-frequency", gd->pci_clk, 1);
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +0400461}
462#endif
463
wdenk3c74e322004-02-22 23:46:08 +0000464#endif /* CONFIG_PCI */