blob: 24affe0414cef93be6f35d881c72d74e0ca762e1 [file] [log] [blame]
Vikas Manocha94d53082017-02-12 10:25:49 -08001#include <common.h>
Vikas Manocha94d53082017-02-12 10:25:49 -08002#include <dm.h>
3#include <dm/pinctrl.h>
Benjamin Gaignard075b0182018-11-27 13:49:53 +01004#include <hwspinlock.h>
Vikas Manocha77417102017-04-10 15:02:57 -07005#include <asm/arch/gpio.h>
6#include <asm/gpio.h>
7#include <asm/io.h>
Vikas Manocha94d53082017-02-12 10:25:49 -08008
9DECLARE_GLOBAL_DATA_PTR;
10
Vikas Manocha58fb3c82017-04-10 15:03:04 -070011#define MAX_PINS_ONE_IP 70
Vikas Manocha77417102017-04-10 15:02:57 -070012#define MODE_BITS_MASK 3
13#define OSPEED_MASK 3
14#define PUPD_MASK 3
15#define OTYPE_MSK 1
16#define AFR_MASK 0xF
17
Patrice Chotard8f651ca2018-10-24 14:10:18 +020018struct stm32_pinctrl_priv {
Benjamin Gaignard075b0182018-11-27 13:49:53 +010019 struct hwspinlock hws;
Patrice Chotard8f651ca2018-10-24 14:10:18 +020020 int pinctrl_ngpios;
21 struct list_head gpio_dev;
22};
23
24struct stm32_gpio_bank {
25 struct udevice *gpio_dev;
26 struct list_head list;
27};
28
Benjamin Gaignard075b0182018-11-27 13:49:53 +010029#ifndef CONFIG_SPL_BUILD
30
Patrice Chotard4ff1c202018-10-24 14:10:19 +020031static char pin_name[PINNAME_SIZE];
Patrice Chotardb42d9382018-10-24 14:10:20 +020032#define PINMUX_MODE_COUNT 5
33static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
34 "gpio input",
35 "gpio output",
36 "analog",
37 "unknown",
38 "alt function",
39};
40
41static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
42{
43 struct stm32_gpio_priv *priv = dev_get_priv(dev);
44 struct stm32_gpio_regs *regs = priv->regs;
45 u32 af;
46 u32 alt_shift = (offset % 8) * 4;
47 u32 alt_index = offset / 8;
48
49 af = (readl(&regs->afr[alt_index]) &
50 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
51
52 return af;
53}
54
Patrice Chotard04355042018-12-03 10:52:50 +010055static int stm32_populate_gpio_dev_list(struct udevice *dev)
56{
57 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
58 struct udevice *gpio_dev;
59 struct udevice *child;
60 struct stm32_gpio_bank *gpio_bank;
61 int ret;
62
63 /*
64 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
65 * a list with all gpio device reference which belongs to the
66 * current pin-controller. This list is used to find pin_name and
67 * pin muxing
68 */
69 list_for_each_entry(child, &dev->child_head, sibling_node) {
70 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
71 &gpio_dev);
72 if (ret < 0)
73 continue;
74
75 gpio_bank = malloc(sizeof(*gpio_bank));
76 if (!gpio_bank) {
77 dev_err(dev, "Not enough memory\n");
78 return -ENOMEM;
79 }
80
81 gpio_bank->gpio_dev = gpio_dev;
82 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
83 }
84
85 return 0;
86}
87
Patrice Chotard8f651ca2018-10-24 14:10:18 +020088static int stm32_pinctrl_get_pins_count(struct udevice *dev)
89{
90 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
91 struct gpio_dev_priv *uc_priv;
92 struct stm32_gpio_bank *gpio_bank;
93
94 /*
95 * if get_pins_count has already been executed once on this
96 * pin-controller, no need to run it again
97 */
98 if (priv->pinctrl_ngpios)
99 return priv->pinctrl_ngpios;
100
Patrice Chotard04355042018-12-03 10:52:50 +0100101 if (list_empty(&priv->gpio_dev))
102 stm32_populate_gpio_dev_list(dev);
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200103 /*
104 * walk through all banks to retrieve the pin-controller
105 * pins number
106 */
107 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
108 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
109
110 priv->pinctrl_ngpios += uc_priv->gpio_count;
111 }
112
113 return priv->pinctrl_ngpios;
114}
115
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200116static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
Patrice Chotard530b63c2018-12-03 10:52:54 +0100117 unsigned int selector,
118 unsigned int *idx)
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200119{
120 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
121 struct stm32_gpio_bank *gpio_bank;
122 struct gpio_dev_priv *uc_priv;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100123 int pin_count = 0;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200124
Patrice Chotard04355042018-12-03 10:52:50 +0100125 if (list_empty(&priv->gpio_dev))
126 stm32_populate_gpio_dev_list(dev);
127
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200128 /* look up for the bank which owns the requested pin */
129 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
130 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
131
Patrice Chotard530b63c2018-12-03 10:52:54 +0100132 if (selector < (pin_count + uc_priv->gpio_count)) {
133 /*
134 * we found the bank, convert pin selector to
135 * gpio bank index
136 */
137 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
138 selector - pin_count);
139 if (*idx < 0)
140 return NULL;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200141
Patrice Chotard530b63c2018-12-03 10:52:54 +0100142 return gpio_bank->gpio_dev;
143 }
144 pin_count += uc_priv->gpio_count;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200145 }
146
147 return NULL;
148}
149
150static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
151 unsigned int selector)
152{
153 struct gpio_dev_priv *uc_priv;
154 struct udevice *gpio_dev;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100155 unsigned int gpio_idx;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200156
157 /* look up for the bank which owns the requested pin */
Patrice Chotard530b63c2018-12-03 10:52:54 +0100158 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200159 if (!gpio_dev) {
160 snprintf(pin_name, PINNAME_SIZE, "Error");
161 } else {
162 uc_priv = dev_get_uclass_priv(gpio_dev);
163
164 snprintf(pin_name, PINNAME_SIZE, "%s%d",
165 uc_priv->bank_name,
Patrice Chotard530b63c2018-12-03 10:52:54 +0100166 gpio_idx);
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200167 }
168
169 return pin_name;
170}
Patrice Chotardb42d9382018-10-24 14:10:20 +0200171
172static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
173 unsigned int selector,
174 char *buf,
175 int size)
176{
177 struct udevice *gpio_dev;
178 const char *label;
Patrice Chotardb42d9382018-10-24 14:10:20 +0200179 int mode;
180 int af_num;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100181 unsigned int gpio_idx;
Patrice Chotardb42d9382018-10-24 14:10:20 +0200182
183 /* look up for the bank which owns the requested pin */
Patrice Chotard530b63c2018-12-03 10:52:54 +0100184 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200185
186 if (!gpio_dev)
187 return -ENODEV;
188
Patrice Chotard530b63c2018-12-03 10:52:54 +0100189 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200190
Patrice Chotard530b63c2018-12-03 10:52:54 +0100191 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
192 selector, gpio_idx, mode);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200193
Patrice Chotardb42d9382018-10-24 14:10:20 +0200194
195 switch (mode) {
196 case GPIOF_UNKNOWN:
197 /* should never happen */
198 return -EINVAL;
199 case GPIOF_UNUSED:
200 snprintf(buf, size, "%s", pinmux_mode[mode]);
201 break;
202 case GPIOF_FUNC:
Patrice Chotard530b63c2018-12-03 10:52:54 +0100203 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200204 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
205 break;
206 case GPIOF_OUTPUT:
207 case GPIOF_INPUT:
208 snprintf(buf, size, "%s %s",
209 pinmux_mode[mode], label ? label : "");
210 break;
211 }
212
213 return 0;
214}
215
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100216#endif
217
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200218int stm32_pinctrl_probe(struct udevice *dev)
219{
220 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200221 int ret;
222
223 INIT_LIST_HEAD(&priv->gpio_dev);
224
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100225 /* hwspinlock property is optional, just log the error */
226 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
227 if (ret)
228 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
229 __func__, ret);
230
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200231 return 0;
232}
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200233
Vikas Manocha77417102017-04-10 15:02:57 -0700234static int stm32_gpio_config(struct gpio_desc *desc,
235 const struct stm32_gpio_ctl *ctl)
236{
237 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
238 struct stm32_gpio_regs *regs = priv->regs;
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100239 struct stm32_pinctrl_priv *ctrl_priv;
240 int ret;
Vikas Manocha77417102017-04-10 15:02:57 -0700241 u32 index;
242
243 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
244 ctl->pupd > 2 || ctl->speed > 3)
245 return -EINVAL;
246
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100247 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
248 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
249 if (ret == -ETIME) {
250 dev_err(desc->dev, "HWSpinlock timeout\n");
251 return ret;
252 }
253
Vikas Manocha77417102017-04-10 15:02:57 -0700254 index = (desc->offset & 0x07) * 4;
255 clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
256 ctl->af << index);
257
258 index = desc->offset * 2;
259 clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
260 ctl->mode << index);
261 clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
262 ctl->speed << index);
263 clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
264
265 index = desc->offset;
266 clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
267
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100268 hwspinlock_unlock(&ctrl_priv->hws);
269
Vikas Manocha77417102017-04-10 15:02:57 -0700270 return 0;
271}
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100272
Vikas Manocha94d53082017-02-12 10:25:49 -0800273static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
274{
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100275 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
Vikas Manocha94d53082017-02-12 10:25:49 -0800276 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
277 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
278 gpio_dsc->pin);
279
280 return 0;
281}
282
283static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
284{
285 gpio_fn &= 0x00FF;
Vikas Manocha77417102017-04-10 15:02:57 -0700286 gpio_ctl->af = 0;
Vikas Manocha94d53082017-02-12 10:25:49 -0800287
288 switch (gpio_fn) {
289 case 0:
290 gpio_ctl->mode = STM32_GPIO_MODE_IN;
291 break;
292 case 1 ... 16:
293 gpio_ctl->mode = STM32_GPIO_MODE_AF;
294 gpio_ctl->af = gpio_fn - 1;
295 break;
296 case 17:
297 gpio_ctl->mode = STM32_GPIO_MODE_AN;
298 break;
299 default:
300 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
301 break;
302 }
303
304 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
305
306 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
307 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
308 else
309 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
310
311 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
312 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
313 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
314 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
315 else
316 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
317
318 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
319 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
320 gpio_ctl->pupd);
321
322 return 0;
323}
324
Christophe Kerelload0376e2017-06-20 17:04:18 +0200325static int stm32_pinctrl_config(int offset)
Vikas Manocha94d53082017-02-12 10:25:49 -0800326{
Vikas Manocha58fb3c82017-04-10 15:03:04 -0700327 u32 pin_mux[MAX_PINS_ONE_IP];
Vikas Manocha94d53082017-02-12 10:25:49 -0800328 int rv, len;
329
Vikas Manocha94d53082017-02-12 10:25:49 -0800330 /*
331 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
332 * usart1) of pin controller phandle "pinctrl-0"
333 * */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200334 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
Vikas Manocha94d53082017-02-12 10:25:49 -0800335 struct stm32_gpio_dsc gpio_dsc;
336 struct stm32_gpio_ctl gpio_ctl;
337 int i;
338
Christophe Kerelload0376e2017-06-20 17:04:18 +0200339 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
Vikas Manocha94d53082017-02-12 10:25:49 -0800340 "pinmux", pin_mux,
341 ARRAY_SIZE(pin_mux));
Christophe Kerelload0376e2017-06-20 17:04:18 +0200342 debug("%s: no of pinmux entries= %d\n", __func__, len);
Vikas Manocha94d53082017-02-12 10:25:49 -0800343 if (len < 0)
344 return -EINVAL;
345 for (i = 0; i < len; i++) {
Vikas Manocha280057b2017-04-10 15:02:59 -0700346 struct gpio_desc desc;
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100347
Vikas Manocha94d53082017-02-12 10:25:49 -0800348 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
349 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
Christophe Kerelload0376e2017-06-20 17:04:18 +0200350 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
Vikas Manocha280057b2017-04-10 15:02:59 -0700351 rv = uclass_get_device_by_seq(UCLASS_GPIO,
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100352 gpio_dsc.port,
353 &desc.dev);
Vikas Manocha280057b2017-04-10 15:02:59 -0700354 if (rv)
355 return rv;
356 desc.offset = gpio_dsc.pin;
357 rv = stm32_gpio_config(&desc, &gpio_ctl);
Vikas Manocha94d53082017-02-12 10:25:49 -0800358 debug("%s: rv = %d\n\n", __func__, rv);
359 if (rv)
360 return rv;
361 }
362 }
363
364 return 0;
365}
366
Christophe Kerellobb44b962017-06-20 17:04:19 +0200367#if CONFIG_IS_ENABLED(PINCTRL_FULL)
368static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
369{
370 return stm32_pinctrl_config(dev_of_offset(config));
371}
372#else /* PINCTRL_FULL */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200373static int stm32_pinctrl_set_state_simple(struct udevice *dev,
374 struct udevice *periph)
375{
376 const void *fdt = gd->fdt_blob;
377 const fdt32_t *list;
378 uint32_t phandle;
379 int config_node;
380 int size, i, ret;
381
382 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
383 if (!list)
384 return -EINVAL;
385
386 debug("%s: periph->name = %s\n", __func__, periph->name);
387
388 size /= sizeof(*list);
389 for (i = 0; i < size; i++) {
390 phandle = fdt32_to_cpu(*list++);
391
392 config_node = fdt_node_offset_by_phandle(fdt, phandle);
393 if (config_node < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900394 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
Christophe Kerelload0376e2017-06-20 17:04:18 +0200395 return -EINVAL;
396 }
397
398 ret = stm32_pinctrl_config(config_node);
399 if (ret)
400 return ret;
401 }
402
403 return 0;
404}
Christophe Kerellobb44b962017-06-20 17:04:19 +0200405#endif /* PINCTRL_FULL */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200406
Vikas Manocha94d53082017-02-12 10:25:49 -0800407static struct pinctrl_ops stm32_pinctrl_ops = {
Christophe Kerellobb44b962017-06-20 17:04:19 +0200408#if CONFIG_IS_ENABLED(PINCTRL_FULL)
409 .set_state = stm32_pinctrl_set_state,
410#else /* PINCTRL_FULL */
Vikas Manocha94d53082017-02-12 10:25:49 -0800411 .set_state_simple = stm32_pinctrl_set_state_simple,
Christophe Kerellobb44b962017-06-20 17:04:19 +0200412#endif /* PINCTRL_FULL */
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200413#ifndef CONFIG_SPL_BUILD
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200414 .get_pin_name = stm32_pinctrl_get_pin_name,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200415 .get_pins_count = stm32_pinctrl_get_pins_count,
Patrice Chotardb42d9382018-10-24 14:10:20 +0200416 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200417#endif
Vikas Manocha94d53082017-02-12 10:25:49 -0800418};
419
420static const struct udevice_id stm32_pinctrl_ids[] = {
Patrice Chotard98693c22017-12-12 09:49:35 +0100421 { .compatible = "st,stm32f429-pinctrl" },
422 { .compatible = "st,stm32f469-pinctrl" },
Vikas Manocha94d53082017-02-12 10:25:49 -0800423 { .compatible = "st,stm32f746-pinctrl" },
Patrice Chotard092e72c2017-09-13 18:00:04 +0200424 { .compatible = "st,stm32h743-pinctrl" },
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100425 { .compatible = "st,stm32mp157-pinctrl" },
426 { .compatible = "st,stm32mp157-z-pinctrl" },
Vikas Manocha94d53082017-02-12 10:25:49 -0800427 { }
428};
429
430U_BOOT_DRIVER(pinctrl_stm32) = {
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200431 .name = "pinctrl_stm32",
432 .id = UCLASS_PINCTRL,
433 .of_match = stm32_pinctrl_ids,
434 .ops = &stm32_pinctrl_ops,
435 .bind = dm_scan_fdt_dev,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200436 .probe = stm32_pinctrl_probe,
437 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
Vikas Manocha94d53082017-02-12 10:25:49 -0800438};