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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +05302/*
3 * Copyright (C) 2015
4 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 *
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +05306 */
7#include <common.h>
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +05308#include <clk.h>
9#include <dm.h>
Simon Glass7fe32b32022-03-04 08:43:05 -070010#include <event.h>
Simon Glass691d7192020-05-10 11:40:02 -060011#include <init.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <malloc.h>
Simon Glass401d1c42020-10-30 21:38:53 -060013#include <asm/global_data.h>
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053014#include <mach/pic32.h>
15#include <mach/ddr.h>
16#include <dt-bindings/clock/microchip,clock.h>
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053017
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053018/* Flash prefetch */
19#define PRECON 0x00
20
21/* Flash ECCCON */
22#define ECC_MASK 0x03
23#define ECC_SHIFT 4
24
25#define CLK_MHZ(x) ((x) / 1000000)
26
27DECLARE_GLOBAL_DATA_PTR;
28
Stephen Warren135aa952016-06-17 09:44:00 -060029static ulong rate(int id)
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053030{
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053031 int ret;
32 struct udevice *dev;
Stephen Warren135aa952016-06-17 09:44:00 -060033 struct clk clk;
34 ulong rate;
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053035
36 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
37 if (ret) {
Stephen Warren135aa952016-06-17 09:44:00 -060038 printf("clk-uclass not found\n");
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053039 return 0;
40 }
41
Stephen Warren135aa952016-06-17 09:44:00 -060042 clk.id = id;
43 ret = clk_request(dev, &clk);
44 if (ret < 0)
45 return ret;
46
47 rate = clk_get_rate(&clk);
48
49 clk_free(&clk);
50
51 return rate;
52}
53
54static ulong clk_get_cpu_rate(void)
55{
56 return rate(PB7CLK);
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +053057}
58
59/* initialize prefetch module related to cpu_clk */
60static void prefetch_init(void)
61{
62 struct pic32_reg_atomic *regs;
63 const void __iomem *base;
64 int v, nr_waits;
65 ulong rate;
66
67 /* cpu frequency in MHZ */
68 rate = clk_get_cpu_rate() / 1000000;
69
70 /* get flash ECC type */
71 base = pic32_get_syscfg_base();
72 v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
73
74 if (v < 2) {
75 if (rate < 66)
76 nr_waits = 0;
77 else if (rate < 133)
78 nr_waits = 1;
79 else
80 nr_waits = 2;
81 } else {
82 if (rate <= 83)
83 nr_waits = 0;
84 else if (rate <= 166)
85 nr_waits = 1;
86 else
87 nr_waits = 2;
88 }
89
90 regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
91 writel(nr_waits, &regs->raw);
92
93 /* Enable prefetch for all */
94 writel(0x30, &regs->set);
95 iounmap(regs);
96}
97
98/* arch specific CPU init after DM */
Simon Glass7fe32b32022-03-04 08:43:05 -070099static int pic32_flash_prefetch(void *ctx, struct event *event)
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530100{
101 /* flash prefetch */
102 prefetch_init();
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530103 return 0;
104}
Simon Glass7fe32b32022-03-04 08:43:05 -0700105EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch);
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530106
107/* Un-gate DDR2 modules (gated by default) */
108static void ddr2_pmd_ungate(void)
109{
110 void __iomem *regs;
111
112 regs = pic32_get_syscfg_base();
113 writel(0, regs + PMD7);
114}
115
116/* initialize the DDR2 Controller and DDR2 PHY */
Simon Glassf1683aa2017-04-06 12:47:05 -0600117int dram_init(void)
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530118{
119 ddr2_pmd_ungate();
120 ddr2_phy_init();
121 ddr2_ctrl_init();
Simon Glass088454c2017-03-31 08:40:25 -0600122 gd->ram_size = ddr2_calculate_size();
123
124 return 0;
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530125}
126
127int misc_init_r(void)
128{
129 set_io_port_base(0);
130 return 0;
131}
132
133#ifdef CONFIG_DISPLAY_BOARDINFO
134const char *get_core_name(void)
135{
136 u32 proc_id;
137 const char *str;
138
139 proc_id = read_c0_prid();
140 switch (proc_id) {
141 case 0x19e28:
142 str = "PIC32MZ[DA]";
143 break;
144 default:
145 str = "UNKNOWN";
146 }
147
148 return str;
149}
150#endif
151#ifdef CONFIG_CMD_CLK
Stephen Warren135aa952016-06-17 09:44:00 -0600152
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530153int soc_clk_dump(void)
154{
Stephen Warren135aa952016-06-17 09:44:00 -0600155 int i;
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530156
157 printf("PLL Speed: %lu MHz\n",
Stephen Warren135aa952016-06-17 09:44:00 -0600158 CLK_MHZ(rate(PLLCLK)));
159
160 printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
161
162 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530163
164 for (i = PB1CLK; i <= PB7CLK; i++)
165 printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
Stephen Warren135aa952016-06-17 09:44:00 -0600166 CLK_MHZ(rate(i)));
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530167
168 for (i = REF1CLK; i <= REF5CLK; i++)
169 printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
Stephen Warren135aa952016-06-17 09:44:00 -0600170 CLK_MHZ(rate(i)));
Purna Chandra Mandalbe961fa2016-01-28 15:30:16 +0530171 return 0;
172}
173#endif