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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roese512f8d52006-05-10 14:10:41 +02002 * (C) Copyright 2000-2006
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenkc6097192002-11-03 00:24:07 +000025 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
39
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040#if !defined(CONFIG_405)
41DECLARE_GLOBAL_DATA_PTR;
42#endif
43
Stefan Roesef3443862006-10-07 11:30:52 +020044#if defined(CONFIG_BOARD_RESET)
45void board_reset(void);
46#endif
47
Stefan Roese3d9569b2005-11-27 19:36:26 +010048#if defined(CONFIG_440)
49#define FREQ_EBC (sys_info.freqEPB)
50#else
51#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
52#endif
53
Stefan Roese887e2ec2006-09-07 11:51:23 +020054#if defined(CONFIG_405GP) || \
55 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
56 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010057
58#define PCI_ASYNC
59
60int pci_async_enabled(void)
61{
62#if defined(CONFIG_405GP)
63 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
64#endif
65
Stefan Roese887e2ec2006-09-07 11:51:23 +020066#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
67 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010068 unsigned long val;
69
Wolfgang Denk74812662005-12-12 16:06:05 +010070 mfsdr(sdr_sdstp1, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010071 return (val & SDR0_SDSTP1_PAME_MASK);
72#endif
73}
74#endif
75
Stefan Roesea46726f2005-11-29 19:13:38 +010076#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010077int pci_arbiter_enabled(void)
78{
79#if defined(CONFIG_405GP)
80 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
81#endif
82
83#if defined(CONFIG_405EP)
84 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
85#endif
86
87#if defined(CONFIG_440GP)
88 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
89#endif
90
Stefan Roese887e2ec2006-09-07 11:51:23 +020091#if defined(CONFIG_440GX) || \
92 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
93 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
94 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010095 unsigned long val;
96
97 mfsdr(sdr_sdstp1, val);
98 return (val & SDR0_SDSTP1_PAE_MASK);
99#endif
100}
101#endif
102
Stefan Roese887e2ec2006-09-07 11:51:23 +0200103#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
104 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100107
108#define I2C_BOOTROM
109
110int i2c_bootrom_enabled(void)
111{
112#if defined(CONFIG_405EP)
113 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200114#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100115 unsigned long val;
116
117 mfsdr(sdr_sdcs, val);
118 return (val & SDR0_SDCS_SDD);
119#endif
120}
Stefan Roese887e2ec2006-09-07 11:51:23 +0200121
122#if defined(CONFIG_440GX)
123#define SDR0_PINSTP_SHIFT 29
124static char *bootstrap_str[] = {
125 "EBC (16 bits)",
126 "EBC (8 bits)",
127 "EBC (32 bits)",
128 "EBC (8 bits)",
129 "PCI",
130 "I2C (Addr 0x54)",
131 "Reserved",
132 "I2C (Addr 0x50)",
133};
134#endif
135
136#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
137#define SDR0_PINSTP_SHIFT 30
138static char *bootstrap_str[] = {
139 "EBC (8 bits)",
140 "PCI",
141 "I2C (Addr 0x54)",
142 "I2C (Addr 0x50)",
143};
144#endif
145
146#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
147#define SDR0_PINSTP_SHIFT 29
148static char *bootstrap_str[] = {
149 "EBC (8 bits)",
150 "PCI",
151 "NAND (8 bits)",
152 "EBC (16 bits)",
153 "EBC (16 bits)",
154 "I2C (Addr 0x54)",
155 "PCI",
156 "I2C (Addr 0x52)",
157};
158#endif
159
160#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
161#define SDR0_PINSTP_SHIFT 29
162static char *bootstrap_str[] = {
163 "EBC (8 bits)",
164 "EBC (16 bits)",
165 "EBC (16 bits)",
166 "NAND (8 bits)",
167 "PCI",
168 "I2C (Addr 0x54)",
169 "PCI",
170 "I2C (Addr 0x52)",
171};
172#endif
173
174#if defined(SDR0_PINSTP_SHIFT)
175static int bootstrap_option(void)
176{
177 unsigned long val;
178
179 mfsdr(sdr_pinstp, val);
180 return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
181}
182#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100183#endif
184
Stefan Roese3d9569b2005-11-27 19:36:26 +0100185
186#if defined(CONFIG_440)
187static int do_chip_reset(unsigned long sys0, unsigned long sys1);
188#endif
189
wdenkc6097192002-11-03 00:24:07 +0000190
191int checkcpu (void)
192{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100193#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100194 uint pvr = get_pvr();
wdenkc6097192002-11-03 00:24:07 +0000195 ulong clock = gd->cpu_clk;
196 char buf[32];
wdenkc6097192002-11-03 00:24:07 +0000197
Stefan Roese3d9569b2005-11-27 19:36:26 +0100198#if !defined(CONFIG_IOP480)
Wolfgang Denkba999c52006-10-20 17:54:33 +0200199 char addstr[64] = "";
Stefan Roese3d9569b2005-11-27 19:36:26 +0100200 sys_info_t sys_info;
wdenkc6097192002-11-03 00:24:07 +0000201
202 puts ("CPU: ");
203
204 get_sys_info(&sys_info);
205
Stefan Roese3d9569b2005-11-27 19:36:26 +0100206 puts("AMCC PowerPC 4");
207
208#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
209 puts("05");
wdenkc6097192002-11-03 00:24:07 +0000210#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100211#if defined(CONFIG_440)
212 puts("40");
wdenkc6097192002-11-03 00:24:07 +0000213#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100214
wdenkc6097192002-11-03 00:24:07 +0000215 switch (pvr) {
216 case PVR_405GP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100217 puts("GP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000218 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100219
wdenkc6097192002-11-03 00:24:07 +0000220 case PVR_405GP_RC:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100221 puts("GP Rev. C");
wdenkc6097192002-11-03 00:24:07 +0000222 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100223
wdenkc6097192002-11-03 00:24:07 +0000224 case PVR_405GP_RD:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100225 puts("GP Rev. D");
wdenkc6097192002-11-03 00:24:07 +0000226 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100227
wdenk42dfe7a2004-03-14 22:25:36 +0000228#ifdef CONFIG_405GP
Stefan Roese3d9569b2005-11-27 19:36:26 +0100229 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
230 puts("GP Rev. E");
wdenkc6097192002-11-03 00:24:07 +0000231 break;
232#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100233
wdenkc6097192002-11-03 00:24:07 +0000234 case PVR_405CR_RA:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100235 puts("CR Rev. A");
wdenkc6097192002-11-03 00:24:07 +0000236 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100237
wdenkc6097192002-11-03 00:24:07 +0000238 case PVR_405CR_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100239 puts("CR Rev. B");
240 break;
241
242#ifdef CONFIG_405CR
243 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
244 puts("CR Rev. C");
245 break;
246#endif
247
248 case PVR_405GPR_RB:
249 puts("GPr Rev. B");
250 break;
251
stroeseb867d702003-05-23 11:18:02 +0000252 case PVR_405EP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100253 puts("EP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000254 break;
wdenkc6097192002-11-03 00:24:07 +0000255
256#if defined(CONFIG_440)
wdenk8bde7f72003-06-27 21:31:46 +0000257 case PVR_440GP_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200258 puts("GP Rev. B");
wdenk4d816772003-09-03 14:03:26 +0000259 /* See errata 1.12: CHIP_4 */
260 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
261 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
262 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
263 "Resetting chip ...\n");
264 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
265 do_chip_reset ( mfdcr(cpc0_strp0),
266 mfdcr(cpc0_strp1) );
267 }
wdenkc6097192002-11-03 00:24:07 +0000268 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100269
wdenk8bde7f72003-06-27 21:31:46 +0000270 case PVR_440GP_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200271 puts("GP Rev. C");
wdenkba56f622004-02-06 23:19:44 +0000272 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100273
wdenkba56f622004-02-06 23:19:44 +0000274 case PVR_440GX_RA:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200275 puts("GX Rev. A");
wdenkba56f622004-02-06 23:19:44 +0000276 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100277
wdenkba56f622004-02-06 23:19:44 +0000278 case PVR_440GX_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200279 puts("GX Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000280 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100281
stroese0a7c5392005-04-07 05:33:41 +0000282 case PVR_440GX_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200283 puts("GX Rev. C");
stroese0a7c5392005-04-07 05:33:41 +0000284 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100285
Stefan Roese57275b62005-11-01 10:08:03 +0100286 case PVR_440GX_RF:
287 puts("GX Rev. F");
288 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100289
Stefan Roesec157d8e2005-08-01 16:41:48 +0200290 case PVR_440EP_RA:
291 puts("EP Rev. A");
292 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100293
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200294#ifdef CONFIG_440EP
295 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200296 puts("EP Rev. B");
297 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200298
299 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
300 puts("EP Rev. C");
301 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200302#endif /* CONFIG_440EP */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100303
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200304#ifdef CONFIG_440GR
305 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
306 puts("GR Rev. A");
307 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200308
Stefan Roese5770a1e2006-05-18 19:21:53 +0200309 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200310 puts("GR Rev. B");
311 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200312#endif /* CONFIG_440GR */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100313#endif /* CONFIG_440 */
314
Stefan Roese2902fad2007-01-31 16:56:10 +0100315#ifdef CONFIG_440EPX
316 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200317 puts("EPx Rev. A");
318 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200319 break;
320
Stefan Roese2902fad2007-01-31 16:56:10 +0100321 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200322 puts("EPx Rev. A");
323 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200324 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100325#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200326
Stefan Roese2902fad2007-01-31 16:56:10 +0100327#ifdef CONFIG_440GRX
328 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200329 puts("GRx Rev. A");
330 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200331 break;
332
Stefan Roese2902fad2007-01-31 16:56:10 +0100333 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200334 puts("GRx Rev. A");
335 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200336 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100337#endif /* CONFIG_440GRX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200338
Stefan Roese95981772007-01-13 08:01:03 +0100339 case PVR_440SP_6_RAB:
340 puts("SP Rev. A/B");
341 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100342 break;
343
Stefan Roese95981772007-01-13 08:01:03 +0100344 case PVR_440SP_RAB:
345 puts("SP Rev. A/B");
346 strcpy(addstr, "No RAID 6 support");
347 break;
348
349 case PVR_440SP_6_RC:
350 puts("SP Rev. C");
351 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100352 break;
353
Stefan Roesee732fae2006-11-28 16:09:24 +0100354 case PVR_440SP_RC:
355 puts("SP Rev. C");
Stefan Roese95981772007-01-13 08:01:03 +0100356 strcpy(addstr, "No RAID 6 support");
357 break;
358
359 case PVR_440SPe_6_RA:
360 puts("SPe Rev. A");
361 strcpy(addstr, "RAID 6 support");
Stefan Roesee732fae2006-11-28 16:09:24 +0100362 break;
363
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200364 case PVR_440SPe_RA:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200365 puts("SPe Rev. A");
Stefan Roese95981772007-01-13 08:01:03 +0100366 strcpy(addstr, "No RAID 6 support");
367 break;
368
369 case PVR_440SPe_6_RB:
370 puts("SPe Rev. B");
371 strcpy(addstr, "RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200372 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200373
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200374 case PVR_440SPe_RB:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200375 puts("SPe Rev. B");
Stefan Roese95981772007-01-13 08:01:03 +0100376 strcpy(addstr, "No RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200377 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200378
wdenk8bde7f72003-06-27 21:31:46 +0000379 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200380 printf (" UNKNOWN (PVR=%08x)", pvr);
wdenkc6097192002-11-03 00:24:07 +0000381 break;
382 }
Stefan Roese3d9569b2005-11-27 19:36:26 +0100383
384 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
385 sys_info.freqPLB / 1000000,
386 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
387 FREQ_EBC / 1000000);
388
Stefan Roeseedf0b542006-10-18 15:59:35 +0200389 if (addstr[0] != 0)
390 printf(" %s\n", addstr);
391
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100392#if defined(I2C_BOOTROM)
393 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200394#if defined(SDR0_PINSTP_SHIFT)
395 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
396 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
Wolfgang Denkba999c52006-10-20 17:54:33 +0200397#endif /* SDR0_PINSTP_SHIFT */
398#endif /* I2C_BOOTROM */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100399
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100400#if defined(CONFIG_PCI)
401 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100402#endif
403
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100404#if defined(PCI_ASYNC)
405 if (pci_async_enabled()) {
Stefan Roese3d9569b2005-11-27 19:36:26 +0100406 printf (", PCI async ext clock used");
407 } else {
408 printf (", PCI sync clock at %lu MHz",
409 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
410 }
411#endif
412
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100413#if defined(CONFIG_PCI)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100414 putc('\n');
415#endif
416
417#if defined(CONFIG_405EP)
418 printf (" 16 kB I-Cache 16 kB D-Cache");
419#elif defined(CONFIG_440)
420 printf (" 32 kB I-Cache 32 kB D-Cache");
421#else
422 printf (" 16 kB I-Cache %d kB D-Cache",
423 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
424#endif
425#endif /* !defined(CONFIG_IOP480) */
426
427#if defined(CONFIG_IOP480)
428 printf ("PLX IOP480 (PVR=%08x)", pvr);
429 printf (" at %s MHz:", strmhz(buf, clock));
430 printf (" %u kB I-Cache", 4);
431 printf (" %u kB D-Cache", 2);
432#endif
433
434#endif /* !defined(CONFIG_405) */
435
436 putc ('\n');
wdenkc6097192002-11-03 00:24:07 +0000437
438 return 0;
439}
440
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200441#if defined (CONFIG_440SPE)
442int ppc440spe_revB() {
443 unsigned int pvr;
444
445 pvr = get_pvr();
Stefan Roese5a5c5692007-01-15 09:46:29 +0100446 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200447 return 1;
448 else
449 return 0;
450}
451#endif
wdenkc6097192002-11-03 00:24:07 +0000452
453/* ------------------------------------------------------------------------- */
454
wdenk8bde7f72003-06-27 21:31:46 +0000455int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000456{
Stefan Roese1f94d162006-11-27 14:48:41 +0100457#if defined(CONFIG_BOARD_RESET)
458 board_reset();
Stefan Roese1729b922006-11-27 14:52:04 +0100459#else
Stefan Roese1c2ce222006-11-27 14:12:17 +0100460#if defined(CFG_4xx_RESET_TYPE)
461 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200462#else
wdenk8bde7f72003-06-27 21:31:46 +0000463 /*
464 * Initiate system reset in debug control register DBCR
465 */
Stefan Roesef3443862006-10-07 11:30:52 +0200466 mtspr(dbcr0, 0x30000000);
Stefan Roese1729b922006-11-27 14:52:04 +0100467#endif /* defined(CFG_4xx_RESET_TYPE) */
Stefan Roesef3443862006-10-07 11:30:52 +0200468#endif /* defined(CONFIG_BOARD_RESET) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200469
wdenkc6097192002-11-03 00:24:07 +0000470 return 1;
471}
472
473#if defined(CONFIG_440)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100474static int do_chip_reset (unsigned long sys0, unsigned long sys1)
wdenkc6097192002-11-03 00:24:07 +0000475{
wdenk4d816772003-09-03 14:03:26 +0000476 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
477 * reset.
478 */
479 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
480 mtdcr (cpc0_sys0, sys0);
481 mtdcr (cpc0_sys1, sys1);
482 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
483 mtspr (dbcr0, 0x20000000); /* Reset the chip */
wdenkc6097192002-11-03 00:24:07 +0000484
wdenk4d816772003-09-03 14:03:26 +0000485 return 1;
wdenkc6097192002-11-03 00:24:07 +0000486}
487#endif
488
489
490/*
491 * Get timebase clock frequency
492 */
493unsigned long get_tbclk (void)
494{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100495#if !defined(CONFIG_IOP480)
wdenkc6097192002-11-03 00:24:07 +0000496 sys_info_t sys_info;
497
498 get_sys_info(&sys_info);
499 return (sys_info.freqProcessor);
wdenkc6097192002-11-03 00:24:07 +0000500#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100501 return (66000000);
wdenkc6097192002-11-03 00:24:07 +0000502#endif
503
504}
505
506
507#if defined(CONFIG_WATCHDOG)
508void
509watchdog_reset(void)
510{
511 int re_enable = disable_interrupts();
512 reset_4xx_watchdog();
513 if (re_enable) enable_interrupts();
514}
515
516void
517reset_4xx_watchdog(void)
518{
519 /*
520 * Clear TSR(WIS) bit
521 */
522 mtspr(tsr, 0x40000000);
523}
524#endif /* CONFIG_WATCHDOG */