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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2b6a013caf3ca6daa84a96ee72ea2cb88cf78a8f / . / arch / arm / dts / am33xx.dtsi
blob: 3c7e0385f36405c3b580892b307b861be4a5582c [file] [log] [blame]
Andrew Davisd30b2bf2023-04-11 13:24:54 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]2/*
3 * Device Tree Source for AM33XX SoC
4 *
Andrew Davisd30b2bf2023-04-11 13:24:54 -0500[diff] [blame]5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]6 */
7
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]8#include <dt-bindings/bus/ti-sysc.h>
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/am33xx.h>
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]11#include <dt-bindings/clock/am3.h>
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]12
13/ {
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]16 #address-cells = <1>;
17 #size-cells = <1>;
18 chosen { };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]19
20 aliases {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]30 d-can0 = &dcan0;
31 d-can1 = &dcan1;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]38 spi0 = &spi0;
39 spi1 = &spi1;
Lukasz Majewskiab9e48f2022-02-18 13:28:42 +0100[diff] [blame]40 mmc0 = &mmc1;
41 mmc1 = &mmc2;
Lukasz Majewski4a9099e2022-02-18 13:28:43 +0100[diff] [blame]42 mmc2 = &mmc3;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 compatible = "arm,cortex-a8";
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]50 enable-method = "ti,am3352";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]51 device_type = "cpu";
52 reg = <0>;
53
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]54 operating-points-v2 = <&cpu0_opp_table>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]55
56 clocks = <&dpll_mpu_ck>;
57 clock-names = "cpu";
58
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]59 clock-latency = <300000>; /* From omap-cpufreq driver */
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]60 cpu-idle-states = <&mpu_gate>;
61 };
62
63 idle-states {
64 mpu_gate: mpu_gate {
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
69 ti,idle-wkup-m3;
70 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]71 };
72 };
73
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
76 syscon = <&scm_conf>;
77
78 /*
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
81 * single SoC.
82 */
83 opp50-300000000 {
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
87 opp-suspend;
88 };
89
90 opp100-275000000 {
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
94 opp-suspend;
95 };
96
97 opp100-300000000 {
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
101 opp-suspend;
102 };
103
104 opp100-500000000 {
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
108 };
109
110 opp100-600000000 {
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
114 };
115
116 opp120-600000000 {
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
120 };
121
122 opp120-720000000 {
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
126 };
127
128 oppturbo-720000000 {
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
132 };
133
134 oppturbo-800000000 {
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
138 };
139
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
144 };
145 };
146
147 pmu@4b000000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]148 compatible = "arm,cortex-a8-pmu";
149 interrupts = <3>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]150 reg = <0x4b000000 0x1000000>;
151 ti,hwmods = "debugss";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]152 };
153
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]154 /*
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]155 * The soc node represents the soc top level view. It is used for IPs
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]156 * that are not memory mapped in the MPU view or for the MPU itself.
157 */
158 soc {
159 compatible = "ti,omap-infra";
160 mpu {
161 compatible = "ti,omap3-mpu";
162 ti,hwmods = "mpu";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]163 pm-sram = <&pm_sram_code
164 &pm_sram_data>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]165 };
166 };
167
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]168 /*
169 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]170 * The real AM33XX interconnect network is quite complex. Since
171 * it will not bring real advantage to represent that in DT
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]172 * for the moment, just use a fake OCP bus entry to represent
173 * the whole bus hierarchy.
174 */
Andrew Davis211b3d72023-04-11 13:25:05 -0500[diff] [blame]175 ocp: ocp {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]176 compatible = "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges;
180 ti,hwmods = "l3_main";
181
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]182 l4_wkup: l4_wkup@44c00000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]183 wkup_m3: wkup_m3@100000 {
184 compatible = "ti,am3352-wkup-m3";
185 reg = <0x100000 0x4000>,
186 <0x180000 0x2000>;
187 reg-names = "umem", "dmem";
188 ti,hwmods = "wkup_m3";
189 ti,pm-firmware = "am335x-pm-firmware.elf";
190 };
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]191 };
192 l4_per: interconnect@48000000 {
193 };
194 l4_fw: interconnect@47c00000 {
195 };
196 l4_fast: interconnect@4a000000 {
197 };
198 l4_mpuss: interconnect@4b140000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]199 };
200
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]201 intc: interrupt-controller@48200000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]202 compatible = "ti,am33xx-intc";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]203 interrupt-controller;
204 #interrupt-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]205 reg = <0x48200000 0x1000>;
206 };
207
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]208 target-module@49000000 {
209 compatible = "ti,sysc-omap4", "ti,sysc";
210 reg = <0x49000000 0x4>;
211 reg-names = "rev";
212 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
213 clock-names = "fck";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges = <0x0 0x49000000 0x10000>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]217
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]218 edma: dma@0 {
219 compatible = "ti,edma3-tpcc";
220 reg = <0 0x10000>;
221 reg-names = "edma3_cc";
222 interrupts = <12 13 14>;
223 interrupt-names = "edma3_ccint", "edma3_mperr",
224 "edma3_ccerrint";
225 dma-requests = <64>;
226 #dma-cells = <2>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]227
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]228 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
229 <&edma_tptc2 0>;
230
231 ti,edma-memcpy-channels = <20 21>;
232 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]233 };
234
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]235 target-module@49800000 {
236 compatible = "ti,sysc-omap4", "ti,sysc";
237 reg = <0x49800000 0x4>,
238 <0x49800010 0x4>;
239 reg-names = "rev", "sysc";
240 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
241 ti,sysc-midle = <SYSC_IDLE_FORCE>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
243 <SYSC_IDLE_SMART>;
244 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
245 clock-names = "fck";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x49800000 0x100000>;
249
250 edma_tptc0: dma@0 {
251 compatible = "ti,edma3-tptc";
252 reg = <0 0x100000>;
253 interrupts = <112>;
254 interrupt-names = "edma3_tcerrint";
255 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]256 };
257
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]258 target-module@49900000 {
259 compatible = "ti,sysc-omap4", "ti,sysc";
260 reg = <0x49900000 0x4>,
261 <0x49900010 0x4>;
262 reg-names = "rev", "sysc";
263 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
264 ti,sysc-midle = <SYSC_IDLE_FORCE>;
265 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_SMART>;
267 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
268 clock-names = "fck";
269 #address-cells = <1>;
270 #size-cells = <1>;
271 ranges = <0x0 0x49900000 0x100000>;
272
273 edma_tptc1: dma@0 {
274 compatible = "ti,edma3-tptc";
275 reg = <0 0x100000>;
276 interrupts = <113>;
277 interrupt-names = "edma3_tcerrint";
278 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]279 };
280
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]281 target-module@49a00000 {
282 compatible = "ti,sysc-omap4", "ti,sysc";
283 reg = <0x49a00000 0x4>,
284 <0x49a00010 0x4>;
285 reg-names = "rev", "sysc";
286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
287 ti,sysc-midle = <SYSC_IDLE_FORCE>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
289 <SYSC_IDLE_SMART>;
290 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
291 clock-names = "fck";
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges = <0x0 0x49a00000 0x100000>;
295
296 edma_tptc2: dma@0 {
297 compatible = "ti,edma3-tptc";
298 reg = <0 0x100000>;
299 interrupts = <114>;
300 interrupt-names = "edma3_tcerrint";
301 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]302 };
303
Lukasz Majewski4a9099e2022-02-18 13:28:43 +0100[diff] [blame]304 target-module@47810000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x478102fc 0x4>,
307 <0x47810110 0x4>,
308 <0x47810114 0x4>;
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
311 SYSC_OMAP2_ENAWAKEUP |
312 SYSC_OMAP2_SOFTRESET |
313 SYSC_OMAP2_AUTOIDLE)>;
314 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
315 <SYSC_IDLE_NO>,
316 <SYSC_IDLE_SMART>;
317 ti,syss-mask = <1>;
318 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
319 clock-names = "fck";
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0x0 0x47810000 0x1000>;
323
324 mmc3: mmc@0 {
Andrew Davis211b3d72023-04-11 13:25:05 -0500[diff] [blame]325 compatible = "ti,am335-sdhci";
326 ti,needs-special-reset;
327 interrupts = <29>;
328 reg = <0x0 0x1000>;
329 status = "disabled";
Lukasz Majewski4a9099e2022-02-18 13:28:43 +0100[diff] [blame]330 };
331 };
332
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]333 i2c0: i2c@44e0b000 {
334 compatible = "ti,omap4-i2c";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 ti,hwmods = "i2c1";
338 reg = <0x44e0b000 0x1000>;
339 interrupts = <70>;
340 status = "disabled";
341 };
342
343 i2c1: i2c@4802a000 {
344 compatible = "ti,omap4-i2c";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 ti,hwmods = "i2c2";
348 reg = <0x4802a000 0x1000>;
349 interrupts = <71>;
350 status = "disabled";
351 };
352
353 i2c2: i2c@4819c000 {
354 compatible = "ti,omap4-i2c";
355 #address-cells = <1>;
356 #size-cells = <0>;
357 ti,hwmods = "i2c3";
358 reg = <0x4819c000 0x1000>;
359 interrupts = <30>;
360 status = "disabled";
361 };
362
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]363 mmc1: mmc@48060000 {
364 compatible = "ti,omap4-hsmmc";
365 ti,hwmods = "mmc1";
366 ti,dual-volt;
367 ti,needs-special-reset;
368 ti,needs-special-hs-handling;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]369 dmas = <&edma_xbar 24 0 0
370 &edma_xbar 25 0 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]371 dma-names = "tx", "rx";
372 interrupts = <64>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]373 reg = <0x48060000 0x1000>;
374 status = "disabled";
375 };
376
377 mmc2: mmc@481d8000 {
378 compatible = "ti,omap4-hsmmc";
379 ti,hwmods = "mmc2";
380 ti,needs-special-reset;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]381 dmas = <&edma 2 0
382 &edma 3 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]383 dma-names = "tx", "rx";
384 interrupts = <28>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]385 reg = <0x481d8000 0x1000>;
386 status = "disabled";
387 };
388
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]389 wdt2: wdt@44e35000 {
390 compatible = "ti,omap3-wdt";
391 ti,hwmods = "wd_timer2";
392 reg = <0x44e35000 0x1000>;
393 interrupts = <91>;
394 };
395
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]396 usb: usb@47400000 {
397 compatible = "ti,am33xx-usb";
398 reg = <0x47400000 0x1000>;
399 ranges;
400 #address-cells = <1>;
401 #size-cells = <1>;
402 ti,hwmods = "usb_otg_hs";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]403
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]404 usb_ctrl_mod: control@44e10620 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]405 compatible = "ti,am335x-usb-ctrl-module";
406 reg = <0x44e10620 0x10
407 0x44e10648 0x4>;
408 reg-names = "phy_ctrl", "wakeup";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]409 };
410
411 usb0_phy: usb-phy@47401300 {
412 compatible = "ti,am335x-usb-phy";
413 reg = <0x47401300 0x100>;
414 reg-names = "phy";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]415 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]416 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]417 };
418
419 usb0: usb@47401000 {
420 compatible = "ti,musb-am33xx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]421 reg = <0x47401400 0x400
422 0x47401000 0x200>;
423 reg-names = "mc", "control";
424
425 interrupts = <18>;
426 interrupt-names = "mc";
427 dr_mode = "otg";
428 mentor,multipoint = <1>;
429 mentor,num-eps = <16>;
430 mentor,ram-bits = <12>;
431 mentor,power = <500>;
432 phys = <&usb0_phy>;
433
434 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
435 &cppi41dma 2 0 &cppi41dma 3 0
436 &cppi41dma 4 0 &cppi41dma 5 0
437 &cppi41dma 6 0 &cppi41dma 7 0
438 &cppi41dma 8 0 &cppi41dma 9 0
439 &cppi41dma 10 0 &cppi41dma 11 0
440 &cppi41dma 12 0 &cppi41dma 13 0
441 &cppi41dma 14 0 &cppi41dma 0 1
442 &cppi41dma 1 1 &cppi41dma 2 1
443 &cppi41dma 3 1 &cppi41dma 4 1
444 &cppi41dma 5 1 &cppi41dma 6 1
445 &cppi41dma 7 1 &cppi41dma 8 1
446 &cppi41dma 9 1 &cppi41dma 10 1
447 &cppi41dma 11 1 &cppi41dma 12 1
448 &cppi41dma 13 1 &cppi41dma 14 1>;
449 dma-names =
450 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
451 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
452 "rx14", "rx15",
453 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
454 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
455 "tx14", "tx15";
456 };
457
458 usb1_phy: usb-phy@47401b00 {
459 compatible = "ti,am335x-usb-phy";
460 reg = <0x47401b00 0x100>;
461 reg-names = "phy";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]462 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]463 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]464 };
465
466 usb1: usb@47401800 {
467 compatible = "ti,musb-am33xx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]468 reg = <0x47401c00 0x400
469 0x47401800 0x200>;
470 reg-names = "mc", "control";
471 interrupts = <19>;
472 interrupt-names = "mc";
473 dr_mode = "otg";
474 mentor,multipoint = <1>;
475 mentor,num-eps = <16>;
476 mentor,ram-bits = <12>;
477 mentor,power = <500>;
478 phys = <&usb1_phy>;
479
480 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
481 &cppi41dma 17 0 &cppi41dma 18 0
482 &cppi41dma 19 0 &cppi41dma 20 0
483 &cppi41dma 21 0 &cppi41dma 22 0
484 &cppi41dma 23 0 &cppi41dma 24 0
485 &cppi41dma 25 0 &cppi41dma 26 0
486 &cppi41dma 27 0 &cppi41dma 28 0
487 &cppi41dma 29 0 &cppi41dma 15 1
488 &cppi41dma 16 1 &cppi41dma 17 1
489 &cppi41dma 18 1 &cppi41dma 19 1
490 &cppi41dma 20 1 &cppi41dma 21 1
491 &cppi41dma 22 1 &cppi41dma 23 1
492 &cppi41dma 24 1 &cppi41dma 25 1
493 &cppi41dma 26 1 &cppi41dma 27 1
494 &cppi41dma 28 1 &cppi41dma 29 1>;
495 dma-names =
496 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
497 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
498 "rx14", "rx15",
499 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
500 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
501 "tx14", "tx15";
502 };
503
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]504 cppi41dma: dma-controller@2000 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]505 compatible = "ti,am3359-cppi41";
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]506 reg = <0x0000 0x1000>,
507 <0x2000 0x1000>,
508 <0x3000 0x1000>,
509 <0x4000 0x4000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]510 reg-names = "glue", "controller", "scheduler", "queuemgr";
511 interrupts = <17>;
512 interrupt-names = "glue";
513 #dma-cells = <2>;
514 #dma-channels = <30>;
515 #dma-requests = <256>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]516 };
517 };
518
519 mac: ethernet@4a100000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]520 compatible = "ti,am335x-cpsw","ti,cpsw";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]521 ti,hwmods = "cpgmac0";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]522 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
523 clock-names = "fck", "cpts";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]524 cpdma_channels = <8>;
525 ale_entries = <1024>;
526 bd_ram_size = <0x2000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]527 mac_control = <0x20>;
528 slaves = <2>;
529 active_slave = <0>;
530 cpts_clock_mult = <0x80000000>;
531 cpts_clock_shift = <29>;
532 reg = <0x4a100000 0x800
533 0x4a101200 0x100>;
534 #address-cells = <1>;
535 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]536 /*
537 * c0_rx_thresh_pend
538 * c0_rx_pend
539 * c0_tx_pend
540 * c0_misc_pend
541 */
542 interrupts = <40 41 42 43>;
543 ranges;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]544 syscon = <&scm_conf>;
545 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]546
547 davinci_mdio: mdio@4a101000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]548 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]549 #address-cells = <1>;
550 #size-cells = <0>;
551 ti,hwmods = "davinci_mdio";
552 bus_freq = <1000000>;
553 reg = <0x4a101000 0x100>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]554 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]555 };
556
557 cpsw_emac0: slave@4a100200 {
558 /* Filled in by U-Boot */
559 mac-address = [ 00 00 00 00 00 00 ];
560 };
561
562 cpsw_emac1: slave@4a100300 {
563 /* Filled in by U-Boot */
564 mac-address = [ 00 00 00 00 00 00 ];
565 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]566
567 phy_sel: cpsw-phy-sel@44e10650 {
568 compatible = "ti,am3352-cpsw-phy-sel";
569 reg= <0x44e10650 0x4>;
570 reg-names = "gmii-sel";
571 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]572 };
573
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]574 ocmcram: sram@40300000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]575 compatible = "mmio-sram";
576 reg = <0x40300000 0x10000>; /* 64k */
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]577 ranges = <0x0 0x40300000 0x10000>;
578 #address-cells = <1>;
579 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]580
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]581 pm_sram_code: pm-code-sram@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]582 compatible = "ti,sram";
583 reg = <0x0 0x1000>;
584 protect-exec;
585 };
586
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]587 pm_sram_data: pm-data-sram@1000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]588 compatible = "ti,sram";
589 reg = <0x1000 0x1000>;
590 pool;
591 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]592 };
593
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]594 emif: emif@4c000000 {
595 compatible = "ti,emif-am3352";
596 reg = <0x4c000000 0x1000000>;
597 ti,hwmods = "emif";
598 interrupts = <101>;
599 sram = <&pm_sram_code
600 &pm_sram_data>;
601 ti,no-idle;
602 };
603
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]604 gpmc: gpmc@50000000 {
605 compatible = "ti,am3352-gpmc";
606 ti,hwmods = "gpmc";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]607 ti,no-idle-on-init;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]608 reg = <0x50000000 0x2000>;
609 interrupts = <100>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]610 dmas = <&edma 52 0>;
611 dma-names = "rxtx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]612 gpmc,num-cs = <7>;
613 gpmc,num-waitpins = <2>;
614 #address-cells = <2>;
615 #size-cells = <1>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]616 interrupt-controller;
617 #interrupt-cells = <2>;
618 gpio-controller;
619 #gpio-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]620 status = "disabled";
621 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]622
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]623 sham_target: target-module@53100000 {
624 compatible = "ti,sysc-omap3-sham", "ti,sysc";
625 reg = <0x53100100 0x4>,
626 <0x53100110 0x4>,
627 <0x53100114 0x4>;
628 reg-names = "rev", "sysc", "syss";
629 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
630 SYSC_OMAP2_AUTOIDLE)>;
631 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
632 <SYSC_IDLE_NO>,
633 <SYSC_IDLE_SMART>;
634 ti,syss-mask = <1>;
635 /* Domains (P, C): per_pwrdm, l3_clkdm */
636 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
637 clock-names = "fck";
638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges = <0x0 0x53100000 0x1000>;
641
642 sham: sham@0 {
643 compatible = "ti,omap4-sham";
644 reg = <0 0x200>;
645 interrupts = <109>;
646 dmas = <&edma 36 0>;
647 dma-names = "rx";
648 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]649 };
650
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]651 aes_target: target-module@53500000 {
652 compatible = "ti,sysc-omap2", "ti,sysc";
653 reg = <0x53500080 0x4>,
654 <0x53500084 0x4>,
655 <0x53500088 0x4>;
656 reg-names = "rev", "sysc", "syss";
657 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
658 SYSC_OMAP2_AUTOIDLE)>;
659 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
660 <SYSC_IDLE_NO>,
661 <SYSC_IDLE_SMART>,
662 <SYSC_IDLE_SMART_WKUP>;
663 ti,syss-mask = <1>;
664 /* Domains (P, C): per_pwrdm, l3_clkdm */
665 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
666 clock-names = "fck";
667 #address-cells = <1>;
668 #size-cells = <1>;
669 ranges = <0x0 0x53500000 0x1000>;
670
671 aes: aes@0 {
672 compatible = "ti,omap4-aes";
673 reg = <0 0xa0>;
674 interrupts = <103>;
675 dmas = <&edma 6 0>,
676 <&edma 5 0>;
677 dma-names = "tx", "rx";
678 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]679 };
680
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]681 target-module@56000000 {
682 compatible = "ti,sysc-omap4", "ti,sysc";
683 reg = <0x5600fe00 0x4>,
684 <0x5600fe10 0x4>;
685 reg-names = "rev", "sysc";
686 ti,sysc-midle = <SYSC_IDLE_FORCE>,
687 <SYSC_IDLE_NO>,
688 <SYSC_IDLE_SMART>;
689 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
690 <SYSC_IDLE_NO>,
691 <SYSC_IDLE_SMART>;
692 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
693 clock-names = "fck";
694 resets = <&prm_gfx 0>;
695 reset-names = "rstctrl";
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges = <0 0x56000000 0x1000000>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]699
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]700 /*
701 * Closed source PowerVR driver, no child device
702 * binding or driver in mainline
703 */
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]704 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]705 };
706};
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]707
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]708#include "am33xx-l4.dtsi"
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]709#include "am33xx-clocks.dtsi"
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]710
711&prcm {
712 prm_per: prm@c00 {
713 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
714 reg = <0xc00 0x100>;
715 #reset-cells = <1>;
716 };
717
718 prm_wkup: prm@d00 {
719 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
720 reg = <0xd00 0x100>;
721 #reset-cells = <1>;
722 };
723
724 prm_device: prm@f00 {
725 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
726 reg = <0xf00 0x100>;
727 #reset-cells = <1>;
728 };
729
730 prm_gfx: prm@1100 {
731 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
732 reg = <0x1100 0x100>;
733 #reset-cells = <1>;
734 };
735};