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Prafulla Wadaskar91315892009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2003
7 * Ingo Assmus <ingo.assmus@keymile.com>
8 *
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar91315892009-06-14 22:33:46 +053013 */
14
15#include <common.h>
16#include <net.h>
17#include <malloc.h>
18#include <miiphy.h>
Lei Wena7efd712011-10-18 20:11:42 +053019#include <asm/io.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053020#include <asm/errno.h>
21#include <asm/types.h>
Lei Wena7efd712011-10-18 20:11:42 +053022#include <asm/system.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053023#include <asm/byteorder.h>
Anatolij Gustschin36aaa912011-10-29 10:09:22 +000024#include <asm/arch/cpu.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020025
26#if defined(CONFIG_KIRKWOOD)
Stefan Roese3dc23f72014-10-22 12:13:06 +020027#include <asm/arch/soc.h>
Albert Aribaudd3c9ffd2010-07-12 22:24:29 +020028#elif defined(CONFIG_ORION5X)
29#include <asm/arch/orion5x.h>
Sebastian Hesselbarthfb4879b2012-12-04 09:32:01 +010030#elif defined(CONFIG_DOVE)
31#include <asm/arch/dove.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020032#endif
33
Albert Aribaud9b6bcdc2010-07-12 22:24:27 +020034#include "mvgbe.h"
Prafulla Wadaskar91315892009-06-14 22:33:46 +053035
Albert Aribaud49fa6ed2010-07-05 20:15:25 +020036DECLARE_GLOBAL_DATA_PTR;
37
Albert Aribaudd44265a2010-07-12 22:24:28 +020038#define MV_PHY_ADR_REQUEST 0xee
39#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
Simon Kagstrombb1ca3b2009-08-20 10:12:28 +020040
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +010041#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053042/*
43 * smi_reg_read - miiphy_read callback function.
44 *
45 * Returns 16bit phy register value, or 0xffff on error
46 */
Mike Frysinger5700bb62010-07-27 18:35:08 -040047static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053048{
49 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +020050 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
51 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053052 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +020053 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053054
55 /* Phyadr read request */
Albert Aribaudd44265a2010-07-12 22:24:28 +020056 if (phy_adr == MV_PHY_ADR_REQUEST &&
57 reg_ofs == MV_PHY_ADR_REQUEST) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +053058 /* */
Albert Aribaudd44265a2010-07-12 22:24:28 +020059 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053060 return 0;
61 }
62 /* check parameters */
63 if (phy_adr > PHYADR_MASK) {
64 printf("Err..(%s) Invalid PHY address %d\n",
65 __FUNCTION__, phy_adr);
66 return -EFAULT;
67 }
68 if (reg_ofs > PHYREG_MASK) {
69 printf("Err..(%s) Invalid register offset %d\n",
70 __FUNCTION__, reg_ofs);
71 return -EFAULT;
72 }
73
Albert Aribaudd44265a2010-07-12 22:24:28 +020074 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053075 /* wait till the SMI is not busy */
76 do {
77 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020078 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053079 if (timeout-- == 0) {
80 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
81 return -EFAULT;
82 }
Albert Aribaudd44265a2010-07-12 22:24:28 +020083 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053084
85 /* fill the phy address and regiser offset and read opcode */
Albert Aribaudd44265a2010-07-12 22:24:28 +020086 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
87 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
88 | MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053089
90 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020091 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053092
93 /*wait till read value is ready */
Albert Aribaudd44265a2010-07-12 22:24:28 +020094 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053095
96 do {
97 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020098 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053099 if (timeout-- == 0) {
100 printf("Err..(%s) SMI read ready timeout\n",
101 __FUNCTION__);
102 return -EFAULT;
103 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200104 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530105
106 /* Wait for the data to update in the SMI register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200107 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
108 ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530109
Albert Aribaudd44265a2010-07-12 22:24:28 +0200110 *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530111
112 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
113 reg_ofs, *data);
114
115 return 0;
116}
117
118/*
119 * smi_reg_write - imiiphy_write callback function.
120 *
121 * Returns 0 if write succeed, -EINVAL on bad parameters
122 * -ETIME on timeout
123 */
Mike Frysinger5700bb62010-07-27 18:35:08 -0400124static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530125{
126 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200127 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
128 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530129 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200130 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530131
132 /* Phyadr write request*/
Albert Aribaudd44265a2010-07-12 22:24:28 +0200133 if (phy_adr == MV_PHY_ADR_REQUEST &&
134 reg_ofs == MV_PHY_ADR_REQUEST) {
135 MVGBE_REG_WR(regs->phyadr, data);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530136 return 0;
137 }
138
139 /* check parameters */
140 if (phy_adr > PHYADR_MASK) {
141 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
142 return -EINVAL;
143 }
144 if (reg_ofs > PHYREG_MASK) {
145 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
146 return -EINVAL;
147 }
148
149 /* wait till the SMI is not busy */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200150 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530151 do {
152 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200153 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530154 if (timeout-- == 0) {
155 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
156 return -ETIME;
157 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200158 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530159
160 /* fill the phy addr and reg offset and write opcode and data */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200161 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
162 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
163 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
164 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530165
166 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200167 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530168
169 return 0;
170}
Stefan Biglercc796972012-03-26 00:02:13 +0000171#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530172
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100173#if defined(CONFIG_PHYLIB)
174int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
175 int reg_addr)
176{
177 u16 data;
178 int ret;
179 ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
180 if (ret)
181 return ret;
182 return data;
183}
184
185int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
186 int reg_addr, u16 data)
187{
188 return smi_reg_write(bus->name, phy_addr, reg_addr, data);
189}
190#endif
191
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530192/* Stop and checks all queues */
193static void stop_queue(u32 * qreg)
194{
195 u32 reg_data;
196
197 reg_data = readl(qreg);
198
199 if (reg_data & 0xFF) {
200 /* Issue stop command for active channels only */
201 writel((reg_data << 8), qreg);
202
203 /* Wait for all queue activity to terminate. */
204 do {
205 /*
206 * Check port cause register that all queues
207 * are stopped
208 */
209 reg_data = readl(qreg);
210 }
211 while (reg_data & 0xFF);
212 }
213}
214
215/*
216 * set_access_control - Config address decode parameters for Ethernet unit
217 *
218 * This function configures the address decode parameters for the Gigabit
219 * Ethernet Controller according the given parameters struct.
220 *
221 * @regs Register struct pointer.
222 * @param Address decode parameter struct.
223 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200224static void set_access_control(struct mvgbe_registers *regs,
225 struct mvgbe_winparam *param)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530226{
227 u32 access_prot_reg;
228
229 /* Set access control register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200230 access_prot_reg = MVGBE_REG_RD(regs->epap);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530231 /* clear window permission */
232 access_prot_reg &= (~(3 << (param->win * 2)));
233 access_prot_reg |= (param->access_ctrl << (param->win * 2));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200234 MVGBE_REG_WR(regs->epap, access_prot_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530235
236 /* Set window Size reg (SR) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200237 MVGBE_REG_WR(regs->barsz[param->win].size,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530238 (((param->size / 0x10000) - 1) << 16));
239
240 /* Set window Base address reg (BA) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200241 MVGBE_REG_WR(regs->barsz[param->win].bar,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530242 (param->target | param->attrib | param->base_addr));
243 /* High address remap reg (HARR) */
244 if (param->win < 4)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200245 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530246
247 /* Base address enable reg (BARER) */
248 if (param->enable == 1)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200249 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530250 else
Albert Aribaudd44265a2010-07-12 22:24:28 +0200251 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530252}
253
Albert Aribaudd44265a2010-07-12 22:24:28 +0200254static void set_dram_access(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530255{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200256 struct mvgbe_winparam win_param;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530257 int i;
258
259 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
260 /* Set access parameters for DRAM bank i */
261 win_param.win = i; /* Use Ethernet window i */
262 /* Window target - DDR */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200263 win_param.target = MVGBE_TARGET_DRAM;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530264 /* Enable full access */
265 win_param.access_ctrl = EWIN_ACCESS_FULL;
266 win_param.high_addr = 0;
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200267 /* Get bank base and size */
268 win_param.base_addr = gd->bd->bi_dram[i].start;
269 win_param.size = gd->bd->bi_dram[i].size;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530270 if (win_param.size == 0)
271 win_param.enable = 0;
272 else
273 win_param.enable = 1; /* Enable the access */
274
275 /* Enable DRAM bank */
276 switch (i) {
277 case 0:
278 win_param.attrib = EBAR_DRAM_CS0;
279 break;
280 case 1:
281 win_param.attrib = EBAR_DRAM_CS1;
282 break;
283 case 2:
284 win_param.attrib = EBAR_DRAM_CS2;
285 break;
286 case 3:
287 win_param.attrib = EBAR_DRAM_CS3;
288 break;
289 default:
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200290 /* invalid bank, disable access */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530291 win_param.enable = 0;
292 win_param.attrib = 0;
293 break;
294 }
295 /* Set the access control for address window(EPAPR) RD/WR */
296 set_access_control(regs, &win_param);
297 }
298}
299
300/*
301 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
302 *
303 * Go through all the DA filter tables (Unicast, Special Multicast & Other
304 * Multicast) and set each entry to 0.
305 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200306static void port_init_mac_tables(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530307{
308 int table_index;
309
310 /* Clear DA filter unicast table (Ex_dFUT) */
311 for (table_index = 0; table_index < 4; ++table_index)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200312 MVGBE_REG_WR(regs->dfut[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530313
314 for (table_index = 0; table_index < 64; ++table_index) {
315 /* Clear DA filter special multicast table (Ex_dFSMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200316 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530317 /* Clear DA filter other multicast table (Ex_dFOMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200318 MVGBE_REG_WR(regs->dfomt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530319 }
320}
321
322/*
323 * port_uc_addr - This function Set the port unicast address table
324 *
325 * This function locates the proper entry in the Unicast table for the
326 * specified MAC nibble and sets its properties according to function
327 * parameters.
328 * This function add/removes MAC addresses from the port unicast address
329 * table.
330 *
331 * @uc_nibble Unicast MAC Address last nibble.
332 * @option 0 = Add, 1 = remove address.
333 *
334 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
335 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200336static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530337 int option)
338{
339 u32 unicast_reg;
340 u32 tbl_offset;
341 u32 reg_offset;
342
343 /* Locate the Unicast table entry */
344 uc_nibble = (0xf & uc_nibble);
345 /* Register offset from unicast table base */
346 tbl_offset = (uc_nibble / 4);
347 /* Entry offset within the above register */
348 reg_offset = uc_nibble % 4;
349
350 switch (option) {
351 case REJECT_MAC_ADDR:
352 /*
353 * Clear accepts frame bit at specified unicast
354 * DA table entry
355 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200356 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530357 unicast_reg &= (0xFF << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200358 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530359 break;
360 case ACCEPT_MAC_ADDR:
361 /* Set accepts frame bit at unicast DA filter table entry */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200362 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530363 unicast_reg &= (0xFF << (8 * reg_offset));
364 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200365 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530366 break;
367 default:
368 return 0;
369 }
370 return 1;
371}
372
373/*
374 * port_uc_addr_set - This function Set the port Unicast address.
375 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200376static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530377{
378 u32 mac_h;
379 u32 mac_l;
380
381 mac_l = (p_addr[4] << 8) | (p_addr[5]);
382 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
383 (p_addr[3] << 0);
384
Albert Aribaudd44265a2010-07-12 22:24:28 +0200385 MVGBE_REG_WR(regs->macal, mac_l);
386 MVGBE_REG_WR(regs->macah, mac_h);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530387
388 /* Accept frames of this address */
389 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
390}
391
392/*
Albert Aribaudd44265a2010-07-12 22:24:28 +0200393 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530394 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200395static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530396{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200397 struct mvgbe_rxdesc *p_rx_desc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530398 int i;
399
400 /* initialize the Rx descriptors ring */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200401 p_rx_desc = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530402 for (i = 0; i < RINGSZ; i++) {
403 p_rx_desc->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200404 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530405 p_rx_desc->buf_size = PKTSIZE_ALIGN;
406 p_rx_desc->byte_cnt = 0;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200407 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530408 if (i == (RINGSZ - 1))
Albert Aribaudd44265a2010-07-12 22:24:28 +0200409 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530410 else {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200411 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
412 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530413 p_rx_desc = p_rx_desc->nxtdesc_p;
414 }
415 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200416 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530417}
418
Albert Aribaudd44265a2010-07-12 22:24:28 +0200419static int mvgbe_init(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530420{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200421 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
422 struct mvgbe_registers *regs = dmvgbe->regs;
Sascha Silbe0611c602013-08-11 17:08:23 +0200423#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
424 !defined(CONFIG_PHYLIB) && \
425 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200426 int i;
Prafulla Wadaskaraba82372009-09-09 15:59:19 +0530427#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530428 /* setup RX rings */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200429 mvgbe_init_rx_desc_ring(dmvgbe);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530430
431 /* Clear the ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200432 MVGBE_REG_WR(regs->ic, 0);
433 MVGBE_REG_WR(regs->ice, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530434 /* Unmask RX buffer and TX end interrupt */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200435 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530436 /* Unmask phy and link status changes interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200437 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530438
439 set_dram_access(regs);
440 port_init_mac_tables(regs);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200441 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530442
443 /* Assign port configuration and command. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200444 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
445 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
446 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530447
448 /* Assign port SDMA configuration */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200449 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
450 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
451 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
452 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530453 /* Turn off the port/RXUQ bandwidth limitation */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200454 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530455
456 /* Set maximum receive buffer to 9700 bytes */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200457 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
458 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530459
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530460 /* Enable port initially */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200461 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530462
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530463 /*
464 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
465 * disable the leaky bucket mechanism .
466 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200467 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530468
469 /* Assignment of Rx CRDB of given RXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200470 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200471 /* ensure previous write is done before enabling Rx DMA */
472 isb();
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530473 /* Enable port Rx. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200474 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530475
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100476#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
477 !defined(CONFIG_PHYLIB) && \
478 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200479 /* Wait up to 5s for the link status */
480 for (i = 0; i < 5; i++) {
481 u16 phyadr;
482
Albert Aribaudd44265a2010-07-12 22:24:28 +0200483 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
484 MV_PHY_ADR_REQUEST, &phyadr);
Simon Kagstromcad713b2009-08-20 10:13:06 +0200485 /* Return if we get link up */
486 if (miiphy_link(dev->name, phyadr))
487 return 0;
488 udelay(1000000);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530489 }
Simon Kagstromcad713b2009-08-20 10:13:06 +0200490
491 printf("No link on %s\n", dev->name);
492 return -1;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530493#endif
494 return 0;
495}
496
Albert Aribaudd44265a2010-07-12 22:24:28 +0200497static int mvgbe_halt(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530498{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200499 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
500 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530501
502 /* Disable all gigE address decoder */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200503 MVGBE_REG_WR(regs->bare, 0x3f);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530504
505 stop_queue(&regs->tqc);
506 stop_queue(&regs->rqc);
507
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530508 /* Disable port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200509 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530510 /* Set port is not reset */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200511 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530512#ifdef CONFIG_SYS_MII_MODE
513 /* Set MMI interface up */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200514 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530515#endif
516 /* Disable & mask ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200517 MVGBE_REG_WR(regs->ic, 0);
518 MVGBE_REG_WR(regs->ice, 0);
519 MVGBE_REG_WR(regs->pim, 0);
520 MVGBE_REG_WR(regs->peim, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530521
522 return 0;
523}
524
Albert Aribaudd44265a2010-07-12 22:24:28 +0200525static int mvgbe_write_hwaddr(struct eth_device *dev)
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530526{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200527 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
528 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530529
530 /* Programs net device MAC address after initialization */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200531 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530532 return 0;
533}
534
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000535static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530536{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200537 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
538 struct mvgbe_registers *regs = dmvgbe->regs;
539 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200540 void *p = (void *)dataptr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200541 u32 cmd_sts;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000542 u32 txuq0_reg_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530543
Simon Kagstrom477fa632009-08-20 10:14:11 +0200544 /* Copy buffer if it's misaligned */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530545 if ((u32) dataptr & 0x07) {
Simon Kagstrom477fa632009-08-20 10:14:11 +0200546 if (datasize > PKTSIZE_ALIGN) {
547 printf("Non-aligned data too large (%d)\n",
548 datasize);
549 return -1;
550 }
551
Albert Aribaudd44265a2010-07-12 22:24:28 +0200552 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
553 p = dmvgbe->p_aligned_txbuf;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530554 }
Simon Kagstrom477fa632009-08-20 10:14:11 +0200555
Albert Aribaudd44265a2010-07-12 22:24:28 +0200556 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
557 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
558 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
559 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200560 p_txdesc->buf_ptr = (u8 *) p;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530561 p_txdesc->byte_cnt = datasize;
562
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200563 /* Set this tc desc as zeroth TXUQ */
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000564 txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
565 writel((u32) p_txdesc, txuq0_reg_addr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200566
567 /* ensure tx desc writes above are performed before we start Tx DMA */
568 isb();
569
570 /* Apply send command using zeroth TXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200571 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530572
573 /*
574 * wait for packet xmit completion
575 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200576 cmd_sts = readl(&p_txdesc->cmd_sts);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200577 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530578 /* return fail if error is detected */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200579 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
580 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
581 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530582 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
583 return -1;
584 }
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200585 cmd_sts = readl(&p_txdesc->cmd_sts);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530586 };
587 return 0;
588}
589
Albert Aribaudd44265a2010-07-12 22:24:28 +0200590static int mvgbe_recv(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530591{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200592 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
593 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200594 u32 cmd_sts;
595 u32 timeout = 0;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000596 u32 rxdesc_curr_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530597
598 /* wait untill rx packet available or timeout */
599 do {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200600 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530601 timeout++;
602 else {
603 debug("%s time out...\n", __FUNCTION__);
604 return -1;
605 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200606 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530607
608 if (p_rxdesc_curr->byte_cnt != 0) {
609 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
610 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
611 (u32) p_rxdesc_curr->buf_ptr,
612 (u32) p_rxdesc_curr->cmd_sts);
613 }
614
615 /*
616 * In case received a packet without first/last bits on
617 * OR the error summary bit is on,
618 * the packets needs to be dropeed.
619 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200620 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
621
622 if ((cmd_sts &
Albert Aribaudd44265a2010-07-12 22:24:28 +0200623 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
624 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530625
626 printf("Err..(%s) Dropping packet spread on"
627 " multiple descriptors\n", __FUNCTION__);
628
Albert Aribaudd44265a2010-07-12 22:24:28 +0200629 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530630
631 printf("Err..(%s) Dropping packet with errors\n",
632 __FUNCTION__);
633
634 } else {
635 /* !!! call higher layer processing */
636 debug("%s: Sending Received packet to"
637 " upper layer (NetReceive)\n", __FUNCTION__);
638
639 /* let the upper layer handle the packet */
640 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
641 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
642 }
643 /*
644 * free these descriptors and point next in the ring
645 */
646 p_rxdesc_curr->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200647 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530648 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
649 p_rxdesc_curr->byte_cnt = 0;
650
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000651 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
652 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200653
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530654 return 0;
655}
656
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100657#if defined(CONFIG_PHYLIB)
658int mvgbe_phylib_init(struct eth_device *dev, int phyid)
659{
660 struct mii_dev *bus;
661 struct phy_device *phydev;
662 int ret;
663
664 bus = mdio_alloc();
665 if (!bus) {
666 printf("mdio_alloc failed\n");
667 return -ENOMEM;
668 }
669 bus->read = mvgbe_phy_read;
670 bus->write = mvgbe_phy_write;
671 sprintf(bus->name, dev->name);
672
673 ret = mdio_register(bus);
674 if (ret) {
675 printf("mdio_register failed\n");
676 free(bus);
677 return -ENOMEM;
678 }
679
680 /* Set phy address of the port */
681 mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
682
683 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
684 if (!phydev) {
685 printf("phy_connect failed\n");
686 return -ENODEV;
687 }
688
689 phy_config(phydev);
690 phy_startup(phydev);
691
692 return 0;
693}
694#endif
695
Albert Aribaudd44265a2010-07-12 22:24:28 +0200696int mvgbe_initialize(bd_t *bis)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530697{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200698 struct mvgbe_device *dmvgbe;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530699 struct eth_device *dev;
700 int devnum;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200701 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530702
Albert Aribaudd44265a2010-07-12 22:24:28 +0200703 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530704 /*skip if port is configured not to use */
705 if (used_ports[devnum] == 0)
706 continue;
707
Albert Aribaudd44265a2010-07-12 22:24:28 +0200708 dmvgbe = malloc(sizeof(struct mvgbe_device));
709
710 if (!dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530711 goto error1;
712
Albert Aribaudd44265a2010-07-12 22:24:28 +0200713 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530714
Albert Aribaudd44265a2010-07-12 22:24:28 +0200715 dmvgbe->p_rxdesc =
716 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
717 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
718
719 if (!dmvgbe->p_rxdesc)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530720 goto error2;
721
Albert Aribaudd44265a2010-07-12 22:24:28 +0200722 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
723 RINGSZ*PKTSIZE_ALIGN + 1);
724
725 if (!dmvgbe->p_rxbuf)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530726 goto error3;
727
Albert Aribaudd44265a2010-07-12 22:24:28 +0200728 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
729
730 if (!dmvgbe->p_aligned_txbuf)
Simon Kagstrom477fa632009-08-20 10:14:11 +0200731 goto error4;
732
Albert Aribaudd44265a2010-07-12 22:24:28 +0200733 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
734 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
735
736 if (!dmvgbe->p_txdesc) {
737 free(dmvgbe->p_aligned_txbuf);
738error4:
739 free(dmvgbe->p_rxbuf);
740error3:
741 free(dmvgbe->p_rxdesc);
742error2:
743 free(dmvgbe);
744error1:
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530745 printf("Err.. %s Failed to allocate memory\n",
746 __FUNCTION__);
747 return -1;
748 }
749
Albert Aribaudd44265a2010-07-12 22:24:28 +0200750 dev = &dmvgbe->dev;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530751
Mike Frysingerf6add132011-11-10 14:11:04 +0000752 /* must be less than sizeof(dev->name) */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530753 sprintf(dev->name, "egiga%d", devnum);
754
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530755 switch (devnum) {
756 case 0:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200757 dmvgbe->regs = (void *)MVGBE0_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530758 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200759#if defined(MVGBE1_BASE)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530760 case 1:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200761 dmvgbe->regs = (void *)MVGBE1_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530762 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200763#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530764 default: /* this should never happen */
765 printf("Err..(%s) Invalid device number %d\n",
766 __FUNCTION__, devnum);
767 return -1;
768 }
769
Albert Aribaudd44265a2010-07-12 22:24:28 +0200770 dev->init = (void *)mvgbe_init;
771 dev->halt = (void *)mvgbe_halt;
772 dev->send = (void *)mvgbe_send;
773 dev->recv = (void *)mvgbe_recv;
774 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530775
776 eth_register(dev);
777
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100778#if defined(CONFIG_PHYLIB)
779 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
780#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530781 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
782 /* Set phy address of the port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200783 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
784 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530785#endif
786 }
787 return 0;
Prafulla Wadaskar0b785dd2009-07-01 20:34:51 +0200788}