Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/arch/imx-regs.h> |
| 26 | #include <asm/arch/mx6x_pins.h> |
| 27 | #include <asm/arch/iomux-v3.h> |
| 28 | #include <asm/errno.h> |
| 29 | #include <asm/gpio.h> |
| 30 | #include <mmc.h> |
| 31 | #include <fsl_esdhc.h> |
Troy Kisky | 2bf3359 | 2012-02-07 14:08:50 +0000 | [diff] [blame^] | 32 | #include <micrel.h> |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 33 | #include <miiphy.h> |
| 34 | #include <netdev.h> |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | |
| 37 | #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 38 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 39 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 40 | |
| 41 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 42 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| 43 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 44 | |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 45 | #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 46 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 47 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 48 | |
Eric Nelson | 373a1d8 | 2012-01-31 07:52:05 +0000 | [diff] [blame] | 49 | #define SPI_PAD_CTRL (PAD_CTL_HYS | \ |
| 50 | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ |
| 51 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 52 | |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 53 | int dram_init(void) |
| 54 | { |
| 55 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 56 | |
| 57 | return 0; |
| 58 | } |
| 59 | |
Troy Kisky | 8e7d7b6 | 2012-01-12 23:49:25 +0000 | [diff] [blame] | 60 | iomux_v3_cfg_t uart1_pads[] = { |
| 61 | MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 62 | MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 63 | }; |
| 64 | |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 65 | iomux_v3_cfg_t uart2_pads[] = { |
| 66 | MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 67 | MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 68 | }; |
| 69 | |
| 70 | iomux_v3_cfg_t usdhc3_pads[] = { |
| 71 | MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 72 | MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 73 | MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 74 | MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 75 | MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 76 | MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 77 | MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| 78 | }; |
| 79 | |
| 80 | iomux_v3_cfg_t usdhc4_pads[] = { |
| 81 | MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 82 | MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 83 | MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 84 | MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 85 | MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 86 | MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 87 | MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| 88 | }; |
| 89 | |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 90 | iomux_v3_cfg_t enet_pads1[] = { |
| 91 | MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 92 | MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 93 | MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 94 | MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 95 | MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 96 | MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 97 | MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 98 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 99 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 100 | /* pin 35 - 1 (PHY_AD2) on reset */ |
| 101 | MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 102 | /* pin 32 - 1 - (MODE0) all */ |
| 103 | MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 104 | /* pin 31 - 1 - (MODE1) all */ |
| 105 | MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 106 | /* pin 28 - 1 - (MODE2) all */ |
| 107 | MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 108 | /* pin 27 - 1 - (MODE3) all */ |
| 109 | MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 110 | /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ |
| 111 | MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 112 | /* pin 42 PHY nRST */ |
| 113 | MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 114 | }; |
| 115 | |
| 116 | iomux_v3_cfg_t enet_pads2[] = { |
| 117 | MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 118 | MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 119 | MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 120 | MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 121 | MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 122 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 123 | }; |
| 124 | |
| 125 | static void setup_iomux_enet(void) |
| 126 | { |
| 127 | gpio_direction_output(87, 0); /* GPIO 3-23 */ |
| 128 | gpio_direction_output(190, 1); /* GPIO 6-30 */ |
| 129 | gpio_direction_output(185, 1); /* GPIO 6-25 */ |
| 130 | gpio_direction_output(187, 1); /* GPIO 6-27 */ |
| 131 | gpio_direction_output(188, 1); /* GPIO 6-28*/ |
| 132 | gpio_direction_output(189, 1); /* GPIO 6-29 */ |
| 133 | imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); |
| 134 | gpio_direction_output(184, 1); /* GPIO 6-24 */ |
| 135 | |
| 136 | /* Need delay 10ms according to KSZ9021 spec */ |
| 137 | udelay(1000 * 10); |
| 138 | gpio_direction_output(87, 1); /* GPIO 3-23 */ |
| 139 | |
| 140 | imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); |
| 141 | } |
| 142 | |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 143 | static void setup_iomux_uart(void) |
| 144 | { |
Troy Kisky | 8e7d7b6 | 2012-01-12 23:49:25 +0000 | [diff] [blame] | 145 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 146 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 147 | } |
| 148 | |
| 149 | #ifdef CONFIG_FSL_ESDHC |
| 150 | struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| 151 | {USDHC3_BASE_ADDR, 1}, |
| 152 | {USDHC4_BASE_ADDR, 1}, |
| 153 | }; |
| 154 | |
| 155 | int board_mmc_getcd(struct mmc *mmc) |
| 156 | { |
| 157 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 158 | int ret; |
| 159 | |
| 160 | if (cfg->esdhc_base == USDHC3_BASE_ADDR) { |
| 161 | gpio_direction_input(192); /*GPIO7_0*/ |
| 162 | ret = !gpio_get_value(192); |
| 163 | } else { |
| 164 | gpio_direction_input(38); /*GPIO2_6*/ |
| 165 | ret = !gpio_get_value(38); |
| 166 | } |
| 167 | |
| 168 | return ret; |
| 169 | } |
| 170 | |
| 171 | int board_mmc_init(bd_t *bis) |
| 172 | { |
| 173 | s32 status = 0; |
| 174 | u32 index = 0; |
| 175 | |
| 176 | for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
| 177 | switch (index) { |
| 178 | case 0: |
| 179 | imx_iomux_v3_setup_multiple_pads( |
| 180 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 181 | break; |
| 182 | case 1: |
| 183 | imx_iomux_v3_setup_multiple_pads( |
| 184 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 185 | break; |
| 186 | default: |
| 187 | printf("Warning: you configured more USDHC controllers" |
| 188 | "(%d) then supported by the board (%d)\n", |
| 189 | index + 1, CONFIG_SYS_FSL_USDHC_NUM); |
| 190 | return status; |
| 191 | } |
| 192 | |
| 193 | status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
| 194 | } |
| 195 | |
| 196 | return status; |
| 197 | } |
| 198 | #endif |
| 199 | |
Eric Nelson | 373a1d8 | 2012-01-31 07:52:05 +0000 | [diff] [blame] | 200 | #ifdef CONFIG_MXC_SPI |
| 201 | iomux_v3_cfg_t ecspi1_pads[] = { |
| 202 | /* SS1 */ |
| 203 | MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 204 | MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 205 | MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 206 | MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 207 | }; |
| 208 | |
| 209 | void setup_spi(void) |
| 210 | { |
Eric Nelson | ba54b92 | 2012-01-31 07:52:09 +0000 | [diff] [blame] | 211 | gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); |
Eric Nelson | 373a1d8 | 2012-01-31 07:52:05 +0000 | [diff] [blame] | 212 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, |
| 213 | ARRAY_SIZE(ecspi1_pads)); |
| 214 | } |
| 215 | #endif |
| 216 | |
Troy Kisky | 2bf3359 | 2012-02-07 14:08:50 +0000 | [diff] [blame^] | 217 | int board_phy_config(struct phy_device *phydev) |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 218 | { |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 219 | /* min rx data delay */ |
Troy Kisky | 2bf3359 | 2012-02-07 14:08:50 +0000 | [diff] [blame^] | 220 | ksz9021_phy_extended_write(phydev, |
| 221 | MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); |
| 222 | /* min tx data delay */ |
| 223 | ksz9021_phy_extended_write(phydev, |
| 224 | MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); |
| 225 | /* max rx/tx clock delay, min rx/tx control */ |
| 226 | ksz9021_phy_extended_write(phydev, |
| 227 | MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); |
| 228 | if (phydev->drv->config) |
| 229 | phydev->drv->config(phydev); |
| 230 | |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | int board_eth_init(bd_t *bis) |
| 235 | { |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 236 | int ret; |
| 237 | |
| 238 | setup_iomux_enet(); |
| 239 | |
| 240 | ret = cpu_eth_init(bis); |
Troy Kisky | 2bf3359 | 2012-02-07 14:08:50 +0000 | [diff] [blame^] | 241 | if (ret) |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 242 | printf("FEC MXC: %s:failed\n", __func__); |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 243 | |
Eric Nelson | 373a1d8 | 2012-01-31 07:52:05 +0000 | [diff] [blame] | 244 | #ifdef CONFIG_MXC_SPI |
| 245 | setup_spi(); |
| 246 | #endif |
| 247 | |
Jason Liu | 2af81e2 | 2012-01-12 22:56:16 +0000 | [diff] [blame] | 248 | return 0; |
| 249 | } |
| 250 | |
Jason Liu | bc5833c | 2011-12-29 06:34:19 +0000 | [diff] [blame] | 251 | int board_early_init_f(void) |
| 252 | { |
| 253 | setup_iomux_uart(); |
| 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | |
| 258 | int board_init(void) |
| 259 | { |
| 260 | /* address of boot parameters */ |
| 261 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | int checkboard(void) |
| 267 | { |
| 268 | puts("Board: MX6Q-Sabre Lite\n"); |
| 269 | |
| 270 | return 0; |
| 271 | } |