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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roesefc84a842008-03-07 08:01:43 +01002 * (C) Copyright 2006-2008
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
Larry Johnson214398d2008-01-18 21:49:05 -050025/*
Stefan Roesee8025942007-01-30 17:06:10 +010026 * sequoia.h - configuration for Sequoia & Rainier boards
Larry Johnson214398d2008-01-18 21:49:05 -050027 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020028#ifndef __CONFIG_H
29#define __CONFIG_H
30
Larry Johnson214398d2008-01-18 21:49:05 -050031/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020032 * High Level Configuration Options
Larry Johnson214398d2008-01-18 21:49:05 -050033 */
Stefan Roesee8025942007-01-30 17:06:10 +010034/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
Stefan Roese854bc8d2006-09-13 13:51:58 +020035#ifndef CONFIG_RAINIER
Larry Johnson214398d2008-01-18 21:49:05 -050036#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roese72675dc2008-06-06 15:55:21 +020037#define CONFIG_HOSTNAME sequoia
Stefan Roese854bc8d2006-09-13 13:51:58 +020038#else
Larry Johnson214398d2008-01-18 21:49:05 -050039#define CONFIG_440GRX 1 /* Specific PPC440GRx */
Stefan Roese72675dc2008-06-06 15:55:21 +020040#define CONFIG_HOSTNAME rainier
Stefan Roese854bc8d2006-09-13 13:51:58 +020041#endif
Larry Johnson214398d2008-01-18 21:49:05 -050042#define CONFIG_440 1 /* ... PPC440 family */
43#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese72675dc2008-06-06 15:55:21 +020044
45/*
46 * Include common defines/options for all AMCC eval boards
47 */
48#include "amcc-common.h"
49
Jeffrey Manne3b8c782007-05-05 08:32:14 +020050/* Detect Sequoia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
Jeffrey Mann193b4a32007-05-07 19:42:49 +020052 33333333 : 33000000)
Stefan Roese887e2ec2006-09-07 11:51:23 +020053
Anatolij Gustschinbc778812008-02-21 12:52:29 +010054/*
55 * Define this if you want support for video console with radeon 9200 pci card
56 * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
57 */
58#undef CONFIG_VIDEO
59
60#ifdef CONFIG_VIDEO
Stefan Roesed25dfe02007-10-31 17:57:52 +010061/*
62 * 44x dcache supported is working now on sequoia, but we don't enable
63 * it yet since it needs further testing
64 */
Larry Johnson214398d2008-01-18 21:49:05 -050065#define CONFIG_4xx_DCACHE /* enable dcache */
Stefan Roesed25dfe02007-10-31 17:57:52 +010066#endif
67
Larry Johnson214398d2008-01-18 21:49:05 -050068#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
69#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roese887e2ec2006-09-07 11:51:23 +020070
Larry Johnson214398d2008-01-18 21:49:05 -050071/*
72 * Base addresses -- Note these are effective addresses where the actual
73 * resources get mapped (not physical addresses).
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
76#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
77#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
78#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
79#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
80#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
81#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
82#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
83#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
84#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
85#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese887e2ec2006-09-07 11:51:23 +020086
87/* Don't change either of these */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
Stefan Roese887e2ec2006-09-07 11:51:23 +020089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_USB2D0_BASE 0xe0000100
91#define CONFIG_SYS_USB_DEVICE 0xe0000000
92#define CONFIG_SYS_USB_HOST 0xe0000400
93#define CONFIG_SYS_BCSR_BASE 0xc0000000
Stefan Roese887e2ec2006-09-07 11:51:23 +020094
Larry Johnson214398d2008-01-18 21:49:05 -050095/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020096 * Initial RAM & stack pointer
Larry Johnson214398d2008-01-18 21:49:05 -050097 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020098/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
100#define CONFIG_SYS_INIT_RAM_END (4 << 10)
101#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
102#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
103#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
Stefan Roese887e2ec2006-09-07 11:51:23 +0200104
Larry Johnson214398d2008-01-18 21:49:05 -0500105/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200106 * Serial Port
Larry Johnson214398d2008-01-18 21:49:05 -0500107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200109/* define this if you want console on UART1 */
110#undef CONFIG_UART1_CONSOLE
111
Larry Johnson214398d2008-01-18 21:49:05 -0500112/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200113 * Environment
Larry Johnson214398d2008-01-18 21:49:05 -0500114 */
Stefan Roesed8731332009-05-11 13:46:14 +0200115#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
116#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
117#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
118#elif defined(CONFIG_SYS_RAMBOOT)
119#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
120#define CONFIG_ENV_SIZE (8 << 10)
121/*
122 * In RAM-booting version, we have no environment storage. So we need to
123 * provide at least preliminary MAC addresses for the 4xx EMAC driver to
124 * register the interfaces. Those two addresses are generated via the
125 * tools/gen_eth_addr tool and should only be used in a closed laboratory
126 * environment.
127 */
128#define CONFIG_ETHADDR 4a:56:49:22:3e:43
129#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
Stefan Roese887e2ec2006-09-07 11:51:23 +0200130#else
Stefan Roesed8731332009-05-11 13:46:14 +0200131#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200132#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200133
Stefan Roesed8731332009-05-11 13:46:14 +0200134#if defined(CONFIG_CMD_FLASH)
Larry Johnson214398d2008-01-18 21:49:05 -0500135/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200136 * FLASH related
Larry Johnson214398d2008-01-18 21:49:05 -0500137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200139#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
144#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
150#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
153#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200154
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200155#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200156#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200158#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159
160/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
162#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200163#endif
Stefan Roesed8731332009-05-11 13:46:14 +0200164#endif /* CONFIG_CMD_FLASH */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200165
Stefan Roese887e2ec2006-09-07 11:51:23 +0200166/*
167 * IPL (Initial Program Loader, integrated inside CPU)
168 * Will load first 4k from NAND (SPL) into cache and execute it from there.
169 *
170 * SPL (Secondary Program Loader)
171 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
172 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
173 * controller and the NAND controller so that the special U-Boot image can be
174 * loaded from NAND to SDRAM.
175 *
176 * NUB (NAND U-Boot)
177 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
178 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
179 *
180 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
181 * set up. While still running from cache, I experienced problems accessing
182 * the NAND controller. sr - 2006-08-25
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
185#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
186#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
187#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
188#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
Larry Johnson214398d2008-01-18 21:49:05 -0500189 /* this addr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200191
192/*
193 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
196#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200197
198/*
199 * Now the NAND chip has to be defined (no autodetection used!)
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
202#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
203#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
204#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
205#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_NAND_ECCSIZE 256
208#define CONFIG_SYS_NAND_ECCBYTES 3
209#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
210#define CONFIG_SYS_NAND_OOBSIZE 16
211#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
212#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Stefan Roese9d909602007-06-01 15:29:04 +0200213
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200214#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roesed12ae802006-09-12 20:19:10 +0200215/*
216 * For NAND booting the environment is embedded in the U-Boot image. Please take
217 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
220#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200222#endif
223
Larry Johnson214398d2008-01-18 21:49:05 -0500224/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200225 * DDR SDRAM
Larry Johnson214398d2008-01-18 21:49:05 -0500226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Stefan Roesed8731332009-05-11 13:46:14 +0200228#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
229 !defined(CONFIG_SYS_RAMBOOT)
Larry Johnson214398d2008-01-18 21:49:05 -0500230#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roese02388982007-01-05 10:38:05 +0100231#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roese14f73ca2008-03-26 10:14:11 +0100233 /* 440EPx errata CHIP 11 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200234
Larry Johnson214398d2008-01-18 21:49:05 -0500235/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200236 * I2C
Larry Johnson214398d2008-01-18 21:49:05 -0500237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_I2C_MULTI_EEPROMS
241#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
242#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
243#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
244#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese887e2ec2006-09-07 11:51:23 +0200245
Stefan Roesecfc25872009-10-19 16:19:36 +0200246/* I2C bootstrap EEPROM */
247#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
248#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
249#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
250
Stefan Roese887e2ec2006-09-07 11:51:23 +0200251/* I2C SYSMON (LM75, AD7414 is almost compatible) */
Larry Johnson214398d2008-01-18 21:49:05 -0500252#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
253#define CONFIG_DTT_AD7414 1 /* use AD7414 */
254#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_DTT_MAX_TEMP 70
256#define CONFIG_SYS_DTT_LOW_TEMP -30
257#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese887e2ec2006-09-07 11:51:23 +0200258
Stefan Roese72675dc2008-06-06 15:55:21 +0200259/*
260 * Default environment variables
261 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200262#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese72675dc2008-06-06 15:55:21 +0200263 CONFIG_AMCC_DEF_ENV \
264 CONFIG_AMCC_DEF_ENV_POWERPC \
265 CONFIG_AMCC_DEF_ENV_PPC_OLD \
266 CONFIG_AMCC_DEF_ENV_NOR_UPD \
267 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese4ef62512006-11-20 20:39:52 +0100268 "kernel_addr=FC000000\0" \
269 "ramdisk_addr=FC180000\0" \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200270 ""
Stefan Roese887e2ec2006-09-07 11:51:23 +0200271
272#define CONFIG_M88E1111_PHY 1
273#define CONFIG_IBM_EMAC4_V4 1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200274#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
275
Larry Johnson214398d2008-01-18 21:49:05 -0500276#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200277#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
278
279#define CONFIG_HAS_ETH0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200280#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
281#define CONFIG_PHY1_ADDR 1
282
283/* USB */
Stefan Roese854bc8d2006-09-13 13:51:58 +0200284#ifdef CONFIG_440EPX
Chris Zhang559e2c82010-01-06 13:34:06 -0800285
286#undef CONFIG_USB_EHCI /* OHCI by default */
287
288#ifdef CONFIG_USB_EHCI
289#define CONFIG_USB_EHCI_PPC4XX
290#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
291#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
292#define CONFIG_EHCI_MMIO_BIG_ENDIAN
293#define CONFIG_EHCI_DESC_BIG_ENDIAN
294#ifdef CONFIG_4xx_DCACHE
295#define CONFIG_EHCI_DCACHE
296#endif
297#else /* CONFIG_USB_EHCI */
Matthias Fuchs2d146842007-11-09 15:37:53 +0100298#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs2d146842007-11-09 15:37:53 +0100300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
302#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
303#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
304#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
305#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Chris Zhang559e2c82010-01-06 13:34:06 -0800306#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200307
Chris Zhang559e2c82010-01-06 13:34:06 -0800308#define CONFIG_USB_STORAGE
Stefan Roese887e2ec2006-09-07 11:51:23 +0200309/* Comment this out to enable USB 1.1 device */
310#define USB_2_0_DEVICE
311
Stefan Roese854bc8d2006-09-13 13:51:58 +0200312#endif /* CONFIG_440EPX */
313
Stefan Roese887e2ec2006-09-07 11:51:23 +0200314/* Partitions */
315#define CONFIG_MAC_PARTITION
316#define CONFIG_DOS_PARTITION
317#define CONFIG_ISO_PARTITION
318
Jon Loeliger46da1e92007-07-04 22:33:30 -0500319/*
Stefan Roese72675dc2008-06-06 15:55:21 +0200320 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500321 */
Stefan Roesecfc25872009-10-19 16:19:36 +0200322#define CONFIG_CMD_CHIP_CONFIG
Jon Loeliger46da1e92007-07-04 22:33:30 -0500323#define CONFIG_CMD_DTT
Jon Loeliger46da1e92007-07-04 22:33:30 -0500324#define CONFIG_CMD_FAT
Jon Loeliger46da1e92007-07-04 22:33:30 -0500325#define CONFIG_CMD_NAND
Jon Loeliger46da1e92007-07-04 22:33:30 -0500326#define CONFIG_CMD_PCI
Jon Loeliger46da1e92007-07-04 22:33:30 -0500327#define CONFIG_CMD_SDRAM
328
329#ifdef CONFIG_440EPX
330#define CONFIG_CMD_USB
331#endif
332
Stefan Roese9de469b2007-08-16 10:18:33 +0200333#ifndef CONFIG_RAINIER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
Stefan Roese9de469b2007-08-16 10:18:33 +0200335#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_POST_FPU_ON 0
Stefan Roese9de469b2007-08-16 10:18:33 +0200337#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200338
Stefan Roese9a929172009-04-15 14:06:26 +0200339/*
340 * Don't run the memory POST on the NAND-booting version. It will
341 * overwrite part of the U-Boot image which is already loaded from NAND
342 * to SDRAM.
343 */
Stefan Roesed8731332009-05-11 13:46:14 +0200344#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
Stefan Roese9a929172009-04-15 14:06:26 +0200345#define CONFIG_SYS_POST_MEMORY_ON 0
346#else
347#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
348#endif
349
Igor Lisitsina11e0692007-03-28 19:06:19 +0400350/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
352 CONFIG_SYS_POST_CPU | \
353 CONFIG_SYS_POST_ETHER | \
Stefan Roese9a929172009-04-15 14:06:26 +0200354 CONFIG_SYS_POST_FPU_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 CONFIG_SYS_POST_I2C | \
Stefan Roese9a929172009-04-15 14:06:26 +0200356 CONFIG_SYS_POST_MEMORY_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357 CONFIG_SYS_POST_SPR | \
358 CONFIG_SYS_POST_UART)
Igor Lisitsina11e0692007-03-28 19:06:19 +0400359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Igor Lisitsina11e0692007-03-28 19:06:19 +0400361#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400365
Stefan Roese887e2ec2006-09-07 11:51:23 +0200366#define CONFIG_SUPPORT_VFAT
367
Larry Johnson214398d2008-01-18 21:49:05 -0500368/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200369 * PCI stuff
Larry Johnson214398d2008-01-18 21:49:05 -0500370 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200371/* General PCI */
Larry Johnson214398d2008-01-18 21:49:05 -0500372#define CONFIG_PCI /* include pci support */
373#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnson214398d2008-01-18 21:49:05 -0500375#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
377 /* CONFIG_SYS_PCI_MEMBASE */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200378/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_PCI_TARGET_INIT
380#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea760b022009-11-12 16:41:09 +0100381#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Stefan Roese887e2ec2006-09-07 11:51:23 +0200382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
384#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200385
386/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200387 * External Bus Controller (EBC) Setup
Larry Johnson214398d2008-01-18 21:49:05 -0500388 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200389
390/*
391 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
392 */
Stefan Roesed8731332009-05-11 13:46:14 +0200393#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
394 !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Larry Johnson214398d2008-01-18 21:49:05 -0500396/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_EBC_PB0AP 0x03017200
398#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200399
Larry Johnson214398d2008-01-18 21:49:05 -0500400/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_EBC_PB3AP 0x018003c0
402#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200403#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Larry Johnson214398d2008-01-18 21:49:05 -0500405/* Memory Bank 3 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_EBC_PB3AP 0x03017200
407#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200408
Larry Johnson214398d2008-01-18 21:49:05 -0500409/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_EBC_PB0AP 0x018003c0
411#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200412#endif
413
Larry Johnson214398d2008-01-18 21:49:05 -0500414/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_EBC_PB2AP 0x24814580
416#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_BCSR5_PCI66EN 0x80
Stefan Roese5a5958b2007-10-15 11:29:33 +0200419
Larry Johnson214398d2008-01-18 21:49:05 -0500420/*
Stefan Roese43a2b0e2006-10-20 14:28:52 +0200421 * NAND FLASH
Larry Johnson214398d2008-01-18 21:49:05 -0500422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
425#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese43a2b0e2006-10-20 14:28:52 +0200426
Larry Johnson214398d2008-01-18 21:49:05 -0500427/*
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500428 * PPC440 GPIO Configuration
429 */
430/* test-only: take GPIO init from pcs440ep ???? in config file */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500432{ \
433/* GPIO Core 0 */ \
434{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
435{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
436{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
437{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
438{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
439{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
440{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
441{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
442{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
443{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
444{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
445{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
446{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
447{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
448{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
449{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
450{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
451{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
452{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
453{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
454{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
455{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
456{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
457{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
458{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
459{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
460{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
461{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
462{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
463{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
464{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
465{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
466}, \
467{ \
468/* GPIO Core 1 */ \
469{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
470{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
Steven A. Falcoeab10072008-08-06 15:42:52 -0400471{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
472{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
473{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
474{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
475{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
476{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500477{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
478{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
479{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
480{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
481{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
482{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
483{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
484{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
485{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
486{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
487{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
488{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
489{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
490{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
491{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
492{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
493{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
494{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
495{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
496{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
497{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
498{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
499{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
500{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
501} \
502}
503
Anatolij Gustschinbc778812008-02-21 12:52:29 +0100504#ifdef CONFIG_VIDEO
505#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
506#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
507#define VIDEO_IO_OFFSET 0xe8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Anatolij Gustschinbc778812008-02-21 12:52:29 +0100509#define CONFIG_VIDEO_SW_CURSOR
510#define CONFIG_VIDEO_LOGO
511#define CONFIG_CFB_CONSOLE
512#define CONFIG_SPLASH_SCREEN
513#define CONFIG_VGA_AS_SINGLE_DEVICE
514#define CONFIG_CMD_BMP
515#endif
516
Larry Johnson214398d2008-01-18 21:49:05 -0500517#endif /* __CONFIG_H */