blob: e36e63e81e4ea48d74ca300be867ddce8e047718 [file] [log] [blame]
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Tom Rini65cc0e22022-11-16 13:10:41 -05009#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090010
11/*
12 * SDRAM (for initialize)
13 */
Tom Riniaa6e94d2022-11-16 13:10:37 -050014#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090015#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
Tom Rini1d457db2022-12-04 10:04:50 -050017#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090018
19#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
20
21/*
22 * Boot info
23 */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090024
25/*
26 * Hardware drivers support
27 */
28
29/* RTC */
Tom Rini65cc0e22022-11-16 13:10:41 -050030#define CFG_SYS_I2C_RTC_ADDR 0x51
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090031
32/* Serial (pl011) */
33#define UART_CLK (62500000)
Tom Rinif410d0a2022-12-04 10:13:30 -050034#define CFG_PL011_CLOCK UART_CLK
Tom Rinib8615742022-12-04 10:13:31 -050035#define CFG_PL01x_PORTS {(void *)(0x2a400000)}
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090036
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090037/* Support MTD */
Tom Rini65cc0e22022-11-16 13:10:41 -050038#define CFG_SYS_FLASH_BASE (0x08000000)
39#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090040
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090041/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090042
Jassi Brar6b403ca2023-05-31 00:29:56 -050043#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
Jassi Brar6b403ca2023-05-31 00:29:56 -050044#define DEVELOPERBOX_FIP_IMAGE_GUID \
45 EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
46 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
47#else
Sughosh Ganu741ef862022-04-15 11:29:34 +053048#define DEVELOPERBOX_FIP_IMAGE_GUID \
49 EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
50 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
Jassi Brar6b403ca2023-05-31 00:29:56 -050051#endif
Sughosh Ganu741ef862022-04-15 11:29:34 +053052
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090053/* Distro boot settings */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090054#ifdef CONFIG_CMD_USB
55#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
56#else
57#define BOOT_TARGET_DEVICE_USB(func)
58#endif
59
60#ifdef CONFIG_CMD_MMC
61#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
62#else
63#define BOOT_TARGET_DEVICE_MMC(func)
64#endif
65
66#ifdef CONFIG_CMD_NVME
67#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
68#else
69#define BOOT_TARGET_DEVICE_NVME(func)
70#endif
71
72#ifdef CONFIG_CMD_SCSI
73#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
74#else
75#define BOOT_TARGET_DEVICE_SCSI(func)
76#endif
77
78#define BOOT_TARGET_DEVICES(func) \
79 BOOT_TARGET_DEVICE_USB(func) \
80 BOOT_TARGET_DEVICE_MMC(func) \
81 BOOT_TARGET_DEVICE_SCSI(func) \
82 BOOT_TARGET_DEVICE_NVME(func) \
83
84#include <config_distro_bootcmd.h>
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090085
Tom Rini0613c362022-12-04 10:03:50 -050086#define CFG_EXTRA_ENV_SETTINGS \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090087 "fdt_addr_r=0x9fe00000\0" \
88 "kernel_addr_r=0x90000000\0" \
89 "ramdisk_addr_r=0xa0000000\0" \
90 "scriptaddr=0x88000000\0" \
91 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090092 BOOTENV
93
94#endif /* __CONFIG_H */