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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenkdb2f721f2003-03-06 00:58:30 +000011 */
12
13/*
wdenk7a8e9bed2003-05-31 18:35:21 +000014 * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
15 */
16
17/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020018 !! !!
wdenk7a8e9bed2003-05-31 18:35:21 +000019 !! This configuration requires JP3 to be in position 1-2 to work !!
Wolfgang Denk14d0a022010-10-07 21:51:12 +020020 !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !!
wdenk7a8e9bed2003-05-31 18:35:21 +000021 !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
22 !! 0xfff00000 !!
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023 !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020024 !! !!
wdenk8bde7f72003-06-27 21:31:46 +000025 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
wdenkdb2f721f2003-03-06 00:58:30 +000026 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
wdenkc837dcb2004-01-20 23:12:12 +000036#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkdb2f721f2003-03-06 00:58:30 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xfe000000
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050043#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenkdb2f721f2003-03-06 00:58:30 +000044
45/* allow serial and ethaddr to be overwritten */
46#define CONFIG_ENV_OVERWRITE
47
48/*
49 * select serial console configuration
50 *
51 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
52 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
53 * for SCC).
54 *
55 * if CONFIG_CONS_NONE is defined, then the serial console routines must
56 * defined elsewhere (for example, on the cogent platform, there are serial
57 * ports on the motherboard which are used for the serial console - see
58 * cogent/cma101/serial.[ch]).
59 */
60#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
61#define CONFIG_CONS_ON_SCC /* define if console on SCC */
62#undef CONFIG_CONS_NONE /* define if console on something else */
63#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
64
65/*
66 * select ethernet configuration
67 *
68 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
69 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
70 * for FCC)
71 *
72 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050073 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkdb2f721f2003-03-06 00:58:30 +000074 */
75#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
76#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
77#undef CONFIG_ETHER_NONE /* define if ether on something else */
78#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk5d232d02003-05-22 22:52:13 +000079#define CONFIG_MII /* MII PHY management */
80#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
81/*
82 * Port pins used for bit-banged MII communictions (if applicable).
83 */
84#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020085#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
86 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
87#define MDC_DECLARE MDIO_DECLARE
88
wdenk5d232d02003-05-22 22:52:13 +000089#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
90#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
91#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
92
93#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
94 else iop->pdat &= ~0x00400000
95
96#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
97 else iop->pdat &= ~0x00200000
98
99#define MIIDELAY udelay(1)
wdenkdb2f721f2003-03-06 00:58:30 +0000100
101#if (CONFIG_ETHER_INDEX == 2)
102
103/*
104 * - Rx-CLK is CLK13
105 * - Tx-CLK is CLK14
106 * - Select bus for bd/buffers (see 28-13)
107 * - Half duplex
108 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000109# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
110# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111# define CONFIG_SYS_CPMFCR_RAMTYPE 0
112# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkdb2f721f2003-03-06 00:58:30 +0000113
114#endif /* CONFIG_ETHER_INDEX */
115
116/* other options */
117#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
119#define CONFIG_SYS_I2C_SLAVE 0x7F
120#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkdb2f721f2003-03-06 00:58:30 +0000121
wdenk5d232d02003-05-22 22:52:13 +0000122/* PCI */
123#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000124#define CONFIG_PCI_INDIRECT_BRIDGE
wdenk5d232d02003-05-22 22:52:13 +0000125#define CONFIG_PCI_PNP
126#define CONFIG_PCI_BOOTDELAY 0
127#undef CONFIG_PCI_SCAN_SHOW
128
wdenkdb2f721f2003-03-06 00:58:30 +0000129/*-----------------------------------------------------------------------
130 * Definitions for Serial Presence Detect EEPROM address
131 * (to get SDRAM settings)
132 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200133#define SPD_EEPROM_ADDRESS 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000134
wdenk5d232d02003-05-22 22:52:13 +0000135#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000136#define CONFIG_BAUDRATE 115200
137
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500138/*
139 * Command line configuration.
140 */
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500141#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500142
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500143/* Commands we want, that are not part of default set */
144#define CONFIG_CMD_ASKENV /* ask for env variable */
145#define CONFIG_CMD_CACHE /* icache, dcache */
146#define CONFIG_CMD_DHCP /* DHCP Support */
147#define CONFIG_CMD_DIAG /* Diagnostics */
148#define CONFIG_CMD_IMMAP /* IMMR dump support */
149#define CONFIG_CMD_IRQ /* irqinfo */
150#define CONFIG_CMD_MII /* MII support */
151#define CONFIG_CMD_PCI /* pciinfo */
152#define CONFIG_CMD_PING /* ping support */
153#define CONFIG_CMD_PORTIO /* Port I/O */
154#define CONFIG_CMD_REGINFO /* Register dump */
155#define CONFIG_CMD_SAVES /* save S record dump */
156#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
157
158/* Commands from default set we don't need */
159#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
160#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
wdenkdb2f721f2003-03-06 00:58:30 +0000161
wdenk5d232d02003-05-22 22:52:13 +0000162/* Define a command string that is automatically executed when no character
163 * is read on the console interface withing "Boot Delay" after reset.
164 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200165#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
166#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk5d232d02003-05-22 22:52:13 +0000167
wdenk42dfe7a2004-03-14 22:25:36 +0000168#ifdef CONFIG_BOOT_ROOT_INITRD
wdenk5d232d02003-05-22 22:52:13 +0000169#define CONFIG_BOOTCOMMAND \
170 "version;" \
171 "echo;" \
172 "bootp;" \
173 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100174 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000175 "bootm"
176#endif /* CONFIG_BOOT_ROOT_INITRD */
177
wdenk42dfe7a2004-03-14 22:25:36 +0000178#ifdef CONFIG_BOOT_ROOT_NFS
wdenk5d232d02003-05-22 22:52:13 +0000179#define CONFIG_BOOTCOMMAND \
180 "version;" \
181 "echo;" \
182 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100183 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
184 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000185 "bootm"
186#endif /* CONFIG_BOOT_ROOT_NFS */
187
Jon Loeliger7be044e2007-07-09 21:24:19 -0500188/*
189 * BOOTP options
wdenk5d232d02003-05-22 22:52:13 +0000190 */
Jon Loeliger7be044e2007-07-09 21:24:19 -0500191#define CONFIG_BOOTP_SUBNETMASK
192#define CONFIG_BOOTP_GATEWAY
193#define CONFIG_BOOTP_HOSTNAME
194#define CONFIG_BOOTP_BOOTPATH
195#define CONFIG_BOOTP_BOOTFILESIZE
196#define CONFIG_BOOTP_DNS
wdenk5d232d02003-05-22 22:52:13 +0000197
wdenkdb2f721f2003-03-06 00:58:30 +0000198#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkdb2f721f2003-03-06 00:58:30 +0000199
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500200#if defined(CONFIG_CMD_KGDB)
wdenkdb2f721f2003-03-06 00:58:30 +0000201#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
202#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
203#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
204#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
205#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
206#endif
207
208#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
209
210/*
211 * Miscellaneous configurable options
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_LONGHELP /* undef to save memory */
214#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500215#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000217#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000219#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
221#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
222#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
225#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkdb2f721f2003-03-06 00:58:30 +0000226
wdenk5d232d02003-05-22 22:52:13 +0000227#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
wdenkdb2f721f2003-03-06 00:58:30 +0000228 /* for versions < 2.4.5-pre5 */
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkdb2f721f2003-03-06 00:58:30 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdb2f721f2003-03-06 00:58:30 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_FLASH_BASE 0xFE000000
wdenk5d232d02003-05-22 22:52:13 +0000237#define FLASH_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
239#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
240#define CONFIG_SYS_FLASH_SIZE 8
241#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
242#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
wdenkdb2f721f2003-03-06 00:58:30 +0000243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#undef CONFIG_SYS_FLASH_CHECKSUM
wdenkdb2f721f2003-03-06 00:58:30 +0000245
246/* this is stuff came out of the Motorola docs */
247/* Only change this if you also change the Hardware configuration Word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenkdb2f721f2003-03-06 00:58:30 +0000249
wdenkdb2f721f2003-03-06 00:58:30 +0000250/* Set IMMR to 0xF0000000 or above to boot Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_IMMR 0xF0000000
252#define CONFIG_SYS_BCSR 0xF8000000
253#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
wdenkdb2f721f2003-03-06 00:58:30 +0000254
255/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
256 */
257/*#define CONFIG_VERY_BIG_RAM 1*/
258
259/* What should be the base address of SDRAM DIMM and how big is
260 * it (in Mbytes)? This will normally auto-configure via the SPD.
261*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SDRAM_BASE 0x00000000
263#define CONFIG_SYS_SDRAM_SIZE 16
wdenkdb2f721f2003-03-06 00:58:30 +0000264
265#define SDRAM_SPD_ADDR 0x50
266
wdenkdb2f721f2003-03-06 00:58:30 +0000267/*-----------------------------------------------------------------------
268 * BR2,BR3 - Base Register
269 * Ref: Section 10.3.1 on page 10-14
270 * OR2,OR3 - Option Register
271 * Ref: Section 10.3.2 on page 10-16
272 *-----------------------------------------------------------------------
273 */
274
275/* Bank 2,3 - SDRAM DIMM
276 */
277
278/* The BR2 is configured as follows:
279 *
280 * - Base address of 0x00000000
281 * - 64 bit port size (60x bus only)
282 * - Data errors checking is disabled
283 * - Read and write access
284 * - SDRAM 60x bus
285 * - Access are handled by the memory controller according to MSEL
286 * - Not used for atomic operations
287 * - No data pipelining is done
288 * - Valid
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000291 BRx_PS_64 |\
292 BRx_MS_SDRAM_P |\
293 BRx_V)
294
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000296 BRx_PS_64 |\
297 BRx_MS_SDRAM_P |\
298 BRx_V)
299
300/* With a 64 MB DIMM, the OR2 is configured as follows:
301 *
302 * - 64 MB
303 * - 4 internal banks per device
304 * - Row start address bit is A8 with PSDMR[PBI] = 0
305 * - 12 row address lines
306 * - Back-to-back page mode
307 * - Internal bank interleaving within save device enabled
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#if (CONFIG_SYS_SDRAM_SIZE == 64)
310#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000311 ORxS_BPD_4 |\
312 ORxS_ROWST_PBI0_A8 |\
313 ORxS_NUMR_12)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#elif (CONFIG_SYS_SDRAM_SIZE == 16)
315#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
wdenkdb2f721f2003-03-06 00:58:30 +0000316#else
317#error "INVALID SDRAM CONFIGURATION"
318#endif
319
320/*-----------------------------------------------------------------------
321 * PSDMR - 60x Bus SDRAM Mode Register
322 * Ref: Section 10.3.3 on page 10-21
323 *-----------------------------------------------------------------------
324 */
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#if (CONFIG_SYS_SDRAM_SIZE == 64)
wdenkdb2f721f2003-03-06 00:58:30 +0000327/* With a 64 MB DIMM, the PSDMR is configured as follows:
328 *
329 * - Bank Based Interleaving,
330 * - Refresh Enable,
331 * - Address Multiplexing where A5 is output on A14 pin
332 * (A6 on A15, and so on),
333 * - use address pins A14-A16 as bank select,
334 * - A9 is output on SDA10 during an ACTIVATE command,
335 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
336 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
337 * is 3 clocks,
338 * - earliest timing for READ/WRITE command after ACTIVATE command is
339 * 2 clocks,
340 * - earliest timing for PRECHARGE after last data was read is 1 clock,
341 * - earliest timing for PRECHARGE after last data was written is 1 clock,
342 * - CAS Latency is 2.
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkdb2f721f2003-03-06 00:58:30 +0000345 PSDMR_SDAM_A14_IS_A5 |\
346 PSDMR_BSMA_A14_A16 |\
347 PSDMR_SDA10_PBI0_A9 |\
348 PSDMR_RFRC_7_CLK |\
349 PSDMR_PRETOACT_3W |\
350 PSDMR_ACTTORW_2W |\
351 PSDMR_LDOTOPRE_1C |\
352 PSDMR_WRC_1C |\
353 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#elif (CONFIG_SYS_SDRAM_SIZE == 16)
wdenkdb2f721f2003-03-06 00:58:30 +0000355/* With a 16 MB DIMM, the PSDMR is configured as follows:
356 *
357 * configuration parameters found in Motorola documentation
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PSDMR (0x016EB452)
wdenkdb2f721f2003-03-06 00:58:30 +0000360#else
361#error "INVALID SDRAM CONFIGURATION"
362#endif
363
wdenkdb2f721f2003-03-06 00:58:30 +0000364#define RS232EN_1 0x02000002
365#define RS232EN_2 0x01000001
366#define FETHIEN 0x08000008
367#define FETH_RST 0x04000004
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200370#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200371#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdb2f721f2003-03-06 00:58:30 +0000373
wdenk7a8e9bed2003-05-31 18:35:21 +0000374/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
wdenk5d232d02003-05-22 22:52:13 +0000375/* 0x0EB2B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
wdenk5d232d02003-05-22 22:52:13 +0000377 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
378 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
379 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
wdenkdb2f721f2003-03-06 00:58:30 +0000380 )
wdenk5d232d02003-05-22 22:52:13 +0000381
wdenk7a8e9bed2003-05-31 18:35:21 +0000382/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
wdenkdb2f721f2003-03-06 00:58:30 +0000384
wdenk8bde7f72003-06-27 21:31:46 +0000385/* This value should actually be situated in the first 256 bytes of the FLASH
wdenkdb2f721f2003-03-06 00:58:30 +0000386 which on the standard MPC8266ADS board is at address 0xFF800000
387 The linker script places it at 0xFFF00000 instead.
388
wdenk8bde7f72003-06-27 21:31:46 +0000389 It still works, however, as long as the ADS board jumper JP3 is set to
390 position 2-3 so the board is using the BCSR as Hardware Configuration Word
wdenkdb2f721f2003-03-06 00:58:30 +0000391
wdenk8bde7f72003-06-27 21:31:46 +0000392 If you want to use the one defined here instead, ust copy the first 256 bytes from
393 0xfff00000 to 0xff800000 (for 8MB flash)
wdenkdb2f721f2003-03-06 00:58:30 +0000394
395 - Rune
396
wdenk7a8e9bed2003-05-31 18:35:21 +0000397*/
wdenkdb2f721f2003-03-06 00:58:30 +0000398
399/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_HRCW_SLAVE1 0
401#define CONFIG_SYS_HRCW_SLAVE2 0
402#define CONFIG_SYS_HRCW_SLAVE3 0
403#define CONFIG_SYS_HRCW_SLAVE4 0
404#define CONFIG_SYS_HRCW_SLAVE5 0
405#define CONFIG_SYS_HRCW_SLAVE6 0
406#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkdb2f721f2003-03-06 00:58:30 +0000407
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200408#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500409
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
411# define CONFIG_SYS_RAMBOOT
wdenkdb2f721f2003-03-06 00:58:30 +0000412#endif
413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
415#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
416#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200419# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200421# define CONFIG_ENV_SECT_SIZE 0x40000
wdenkdb2f721f2003-03-06 00:58:30 +0000422#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200423# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200425# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#endif /* CONFIG_SYS_RAMBOOT */
wdenkdb2f721f2003-03-06 00:58:30 +0000427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500429#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000431#endif
432
wdenk7a8e9bed2003-05-31 18:35:21 +0000433/*-----------------------------------------------------------------------
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200434 * HIDx - Hardware Implementation-dependent Registers 2-11
wdenk7a8e9bed2003-05-31 18:35:21 +0000435 *-----------------------------------------------------------------------
436 * HID0 also contains cache control - initially enable both caches and
437 * invalidate contents, then the final state leaves only the instruction
438 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
439 * but Soft reset does not.
440 *
441 * HID1 has only read-only information - nothing to set.
442 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443/*#define CONFIG_SYS_HID0_INIT 0 */
444#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk7a8e9bed2003-05-31 18:35:21 +0000445 HID0_DCE |\
446 HID0_ICFI |\
447 HID0_DCI |\
448 HID0_IFEM |\
449 HID0_ABE)
450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenkdb2f721f2003-03-06 00:58:30 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_HID2 0
wdenkdb2f721f2003-03-06 00:58:30 +0000454
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_SYPCR 0xFFFFFFC3
456#define CONFIG_SYS_BCR 0x004C0000
457#define CONFIG_SYS_SIUMCR 0x4E64C000
458#define CONFIG_SYS_SCCR 0x00000000
wdenkdb2f721f2003-03-06 00:58:30 +0000459
wdenk5d232d02003-05-22 22:52:13 +0000460/* local bus memory map
461 *
462 * 0x00000000-0x03FFFFFF 64MB SDRAM
463 * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
464 * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
465 * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200466 * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
wdenk5d232d02003-05-22 22:52:13 +0000467 * 0xF8000000-0xF8007FFF 32KB BCSR
468 * 0xF8100000-0xF8107FFF 32KB ATM UNI
469 * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
470 * 0xF8300000-0xF8307FFF 32KB EEPROM
471 * 0xFE000000-0xFFFFFFFF 32MB flash
472 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
474#define CONFIG_SYS_OR0_PRELIM 0xFE000836
475#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
476#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
477#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
478#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
479#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
480#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
481#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
482#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
wdenk5d232d02003-05-22 22:52:13 +0000483
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_RMR 0x0001
485#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
486#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
487#define CONFIG_SYS_RCCR 0
488#define CONFIG_SYS_MPTPR 0x00001900
489#define CONFIG_SYS_PSRT 0x00000021
wdenkdb2f721f2003-03-06 00:58:30 +0000490
wdenk65bd0e22003-09-18 10:45:21 +0000491/* This address must not exist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
wdenkdb2f721f2003-03-06 00:58:30 +0000493
wdenk5d232d02003-05-22 22:52:13 +0000494/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
496#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
497#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +0000498 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000499
wdenk8bde7f72003-06-27 21:31:46 +0000500/*
wdenk5d232d02003-05-22 22:52:13 +0000501 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +0000502 * All three PCI master windows, which allow the CPU to access PCI
503 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +0000504 * these windows.
505 */
506
507/* PCIBR0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
509#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000510/* PCIBR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
512#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000513
wdenk8bde7f72003-06-27 21:31:46 +0000514/*
wdenk5d232d02003-05-22 22:52:13 +0000515 * Master window that allows the CPU to access PCI Memory (prefetch).
516 * This window will be setup with the first set of Outbound ATU registers
517 * in the bridge.
518 */
519
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
521#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
522#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
523#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
524#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000525
wdenk8bde7f72003-06-27 21:31:46 +0000526/*
wdenk5d232d02003-05-22 22:52:13 +0000527 * Master window that allows the CPU to access PCI Memory (non-prefetch).
528 * This window will be setup with the second set of Outbound ATU registers
529 * in the bridge.
530 */
531
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
533#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
534#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
535#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
536#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000537
wdenk8bde7f72003-06-27 21:31:46 +0000538/*
wdenk5d232d02003-05-22 22:52:13 +0000539 * Master window that allows the CPU to access PCI IO space.
540 * This window will be setup with the third set of Outbound ATU registers
541 * in the bridge.
542 */
543
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
545#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
546#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
547#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
548#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000549
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200550/*
551 * JFFS2 partitions
552 *
553 */
554/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100555#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200556#define CONFIG_JFFS2_DEV "nor0"
557#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
558#define CONFIG_JFFS2_PART_OFFSET 0x00000000
559
560/* mtdparts command line support */
561/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100562#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200563#define MTDIDS_DEFAULT ""
564#define MTDPARTS_DEFAULT ""
565*/
wdenk5d232d02003-05-22 22:52:13 +0000566
wdenkdb2f721f2003-03-06 00:58:30 +0000567#endif /* __CONFIG_H */