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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 *
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
wdenkc6097192002-11-03 00:24:07 +00007 */
8
9#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070010#include <cpu_func.h>
wdenkc6097192002-11-03 00:24:07 +000011#include <malloc.h>
12#include <net.h>
Ben Warrene3090532008-08-31 10:08:43 -070013#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000014#include <asm/io.h>
15#include <pci.h>
16
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020017#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
wdenkc6097192002-11-03 00:24:07 +000018
Wolfgang Denk138b6082011-11-05 05:12:58 +000019#define PCNET_DEBUG1(fmt,args...) \
20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
21#define PCNET_DEBUG2(fmt,args...) \
22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
wdenkc6097192002-11-03 00:24:07 +000023
wdenkc6097192002-11-03 00:24:07 +000024/*
25 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
26 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
27 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
28 */
29#define PCNET_LOG_TX_BUFFERS 0
30#define PCNET_LOG_RX_BUFFERS 2
31
32#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
33#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
34
35#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
36#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
37
38#define PKT_BUF_SZ 1544
39
40/* The PCNET Rx and Tx ring descriptors. */
41struct pcnet_rx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020042 u32 base;
43 s16 buf_length;
44 s16 status;
45 u32 msg_length;
46 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000047};
48
49struct pcnet_tx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020050 u32 base;
51 s16 length;
52 s16 status;
53 u32 misc;
54 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000055};
56
57/* The PCNET 32-Bit initialization block, described in databook. */
58struct pcnet_init_block {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020059 u16 mode;
60 u16 tlen_rlen;
61 u8 phys_addr[6];
62 u16 reserved;
63 u32 filter[2];
64 /* Receive and transmit ring base, along with extra bits. */
65 u32 rx_ring;
66 u32 tx_ring;
67 u32 reserved2;
wdenkc6097192002-11-03 00:24:07 +000068};
69
Paul Burtonf1ae3822014-04-07 16:41:46 +010070struct pcnet_uncached_priv {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020071 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
72 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
73 struct pcnet_init_block init_block;
Paul Burtonf1ae3822014-04-07 16:41:46 +010074};
75
76typedef struct pcnet_priv {
77 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020078 /* Receive Buffer space */
Paul Burtona354ddc2014-04-07 16:41:47 +010079 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020080 int cur_rx;
81 int cur_tx;
wdenkc6097192002-11-03 00:24:07 +000082} pcnet_priv_t;
83
84static pcnet_priv_t *lp;
85
86/* Offsets from base I/O address for WIO mode */
87#define PCNET_RDP 0x10
88#define PCNET_RAP 0x12
89#define PCNET_RESET 0x14
90#define PCNET_BDP 0x16
91
Paul Burton6011dab2013-11-08 11:18:43 +000092static u16 pcnet_read_csr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +000093{
Paul Burton6011dab2013-11-08 11:18:43 +000094 outw(index, dev->iobase + PCNET_RAP);
95 return inw(dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +000096}
97
Paul Burton6011dab2013-11-08 11:18:43 +000098static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +000099{
Paul Burton6011dab2013-11-08 11:18:43 +0000100 outw(index, dev->iobase + PCNET_RAP);
101 outw(val, dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000102}
103
Paul Burton6011dab2013-11-08 11:18:43 +0000104static u16 pcnet_read_bcr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +0000105{
Paul Burton6011dab2013-11-08 11:18:43 +0000106 outw(index, dev->iobase + PCNET_RAP);
107 return inw(dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000108}
109
Paul Burton6011dab2013-11-08 11:18:43 +0000110static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000111{
Paul Burton6011dab2013-11-08 11:18:43 +0000112 outw(index, dev->iobase + PCNET_RAP);
113 outw(val, dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000114}
115
Paul Burton6011dab2013-11-08 11:18:43 +0000116static void pcnet_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000117{
Paul Burton6011dab2013-11-08 11:18:43 +0000118 inw(dev->iobase + PCNET_RESET);
wdenkc6097192002-11-03 00:24:07 +0000119}
120
Paul Burton6011dab2013-11-08 11:18:43 +0000121static int pcnet_check(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000122{
Paul Burton6011dab2013-11-08 11:18:43 +0000123 outw(88, dev->iobase + PCNET_RAP);
124 return inw(dev->iobase + PCNET_RAP) == 88;
wdenkc6097192002-11-03 00:24:07 +0000125}
126
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200127static int pcnet_init (struct eth_device *dev, bd_t * bis);
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000128static int pcnet_send(struct eth_device *dev, void *packet, int length);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200129static int pcnet_recv (struct eth_device *dev);
130static void pcnet_halt (struct eth_device *dev);
131static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
wdenkc6097192002-11-03 00:24:07 +0000132
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100133static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
Paul Burton4677d662016-05-26 14:49:34 +0100134 void *addr)
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100135{
Paul Burton442d2e02016-05-26 14:49:35 +0100136 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100137 void *virt_addr = addr;
138
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100139 return pci_virt_to_mem(devbusfn, virt_addr);
140}
wdenkc6097192002-11-03 00:24:07 +0000141
142static struct pci_device_id supported[] = {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200143 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
144 {}
wdenkc6097192002-11-03 00:24:07 +0000145};
146
147
Paul Burton6011dab2013-11-08 11:18:43 +0000148int pcnet_initialize(bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000149{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200150 pci_dev_t devbusfn;
151 struct eth_device *dev;
152 u16 command, status;
153 int dev_nr = 0;
Paul Burtonbed1ca32016-05-26 17:32:29 +0100154 u32 bar;
wdenkc6097192002-11-03 00:24:07 +0000155
Paul Burton6011dab2013-11-08 11:18:43 +0000156 PCNET_DEBUG1("\npcnet_initialize...\n");
wdenkc6097192002-11-03 00:24:07 +0000157
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200158 for (dev_nr = 0;; dev_nr++) {
wdenkc6097192002-11-03 00:24:07 +0000159
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200160 /*
161 * Find the PCnet PCI device(s).
162 */
Paul Burton6011dab2013-11-08 11:18:43 +0000163 devbusfn = pci_find_devices(supported, dev_nr);
164 if (devbusfn < 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200165 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200166
167 /*
168 * Allocate and pre-fill the device structure.
169 */
Paul Burton6011dab2013-11-08 11:18:43 +0000170 dev = (struct eth_device *)malloc(sizeof(*dev));
Nobuhiro Iwamatsu5ed0eec2010-10-19 14:03:45 +0900171 if (!dev) {
172 printf("pcnet: Can not allocate memory\n");
173 break;
174 }
175 memset(dev, 0, sizeof(*dev));
Paul Burton442d2e02016-05-26 14:49:35 +0100176 dev->priv = (void *)(unsigned long)devbusfn;
Paul Burton6011dab2013-11-08 11:18:43 +0000177 sprintf(dev->name, "pcnet#%d", dev_nr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200178
179 /*
180 * Setup the PCI device.
181 */
Paul Burtonbed1ca32016-05-26 17:32:29 +0100182 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
183 dev->iobase = pci_io_to_phys(devbusfn, bar);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200184 dev->iobase &= ~0xf;
185
Paul Burton442d2e02016-05-26 14:49:35 +0100186 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
187 dev->name, devbusfn, (unsigned long)dev->iobase);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200188
189 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
Paul Burton6011dab2013-11-08 11:18:43 +0000190 pci_write_config_word(devbusfn, PCI_COMMAND, command);
191 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200192 if ((status & command) != command) {
Paul Burton6011dab2013-11-08 11:18:43 +0000193 printf("%s: Couldn't enable IO access or Bus Mastering\n",
194 dev->name);
195 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200196 continue;
197 }
198
Paul Burton6011dab2013-11-08 11:18:43 +0000199 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200200
201 /*
202 * Probe the PCnet chip.
203 */
Paul Burton6011dab2013-11-08 11:18:43 +0000204 if (pcnet_probe(dev, bis, dev_nr) < 0) {
205 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200206 continue;
207 }
208
209 /*
210 * Setup device structure and register the driver.
211 */
212 dev->init = pcnet_init;
213 dev->halt = pcnet_halt;
214 dev->send = pcnet_send;
215 dev->recv = pcnet_recv;
216
Paul Burton6011dab2013-11-08 11:18:43 +0000217 eth_register(dev);
wdenkc6097192002-11-03 00:24:07 +0000218 }
219
Paul Burton6011dab2013-11-08 11:18:43 +0000220 udelay(10 * 1000);
wdenkc6097192002-11-03 00:24:07 +0000221
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200222 return dev_nr;
wdenkc6097192002-11-03 00:24:07 +0000223}
224
Paul Burton6011dab2013-11-08 11:18:43 +0000225static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
wdenkc6097192002-11-03 00:24:07 +0000226{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200227 int chip_version;
228 char *chipname;
229
wdenkc6097192002-11-03 00:24:07 +0000230#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200231 int i;
wdenkc6097192002-11-03 00:24:07 +0000232#endif
233
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200234 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000235 pcnet_reset(dev);
wdenkc6097192002-11-03 00:24:07 +0000236
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200237 /* Check if register access is working */
Paul Burton6011dab2013-11-08 11:18:43 +0000238 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
239 printf("%s: CSR register access check failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200240 return -1;
241 }
wdenkc6097192002-11-03 00:24:07 +0000242
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200243 /* Identify the chip */
244 chip_version =
Paul Burton6011dab2013-11-08 11:18:43 +0000245 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200246 if ((chip_version & 0xfff) != 0x003)
247 return -1;
248 chip_version = (chip_version >> 12) & 0xffff;
249 switch (chip_version) {
250 case 0x2621:
251 chipname = "PCnet/PCI II 79C970A"; /* PCI */
252 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200253 case 0x2625:
254 chipname = "PCnet/FAST III 79C973"; /* PCI */
255 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200256 case 0x2627:
257 chipname = "PCnet/FAST III 79C975"; /* PCI */
258 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200259 default:
Paul Burton6011dab2013-11-08 11:18:43 +0000260 printf("%s: PCnet version %#x not supported\n",
261 dev->name, chip_version);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200262 return -1;
263 }
wdenkc6097192002-11-03 00:24:07 +0000264
Paul Burton6011dab2013-11-08 11:18:43 +0000265 PCNET_DEBUG1("AMD %s\n", chipname);
wdenkc6097192002-11-03 00:24:07 +0000266
267#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200268 /*
269 * In most chips, after a chip reset, the ethernet address is read from
270 * the station address PROM at the base address and programmed into the
271 * "Physical Address Registers" CSR12-14.
272 */
273 for (i = 0; i < 3; i++) {
274 unsigned int val;
275
Paul Burton6011dab2013-11-08 11:18:43 +0000276 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200277 /* There may be endianness issues here. */
278 dev->enetaddr[2 * i] = val & 0x0ff;
279 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
280 }
wdenkc6097192002-11-03 00:24:07 +0000281#endif /* PCNET_HAS_PROM */
282
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200283 return 0;
wdenkc6097192002-11-03 00:24:07 +0000284}
285
Paul Burton6011dab2013-11-08 11:18:43 +0000286static int pcnet_init(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000287{
Paul Burtonf1ae3822014-04-07 16:41:46 +0100288 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200289 int i, val;
Paul Burton442d2e02016-05-26 14:49:35 +0100290 unsigned long addr;
wdenkc6097192002-11-03 00:24:07 +0000291
Paul Burton6011dab2013-11-08 11:18:43 +0000292 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
wdenkc6097192002-11-03 00:24:07 +0000293
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200294 /* Switch pcnet to 32bit mode */
Paul Burton6011dab2013-11-08 11:18:43 +0000295 pcnet_write_bcr(dev, 20, 2);
wdenkc6097192002-11-03 00:24:07 +0000296
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200297 /* Set/reset autoselect bit */
Paul Burton6011dab2013-11-08 11:18:43 +0000298 val = pcnet_read_bcr(dev, 2) & ~2;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200299 val |= 2;
Paul Burton6011dab2013-11-08 11:18:43 +0000300 pcnet_write_bcr(dev, 2, val);
wdenkc6097192002-11-03 00:24:07 +0000301
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200302 /* Enable auto negotiate, setup, disable fd */
Paul Burton6011dab2013-11-08 11:18:43 +0000303 val = pcnet_read_bcr(dev, 32) & ~0x98;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200304 val |= 0x20;
Paul Burton6011dab2013-11-08 11:18:43 +0000305 pcnet_write_bcr(dev, 32, val);
wdenkc6097192002-11-03 00:24:07 +0000306
wdenkc6097192002-11-03 00:24:07 +0000307 /*
Paul Burton62715a22013-11-08 11:18:46 +0000308 * Enable NOUFLO on supported controllers, with the transmit
309 * start point set to the full packet. This will cause entire
310 * packets to be buffered by the ethernet controller before
311 * transmission, eliminating underflows which are common on
312 * slower devices. Controllers which do not support NOUFLO will
313 * simply be left with a larger transmit FIFO threshold.
314 */
315 val = pcnet_read_bcr(dev, 18);
316 val |= 1 << 11;
317 pcnet_write_bcr(dev, 18, val);
318 val = pcnet_read_csr(dev, 80);
319 val |= 0x3 << 10;
320 pcnet_write_csr(dev, 80, val);
321
322 /*
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200323 * We only maintain one structure because the drivers will never
324 * be used concurrently. In 32bit mode the RX and TX ring entries
325 * must be aligned on 16-byte boundaries.
wdenkc6097192002-11-03 00:24:07 +0000326 */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200327 if (lp == NULL) {
Paul Burton442d2e02016-05-26 14:49:35 +0100328 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200329 addr = (addr + 0xf) & ~0xf;
Paul Burton6011dab2013-11-08 11:18:43 +0000330 lp = (pcnet_priv_t *)addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100331
Paul Burton442d2e02016-05-26 14:49:35 +0100332 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
333 sizeof(*lp->uc));
Paul Burtonf1ae3822014-04-07 16:41:46 +0100334 flush_dcache_range(addr, addr + sizeof(*lp->uc));
Marek Vasut3c0bcb92020-04-18 02:32:19 +0200335 addr = (unsigned long)map_physmem(addr,
336 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
337 MAP_NOCACHE);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100338 lp->uc = (struct pcnet_uncached_priv *)addr;
Paul Burtona354ddc2014-04-07 16:41:47 +0100339
Paul Burton442d2e02016-05-26 14:49:35 +0100340 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
341 sizeof(*lp->rx_buf));
Paul Burtona354ddc2014-04-07 16:41:47 +0100342 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
343 lp->rx_buf = (void *)addr;
wdenkc6097192002-11-03 00:24:07 +0000344 }
wdenkc6097192002-11-03 00:24:07 +0000345
Paul Burtonf1ae3822014-04-07 16:41:46 +0100346 uc = lp->uc;
347
348 uc->init_block.mode = cpu_to_le16(0x0000);
349 uc->init_block.filter[0] = 0x00000000;
350 uc->init_block.filter[1] = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000351
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200352 /*
353 * Initialize the Rx ring.
354 */
355 lp->cur_rx = 0;
356 for (i = 0; i < RX_RING_SIZE; i++) {
Paul Burton4677d662016-05-26 14:49:34 +0100357 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100358 uc->rx_ring[i].base = cpu_to_le32(addr);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100359 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
360 uc->rx_ring[i].status = cpu_to_le16(0x8000);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200361 PCNET_DEBUG1
362 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
Paul Burtonf1ae3822014-04-07 16:41:46 +0100363 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
364 uc->rx_ring[i].status);
wdenkc6097192002-11-03 00:24:07 +0000365 }
wdenkc6097192002-11-03 00:24:07 +0000366
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200367 /*
368 * Initialize the Tx ring. The Tx buffer address is filled in as
369 * needed, but we do need to clear the upper ownership bit.
370 */
371 lp->cur_tx = 0;
372 for (i = 0; i < TX_RING_SIZE; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100373 uc->tx_ring[i].base = 0;
374 uc->tx_ring[i].status = 0;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200375 }
376
377 /*
378 * Setup Init Block.
379 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100380 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200381
382 for (i = 0; i < 6; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100383 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
384 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200385 }
386
Paul Burtonf1ae3822014-04-07 16:41:46 +0100387 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
Paul Burton6011dab2013-11-08 11:18:43 +0000388 RX_RING_LEN_BITS);
Paul Burton4677d662016-05-26 14:49:34 +0100389 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100390 uc->init_block.rx_ring = cpu_to_le32(addr);
Paul Burton4677d662016-05-26 14:49:34 +0100391 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100392 uc->init_block.tx_ring = cpu_to_le32(addr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200393
Paul Burton6011dab2013-11-08 11:18:43 +0000394 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
Paul Burtonf1ae3822014-04-07 16:41:46 +0100395 uc->init_block.tlen_rlen,
396 uc->init_block.rx_ring, uc->init_block.tx_ring);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200397
398 /*
399 * Tell the controller where the Init Block is located.
400 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100401 barrier();
Paul Burton4677d662016-05-26 14:49:34 +0100402 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
Paul Burton6011dab2013-11-08 11:18:43 +0000403 pcnet_write_csr(dev, 1, addr & 0xffff);
404 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200405
Paul Burton6011dab2013-11-08 11:18:43 +0000406 pcnet_write_csr(dev, 4, 0x0915);
407 pcnet_write_csr(dev, 0, 0x0001); /* start */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200408
409 /* Wait for Init Done bit */
410 for (i = 10000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000411 if (pcnet_read_csr(dev, 0) & 0x0100)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200412 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000413 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200414 }
415 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000416 printf("%s: TIMEOUT: controller init failed\n", dev->name);
417 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200418 return -1;
419 }
420
421 /*
422 * Finally start network controller operation.
423 */
Paul Burton6011dab2013-11-08 11:18:43 +0000424 pcnet_write_csr(dev, 0, 0x0002);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200425
426 return 0;
wdenkc6097192002-11-03 00:24:07 +0000427}
428
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000429static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
wdenkc6097192002-11-03 00:24:07 +0000430{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200431 int i, status;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100432 u32 addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100433 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
wdenkc6097192002-11-03 00:24:07 +0000434
Paul Burton6011dab2013-11-08 11:18:43 +0000435 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
436 packet);
wdenkc6097192002-11-03 00:24:07 +0000437
Paul Burtonf3ac8662013-11-08 11:18:45 +0000438 flush_dcache_range((unsigned long)packet,
439 (unsigned long)packet + pkt_len);
440
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200441 /* Wait for completion by testing the OWN bit */
442 for (i = 1000; i > 0; i--) {
Paul Burton6fb49e42014-04-07 16:41:48 +0100443 status = readw(&entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200444 if ((status & 0x8000) == 0)
445 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000446 udelay(100);
447 PCNET_DEBUG2(".");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200448 }
449 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000450 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
451 dev->name, lp->cur_tx, status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200452 pkt_len = 0;
453 goto failure;
454 }
wdenkc6097192002-11-03 00:24:07 +0000455
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200456 /*
457 * Setup Tx ring. Caution: the write order is important here,
458 * set the status with the "ownership" bits last.
459 */
Paul Burton4677d662016-05-26 14:49:34 +0100460 addr = pcnet_virt_to_mem(dev, packet);
Paul Burton6fb49e42014-04-07 16:41:48 +0100461 writew(-pkt_len, &entry->length);
462 writel(0, &entry->misc);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100463 writel(addr, &entry->base);
Paul Burton6fb49e42014-04-07 16:41:48 +0100464 writew(0x8300, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200465
466 /* Trigger an immediate send poll. */
Paul Burton6011dab2013-11-08 11:18:43 +0000467 pcnet_write_csr(dev, 0, 0x0008);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200468
469 failure:
470 if (++lp->cur_tx >= TX_RING_SIZE)
471 lp->cur_tx = 0;
472
Paul Burton6011dab2013-11-08 11:18:43 +0000473 PCNET_DEBUG2("done\n");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200474 return pkt_len;
wdenkc6097192002-11-03 00:24:07 +0000475}
476
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200477static int pcnet_recv (struct eth_device *dev)
478{
479 struct pcnet_rx_head *entry;
Paul Burtona354ddc2014-04-07 16:41:47 +0100480 unsigned char *buf;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200481 int pkt_len = 0;
Paul Burton6fb49e42014-04-07 16:41:48 +0100482 u16 status, err_status;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200483
484 while (1) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100485 entry = &lp->uc->rx_ring[lp->cur_rx];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200486 /*
487 * If we own the next entry, it's a new packet. Send it up.
488 */
Paul Burton6fb49e42014-04-07 16:41:48 +0100489 status = readw(&entry->status);
Paul Burton6011dab2013-11-08 11:18:43 +0000490 if ((status & 0x8000) != 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200491 break;
Paul Burton6fb49e42014-04-07 16:41:48 +0100492 err_status = status >> 8;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200493
Paul Burton6fb49e42014-04-07 16:41:48 +0100494 if (err_status != 0x03) { /* There was an error. */
Paul Burton6011dab2013-11-08 11:18:43 +0000495 printf("%s: Rx%d", dev->name, lp->cur_rx);
Paul Burton6fb49e42014-04-07 16:41:48 +0100496 PCNET_DEBUG1(" (status=0x%x)", err_status);
497 if (err_status & 0x20)
Paul Burton6011dab2013-11-08 11:18:43 +0000498 printf(" Frame");
Paul Burton6fb49e42014-04-07 16:41:48 +0100499 if (err_status & 0x10)
Paul Burton6011dab2013-11-08 11:18:43 +0000500 printf(" Overflow");
Paul Burton6fb49e42014-04-07 16:41:48 +0100501 if (err_status & 0x08)
Paul Burton6011dab2013-11-08 11:18:43 +0000502 printf(" CRC");
Paul Burton6fb49e42014-04-07 16:41:48 +0100503 if (err_status & 0x04)
Paul Burton6011dab2013-11-08 11:18:43 +0000504 printf(" Fifo");
505 printf(" Error\n");
Paul Burton6fb49e42014-04-07 16:41:48 +0100506 status &= 0x03ff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200507
508 } else {
Paul Burton6fb49e42014-04-07 16:41:48 +0100509 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200510 if (pkt_len < 60) {
Paul Burton6011dab2013-11-08 11:18:43 +0000511 printf("%s: Rx%d: invalid packet length %d\n",
512 dev->name, lp->cur_rx, pkt_len);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200513 } else {
Paul Burtona354ddc2014-04-07 16:41:47 +0100514 buf = (*lp->rx_buf)[lp->cur_rx];
515 invalidate_dcache_range((unsigned long)buf,
516 (unsigned long)buf + pkt_len);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500517 net_process_received_packet(buf, pkt_len);
Paul Burton6011dab2013-11-08 11:18:43 +0000518 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
Paul Burtona354ddc2014-04-07 16:41:47 +0100519 lp->cur_rx, pkt_len, buf);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200520 }
521 }
Paul Burton6fb49e42014-04-07 16:41:48 +0100522
523 status |= 0x8000;
524 writew(status, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200525
526 if (++lp->cur_rx >= RX_RING_SIZE)
527 lp->cur_rx = 0;
528 }
529 return pkt_len;
530}
531
Paul Burton6011dab2013-11-08 11:18:43 +0000532static void pcnet_halt(struct eth_device *dev)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200533{
534 int i;
535
Paul Burton6011dab2013-11-08 11:18:43 +0000536 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200537
538 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000539 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200540
541 /* Wait for Stop bit */
542 for (i = 1000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000543 if (pcnet_read_csr(dev, 0) & 0x4)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200544 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000545 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200546 }
Paul Burton6011dab2013-11-08 11:18:43 +0000547 if (i <= 0)
548 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200549}