blob: 97a75709f9d5254344d72d8392a0e5affbe1250c [file] [log] [blame]
Poonam Aggrwal49249e12011-02-09 19:17:53 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwal49249e12011-02-09 19:17:53 +00005 */
6
7/*
8 * P010 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +053014#include <asm/config_mpc85xx.h>
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050015#define CONFIG_NAND_FSL_IFC
Poonam Aggrwal49249e12011-02-09 19:17:53 +000016
17#ifdef CONFIG_SDCARD
Ying Zhangc9e1f582014-01-24 15:50:09 +080018#define CONFIG_SPL_MMC_MINIMAL
19#define CONFIG_SPL_FLUSH_IMAGE
20#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangc9e1f582014-01-24 15:50:09 +080021#define CONFIG_SYS_TEXT_BASE 0x11001000
22#define CONFIG_SPL_TEXT_BASE 0xD0001000
23#define CONFIG_SPL_PAD_TO 0x18000
24#define CONFIG_SPL_MAX_SIZE (96 * 1024)
25#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
26#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
28#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
29#define CONFIG_SYS_MPC85XX_NO_RESETVEC
30#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
31#define CONFIG_SPL_MMC_BOOT
32#ifdef CONFIG_SPL_BUILD
33#define CONFIG_SPL_COMMON_INIT_DDR
34#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000035#endif
36
37#ifdef CONFIG_SPIFLASH
Ying Zhangc9e1f582014-01-24 15:50:09 +080038#ifdef CONFIG_SECURE_BOOT
Poonam Aggrwal49249e12011-02-09 19:17:53 +000039#define CONFIG_RAMBOOT_SPIFLASH
40#define CONFIG_SYS_TEXT_BASE 0x11000000
Ruchika Gupta84e0fb42014-09-29 11:14:35 +053041#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ying Zhangc9e1f582014-01-24 15:50:09 +080042#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080043#define CONFIG_SPL_SPI_FLASH_MINIMAL
44#define CONFIG_SPL_FLUSH_IMAGE
45#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangc9e1f582014-01-24 15:50:09 +080046#define CONFIG_SYS_TEXT_BASE 0x11001000
47#define CONFIG_SPL_TEXT_BASE 0xD0001000
48#define CONFIG_SPL_PAD_TO 0x18000
49#define CONFIG_SPL_MAX_SIZE (96 * 1024)
50#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
51#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
52#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
53#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
54#define CONFIG_SYS_MPC85XX_NO_RESETVEC
55#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
56#define CONFIG_SPL_SPI_BOOT
57#ifdef CONFIG_SPL_BUILD
58#define CONFIG_SPL_COMMON_INIT_DDR
59#endif
60#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000061#endif
62
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053063#ifdef CONFIG_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +080064#ifdef CONFIG_SECURE_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053065#define CONFIG_SPL_INIT_MINIMAL
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053066#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053067#define CONFIG_SPL_FLUSH_IMAGE
68#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69
70#define CONFIG_SYS_TEXT_BASE 0x00201000
71#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
72#define CONFIG_SPL_MAX_SIZE 8192
73#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
74#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053075#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053076#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
77#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
78#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
79#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Ying Zhangc9e1f582014-01-24 15:50:09 +080080#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080081#ifdef CONFIG_TPL_BUILD
82#define CONFIG_SPL_NAND_BOOT
83#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhangc9e1f582014-01-24 15:50:09 +080084#define CONFIG_SPL_NAND_INIT
Ying Zhangc9e1f582014-01-24 15:50:09 +080085#define CONFIG_SPL_COMMON_INIT_DDR
86#define CONFIG_SPL_MAX_SIZE (128 << 10)
87#define CONFIG_SPL_TEXT_BASE 0xD0001000
88#define CONFIG_SYS_MPC85XX_NO_RESETVEC
89#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
90#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
91#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
92#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
93#elif defined(CONFIG_SPL_BUILD)
94#define CONFIG_SPL_INIT_MINIMAL
Ying Zhangc9e1f582014-01-24 15:50:09 +080095#define CONFIG_SPL_NAND_MINIMAL
96#define CONFIG_SPL_FLUSH_IMAGE
97#define CONFIG_SPL_TEXT_BASE 0xff800000
98#define CONFIG_SPL_MAX_SIZE 8192
99#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
100#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
101#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
102#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500103#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800104#define CONFIG_SPL_PAD_TO 0x20000
105#define CONFIG_TPL_PAD_TO 0x20000
106#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
107#define CONFIG_SYS_TEXT_BASE 0x11001000
108#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109#endif
110#endif
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500111
112#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
113#define CONFIG_RAMBOOT_NAND
114#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530115#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500116#endif
117
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000118#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530119#define CONFIG_SYS_TEXT_BASE 0xeff40000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000120#endif
121
122#ifndef CONFIG_RESET_VECTOR_ADDRESS
123#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124#endif
125
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530126#ifdef CONFIG_SPL_BUILD
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
128#else
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000130#endif
131
132/* High Level Configuration Options */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000133#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
134
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000135#if defined(CONFIG_PCI)
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400136#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
137#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000138#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +0000139#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000140#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
141#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
142
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000143#define CONFIG_CMD_PCI
144
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000145/*
146 * PCI Windows
147 * Memory space is mapped 1-1, but I/O space must start from 0.
148 */
149/* controller 1, Slot 1, tgtid 1, Base address a000 */
150#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
151#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
152#ifdef CONFIG_PHYS_64BIT
153#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
154#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
155#else
156#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
157#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
158#endif
159#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
160#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
161#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
162#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
163#ifdef CONFIG_PHYS_64BIT
164#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
165#else
166#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
167#endif
168
169/* controller 2, Slot 2, tgtid 2, Base address 9000 */
York Sun76016862016-11-16 13:30:06 -0800170#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000171#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
York Sun76016862016-11-16 13:30:06 -0800172#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800173#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
174#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000175#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
176#ifdef CONFIG_PHYS_64BIT
177#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
178#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
179#else
180#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
181#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
182#endif
183#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
184#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
185#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
186#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
187#ifdef CONFIG_PHYS_64BIT
188#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
189#else
190#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
191#endif
192
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000193#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000194#endif
195
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000196#define CONFIG_TSEC_ENET
197#define CONFIG_ENV_OVERWRITE
198
199#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
200#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
201
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000202#define CONFIG_MISC_INIT_R
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000203#define CONFIG_HWCONFIG
204/*
205 * These can be toggled for performance analysis, otherwise use default.
206 */
207#define CONFIG_L2_CACHE /* toggle L2 cache */
208#define CONFIG_BTB /* toggle branch predition */
209
210#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
211
212#define CONFIG_ENABLE_36BIT_PHYS
213
214#ifdef CONFIG_PHYS_64BIT
215#define CONFIG_ADDR_MAP 1
216#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
217#endif
218
Zhao Qiangc3cc02a2013-11-26 13:59:15 +0800219#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000220#define CONFIG_SYS_MEMTEST_END 0x1fffffff
221#define CONFIG_PANIC_HANG /* do not reset board on panic */
222
223/* DDR Setup */
York Sun1ba62f12012-02-29 12:36:51 +0000224#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000225#define CONFIG_DDR_SPD
226#define CONFIG_SYS_SPD_BUS_NUM 1
227#define SPD_EEPROM_ADDRESS 0x52
228
229#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
230
231#ifndef __ASSEMBLY__
232extern unsigned long get_sdram_size(void);
233#endif
234#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
235#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
236#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
237
238#define CONFIG_DIMM_SLOTS_PER_CTLR 1
239#define CONFIG_CHIP_SELECTS_PER_CTRL 1
240
241/* DDR3 Controller Settings */
242#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
243#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
244#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
245#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
246#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
247#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
248#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000249#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
250#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
251#define CONFIG_SYS_DDR_RCW_1 0x00000000
252#define CONFIG_SYS_DDR_RCW_2 0x00000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800253#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
254#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000255#define CONFIG_SYS_DDR_TIMING_4 0x00000001
256#define CONFIG_SYS_DDR_TIMING_5 0x03402400
257
Shengzhou Liue512c502013-09-13 14:46:03 +0800258#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
259#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
260#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000261#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
262#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800263#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
264#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000265#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
Shengzhou Liue512c502013-09-13 14:46:03 +0800266#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000267
268/* settings for DDR3 at 667MT/s */
269#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
270#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
271#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
272#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
273#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
274#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
275#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
276#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
277#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
278
279#define CONFIG_SYS_CCSRBAR 0xffe00000
280#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
281
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500282/* Don't relocate CCSRBAR while in NAND_SPL */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530283#ifdef CONFIG_SPL_BUILD
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500284#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
285#endif
286
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000287/*
288 * Memory map
289 *
290 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
291 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
292 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
293 *
294 * Localbus non-cacheable
295 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
296 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
297 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
298 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
299 */
300
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000301/*
302 * IFC Definitions
303 */
304/* NOR Flash on IFC */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530305
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000306#define CONFIG_SYS_FLASH_BASE 0xee000000
307#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
308
309#ifdef CONFIG_PHYS_64BIT
310#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
311#else
312#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
313#endif
314
315#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
316 CSPR_PORT_SIZE_16 | \
317 CSPR_MSEL_NOR | \
318 CSPR_V)
319#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
320#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
321/* NOR Flash Timing Params */
322#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
323 FTIM0_NOR_TEADC(0x5) | \
324 FTIM0_NOR_TEAHC(0x5)
325#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
326 FTIM1_NOR_TRAD_NOR(0x0f)
327#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
328 FTIM2_NOR_TCH(0x4) | \
329 FTIM2_NOR_TWP(0x1c)
330#define CONFIG_SYS_NOR_FTIM3 0x0
331
332#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
333#define CONFIG_SYS_FLASH_QUIET_TEST
334#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
335#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
336
337#undef CONFIG_SYS_FLASH_CHECKSUM
338#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
339#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
340
341/* CFI for NOR Flash */
342#define CONFIG_FLASH_CFI_DRIVER
343#define CONFIG_SYS_FLASH_CFI
344#define CONFIG_SYS_FLASH_EMPTY_INFO
345#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
346
347/* NAND Flash on IFC */
348#define CONFIG_SYS_NAND_BASE 0xff800000
349#ifdef CONFIG_PHYS_64BIT
350#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
351#else
352#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
353#endif
354
Zhao Qiangac688072013-09-26 09:10:32 +0800355#define CONFIG_MTD_DEVICE
356#define CONFIG_MTD_PARTITION
357#define CONFIG_CMD_MTDPARTS
358#define MTDIDS_DEFAULT "nand0=ff800000.flash"
359#define MTDPARTS_DEFAULT \
360 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
361
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000362#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
363 | CSPR_PORT_SIZE_8 \
364 | CSPR_MSEL_NAND \
365 | CSPR_V)
366#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Shengzhou Liue512c502013-09-13 14:46:03 +0800367
York Sun76016862016-11-16 13:30:06 -0800368#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000369#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
370 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
371 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
372 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
373 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
374 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
375 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
Shengzhou Liue512c502013-09-13 14:46:03 +0800376#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
377
York Sun76016862016-11-16 13:30:06 -0800378#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800379#define CONFIG_SYS_NAND_ONFI_DETECTION
380#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
381 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
382 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
383 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
384 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
385 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
386 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
387#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
388#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000389
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500390#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
391#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500392#define CONFIG_CMD_NAND
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500393
York Sun76016862016-11-16 13:30:06 -0800394#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000395/* NAND Flash Timing Params */
396#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
397 FTIM0_NAND_TWP(0x0C) | \
398 FTIM0_NAND_TWCHT(0x04) | \
399 FTIM0_NAND_TWH(0x05)
400#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
401 FTIM1_NAND_TWBE(0x1d) | \
402 FTIM1_NAND_TRR(0x07) | \
403 FTIM1_NAND_TRP(0x0c)
404#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
405 FTIM2_NAND_TREH(0x05) | \
406 FTIM2_NAND_TWHRE(0x0f)
407#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
408
York Sun76016862016-11-16 13:30:06 -0800409#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800410/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
411/* ONFI NAND Flash mode0 Timing Params */
412#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
413 FTIM0_NAND_TWP(0x18) | \
414 FTIM0_NAND_TWCHT(0x07) | \
415 FTIM0_NAND_TWH(0x0a))
416#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
417 FTIM1_NAND_TWBE(0x39) | \
418 FTIM1_NAND_TRR(0x0e) | \
419 FTIM1_NAND_TRP(0x18))
420#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
421 FTIM2_NAND_TREH(0x0a) | \
422 FTIM2_NAND_TWHRE(0x1e))
423#define CONFIG_SYS_NAND_FTIM3 0x0
424#endif
425
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000426#define CONFIG_SYS_NAND_DDR_LAW 11
427
428/* Set up IFC registers for boot location NOR/NAND */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530429#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500430#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
431#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
432#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
433#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
434#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
435#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
436#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
437#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
438#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
439#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
440#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
441#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
442#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
443#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
444#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000445#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
446#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
447#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
448#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
449#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
450#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
451#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
452#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
453#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
454#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
455#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
456#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
457#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
458#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500459#endif
460
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000461/* CPLD on IFC */
462#define CONFIG_SYS_CPLD_BASE 0xffb00000
463
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
466#else
467#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
468#endif
469
470#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
471 | CSPR_PORT_SIZE_8 \
472 | CSPR_MSEL_GPCM \
473 | CSPR_V)
474#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
475#define CONFIG_SYS_CSOR3 0x0
476/* CPLD Timing parameters for IFC CS3 */
477#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
478 FTIM0_GPCM_TEADC(0x0e) | \
479 FTIM0_GPCM_TEAHC(0x0e))
480#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
481 FTIM1_GPCM_TRAD(0x1f))
482#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800483 FTIM2_GPCM_TCH(0x8) | \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000484 FTIM2_GPCM_TWP(0x1f))
485#define CONFIG_SYS_CS3_FTIM3 0x0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000486
Aneesh Bansal76c9aaf2014-03-07 19:12:09 +0530487#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
488 defined(CONFIG_RAMBOOT_NAND)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000489#define CONFIG_SYS_RAMBOOT
490#define CONFIG_SYS_EXTRA_ENV_RELOC
491#else
492#undef CONFIG_SYS_RAMBOOT
493#endif
494
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530495#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Aneesh Bansal50c76362014-01-20 14:57:03 +0530496#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530497#define CONFIG_A003399_NOR_WORKAROUND
498#endif
499#endif
500
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000501#define CONFIG_BOARD_EARLY_INIT_R
502
503#define CONFIG_SYS_INIT_RAM_LOCK
504#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sunb39d1212016-04-06 13:22:10 -0700505#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000506
York Sunb39d1212016-04-06 13:22:10 -0700507#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000508 - GENERATED_GBL_DATA_SIZE)
509#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
510
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530511#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000512#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
513
Ying Zhangc9e1f582014-01-24 15:50:09 +0800514/*
515 * Config the L2 Cache as L2 SRAM
516 */
517#if defined(CONFIG_SPL_BUILD)
518#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
519#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
520#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
521#define CONFIG_SYS_L2_SIZE (256 << 10)
522#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
523#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
524#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
525#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
526#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
527#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
528#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
529#elif defined(CONFIG_NAND)
530#ifdef CONFIG_TPL_BUILD
531#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
532#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
533#define CONFIG_SYS_L2_SIZE (256 << 10)
534#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
535#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
536#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
537#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
538#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
539#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
540#else
541#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
542#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
543#define CONFIG_SYS_L2_SIZE (256 << 10)
544#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
545#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
546#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
547#endif
548#endif
549#endif
550
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000551/* Serial Port */
552#define CONFIG_CONS_INDEX 1
553#undef CONFIG_SERIAL_SOFTWARE_FIFO
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000554#define CONFIG_SYS_NS16550_SERIAL
555#define CONFIG_SYS_NS16550_REG_SIZE 1
556#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800557#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500558#define CONFIG_NS16550_MIN_FUNCTIONS
559#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000560
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000561#define CONFIG_SYS_BAUDRATE_TABLE \
562 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
563
564#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
565#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
566
Heiko Schocher00f792e2012-10-24 13:48:22 +0200567/* I2C */
568#define CONFIG_SYS_I2C
569#define CONFIG_SYS_I2C_FSL
570#define CONFIG_SYS_FSL_I2C_SPEED 400000
571#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
572#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
573#define CONFIG_SYS_FSL_I2C2_SPEED 400000
574#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
575#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Shengzhou Liuad89da02013-09-13 14:46:02 +0800576#define I2C_PCA9557_ADDR1 0x18
Shengzhou Liue512c502013-09-13 14:46:03 +0800577#define I2C_PCA9557_ADDR2 0x19
Shengzhou Liuad89da02013-09-13 14:46:02 +0800578#define I2C_PCA9557_BUS_NUM 0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000579
580/* I2C EEPROM */
York Sun76016862016-11-16 13:30:06 -0800581#if defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800582#define CONFIG_ID_EEPROM
583#ifdef CONFIG_ID_EEPROM
584#define CONFIG_SYS_I2C_EEPROM_NXID
585#endif
586#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
587#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
588#define CONFIG_SYS_EEPROM_BUS_NUM 0
589#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
590#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000591/* enable read and write access to EEPROM */
592#define CONFIG_CMD_EEPROM
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000593#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
594#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
595#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
596
597/* RTC */
598#define CONFIG_RTC_PT7C4338
599#define CONFIG_SYS_I2C_RTC_ADDR 0x68
600
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000601/*
602 * SPI interface will not be available in case of NAND boot SPI CS0 will be
603 * used for SLIC
604 */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530605#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000606/* eSPI - Enhanced SPI */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000607#define CONFIG_SF_DEFAULT_SPEED 10000000
608#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500609#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000610
611#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000612#define CONFIG_MII /* MII PHY management */
613#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
614#define CONFIG_TSEC1 1
615#define CONFIG_TSEC1_NAME "eTSEC1"
616#define CONFIG_TSEC2 1
617#define CONFIG_TSEC2_NAME "eTSEC2"
618#define CONFIG_TSEC3 1
619#define CONFIG_TSEC3_NAME "eTSEC3"
620
621#define TSEC1_PHY_ADDR 1
622#define TSEC2_PHY_ADDR 0
623#define TSEC3_PHY_ADDR 2
624
625#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
626#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
627#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
628
629#define TSEC1_PHYIDX 0
630#define TSEC2_PHYIDX 0
631#define TSEC3_PHYIDX 0
632
633#define CONFIG_ETHPRIME "eTSEC1"
634
635#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
636
637/* TBI PHY configuration for SGMII mode */
638#define CONFIG_TSEC_TBICR_SETTINGS ( \
639 TBICR_PHY_RESET \
640 | TBICR_ANEG_ENABLE \
641 | TBICR_FULL_DUPLEX \
642 | TBICR_SPEED1_SET \
643 )
644
645#endif /* CONFIG_TSEC_ENET */
646
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000647/* SATA */
648#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000649#define CONFIG_FSL_SATA_V2
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000650#define CONFIG_LIBATA
651
652#ifdef CONFIG_FSL_SATA
653#define CONFIG_SYS_SATA_MAX_DEVICE 2
654#define CONFIG_SATA1
655#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
656#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
657#define CONFIG_SATA2
658#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
659#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
660
661#define CONFIG_CMD_SATA
662#define CONFIG_LBA48
663#endif /* #ifdef CONFIG_FSL_SATA */
664
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000665#ifdef CONFIG_MMC
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000666#define CONFIG_FSL_ESDHC
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000667#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
668#endif
669
670#define CONFIG_HAS_FSL_DR_USB
671
672#if defined(CONFIG_HAS_FSL_DR_USB)
673#define CONFIG_USB_EHCI
674
675#ifdef CONFIG_USB_EHCI
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000676#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
677#define CONFIG_USB_EHCI_FSL
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000678#endif
679#endif
680
681/*
682 * Environment
683 */
Ying Zhangc9e1f582014-01-24 15:50:09 +0800684#if defined(CONFIG_SDCARD)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000685#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000686#define CONFIG_FSL_FIXED_MMC_LOCATION
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000687#define CONFIG_SYS_MMC_ENV_DEV 0
688#define CONFIG_ENV_SIZE 0x2000
Ying Zhangc9e1f582014-01-24 15:50:09 +0800689#elif defined(CONFIG_SPIFLASH)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000690#define CONFIG_ENV_IS_IN_SPI_FLASH
691#define CONFIG_ENV_SPI_BUS 0
692#define CONFIG_ENV_SPI_CS 0
693#define CONFIG_ENV_SPI_MAX_HZ 10000000
694#define CONFIG_ENV_SPI_MODE 0
695#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
696#define CONFIG_ENV_SECT_SIZE 0x10000
697#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530698#elif defined(CONFIG_NAND)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500699#define CONFIG_ENV_IS_IN_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +0800700#ifdef CONFIG_TPL_BUILD
701#define CONFIG_ENV_SIZE 0x2000
702#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
703#else
York Sun76016862016-11-16 13:30:06 -0800704#if defined(CONFIG_TARGET_P1010RDB_PA)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500705#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Shengzhou Liue512c502013-09-13 14:46:03 +0800706#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
York Sun76016862016-11-16 13:30:06 -0800707#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800708#define CONFIG_ENV_SIZE (16 * 1024)
709#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
710#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800711#endif
712#define CONFIG_ENV_OFFSET (1024 * 1024)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530713#elif defined(CONFIG_SYS_RAMBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000714#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
715#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
716#define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000717#else
718#define CONFIG_ENV_IS_IN_FLASH
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000719#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000720#define CONFIG_ENV_SIZE 0x2000
721#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
722#endif
723
724#define CONFIG_LOADS_ECHO /* echo on for serial download */
725#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
726
727/*
728 * Command line configuration.
729 */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000730#define CONFIG_CMD_DATE
731#define CONFIG_CMD_ERRATA
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000732#define CONFIG_CMD_IRQ
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000733#define CONFIG_CMD_REGINFO
734
735#undef CONFIG_WATCHDOG /* watchdog disabled */
736
737#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
738 || defined(CONFIG_FSL_SATA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000739#endif
740
Ruchika Gupta737537e2014-10-15 11:35:31 +0530741/* Hash command with SHA acceleration supported in hardware */
742#ifdef CONFIG_FSL_CAAM
743#define CONFIG_CMD_HASH
744#define CONFIG_SHA_HW_ACCEL
745#endif
746
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000747/*
748 * Miscellaneous configurable options
749 */
750#define CONFIG_SYS_LONGHELP /* undef to save memory */
751#define CONFIG_CMDLINE_EDITING /* Command-line editing */
752#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
753#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000754
755#if defined(CONFIG_CMD_KGDB)
756#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
757#else
758#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
759#endif
760#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
761 /* Print Buffer Size */
762#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
763#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000764
765/*
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000766 * For booting Linux, the board info and command line data
767 * have to be in the first 64 MB of memory, since this is
768 * the maximum mapped by the Linux kernel during initialization.
769 */
770#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
771#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
772
773#if defined(CONFIG_CMD_KGDB)
774#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000775#endif
776
777/*
778 * Environment Configuration
779 */
780
781#if defined(CONFIG_TSEC_ENET)
782#define CONFIG_HAS_ETH0
783#define CONFIG_HAS_ETH1
784#define CONFIG_HAS_ETH2
785#endif
786
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000787#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000788#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000789#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
790
791/* default location for tftp and bootm */
792#define CONFIG_LOADADDR 1000000
793
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000794#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
795
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000796#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200797 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000798 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200799 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000800 "loadaddr=1000000\0" \
801 "consoledev=ttyS0\0" \
802 "ramdiskaddr=2000000\0" \
803 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500804 "fdtaddr=1e00000\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000805 "fdtfile=p1010rdb.dtb\0" \
806 "bdev=sda1\0" \
807 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
808 "othbootargs=ramdisk_size=600000\0" \
809 "usbfatboot=setenv bootargs root=/dev/ram rw " \
810 "console=$consoledev,$baudrate $othbootargs; " \
811 "usb start;" \
812 "fatload usb 0:2 $loadaddr $bootfile;" \
813 "fatload usb 0:2 $fdtaddr $fdtfile;" \
814 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
815 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
816 "usbext2boot=setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs; " \
818 "usb start;" \
819 "ext2load usb 0:4 $loadaddr $bootfile;" \
820 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
821 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
Shengzhou Liue512c502013-09-13 14:46:03 +0800822 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
823 CONFIG_BOOTMODE
824
York Sun76016862016-11-16 13:30:06 -0800825#if defined(CONFIG_TARGET_P1010RDB_PA)
Shengzhou Liue512c502013-09-13 14:46:03 +0800826#define CONFIG_BOOTMODE \
827 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
828 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
829 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
830 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
831 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
832 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
833
York Sun76016862016-11-16 13:30:06 -0800834#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800835#define CONFIG_BOOTMODE \
836 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
837 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
838 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
839 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
840 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
841 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
842 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
843 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
844 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
845 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
846#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000847
848#define CONFIG_RAMBOOTCOMMAND \
849 "setenv bootargs root=/dev/ram rw " \
850 "console=$consoledev,$baudrate $othbootargs; " \
851 "tftp $ramdiskaddr $ramdiskfile;" \
852 "tftp $loadaddr $bootfile;" \
853 "tftp $fdtaddr $fdtfile;" \
854 "bootm $loadaddr $ramdiskaddr $fdtaddr"
855
856#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
857
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500858#include <asm/fsl_secure_boot.h>
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500859
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000860#endif /* __CONFIG_H */