blob: 002dab437fac06cb9f50d7539c13a825004f3077 [file] [log] [blame]
Simon Glasse9f66f42018-12-10 10:37:48 -07001// SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +00002/*
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 *
5 * Copyright 2011 Maxim Integrated Products
6 *
Simon Glasse9f66f42018-12-10 10:37:48 -07007 * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +00008 */
Simon Glass150c5af2017-05-30 21:47:09 -06009
10#include <common.h>
Simon Glassd6cadd52018-12-10 10:37:39 -070011#include <audio_codec.h>
12#include <dm.h>
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000013#include <div64.h>
14#include <fdtdec.h>
15#include <i2c.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000017#include <sound.h>
Simon Glassa1efd492018-12-03 04:37:34 -070018#include <asm/gpio.h>
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000019#include "i2s.h"
20#include "max98095.h"
21
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000022/* Index 0 is reserved. */
23int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
24 88200, 96000};
25
26/*
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000027 * codec mclk clock divider coefficients based on sampling rate
28 *
29 * @param rate sampling rate
30 * @param value address of indexvalue to be stored
31 *
32 * @return 0 for success or negative error code.
33 */
34static int rate_value(int rate, u8 *value)
35{
36 int i;
37
38 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
39 if (rate_table[i] >= rate) {
40 *value = i;
41 return 0;
42 }
43 }
44 *value = 1;
45
Simon Glassbc581842018-12-10 10:37:49 -070046 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000047}
48
49/*
50 * Sets hw params for max98095
51 *
Simon Glassa832a3e2018-12-03 04:37:25 -070052 * @param priv max98095 information pointer
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000053 * @param rate Sampling rate
54 * @param bits_per_sample Bits per sample
55 *
Simon Glassbc581842018-12-10 10:37:49 -070056 * @return 0 for success or negative error code.
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000057 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -070058static int max98095_hw_params(struct maxim_priv *priv,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053059 enum en_max_audio_interface aif_id,
60 unsigned int rate, unsigned int bits_per_sample)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000061{
62 u8 regval;
63 int error;
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053064 unsigned short M98095_DAI_CLKMODE;
65 unsigned short M98095_DAI_FORMAT;
66 unsigned short M98095_DAI_FILTERS;
67
68 if (aif_id == AIF1) {
69 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
70 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
71 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
72 } else {
73 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
74 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
75 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
76 }
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000077
78 switch (bits_per_sample) {
79 case 16:
Simon Glass0ab6f0b2018-12-10 10:37:42 -070080 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000081 break;
82 case 24:
Simon Glass0ab6f0b2018-12-10 10:37:42 -070083 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
84 M98095_DAI_WS);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000085 break;
86 default:
87 debug("%s: Illegal bits per sample %d.\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053088 __func__, bits_per_sample);
Simon Glassbc581842018-12-10 10:37:49 -070089 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000090 }
91
92 if (rate_value(rate, &regval)) {
93 debug("%s: Failed to set sample rate to %d.\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053094 __func__, rate);
Simon Glassbc581842018-12-10 10:37:49 -070095 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000096 }
Simon Glassa832a3e2018-12-03 04:37:25 -070097 priv->rate = rate;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000098
Simon Glass0ab6f0b2018-12-10 10:37:42 -070099 error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
Simon Glassa832a3e2018-12-03 04:37:25 -0700100 regval);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000101
102 /* Update sample rate mode */
103 if (rate < 50000)
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700104 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
Simon Glassa832a3e2018-12-03 04:37:25 -0700105 M98095_DAI_DHF, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000106 else
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700107 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
Simon Glassa832a3e2018-12-03 04:37:25 -0700108 M98095_DAI_DHF, M98095_DAI_DHF);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000109
110 if (error < 0) {
111 debug("%s: Error setting hardware params.\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700112 return -EIO;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000113 }
114
115 return 0;
116}
117
118/*
119 * Configures Audio interface system clock for the given frequency
120 *
Simon Glassa832a3e2018-12-03 04:37:25 -0700121 * @param priv max98095 information
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000122 * @param freq Sampling frequency in Hz
123 *
Simon Glassbc581842018-12-10 10:37:49 -0700124 * @return 0 for success or negative error code.
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000125 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700126static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000127{
128 int error = 0;
129
130 /* Requested clock frequency is already setup */
Simon Glassa832a3e2018-12-03 04:37:25 -0700131 if (freq == priv->sysclk)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000132 return 0;
133
134 /* Setup clocks for slave mode, and using the PLL
135 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
136 * 0x02 (when master clk is 20MHz to 40MHz)..
137 * 0x03 (when master clk is 40MHz to 60MHz)..
138 */
139 if ((freq >= 10000000) && (freq < 20000000)) {
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700140 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000141 } else if ((freq >= 20000000) && (freq < 40000000)) {
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700142 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000143 } else if ((freq >= 40000000) && (freq < 60000000)) {
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700144 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000145 } else {
146 debug("%s: Invalid master clock frequency\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700147 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000148 }
149
150 debug("%s: Clock at %uHz\n", __func__, freq);
151
152 if (error < 0)
Simon Glassbc581842018-12-10 10:37:49 -0700153 return -EIO;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000154
Simon Glassa832a3e2018-12-03 04:37:25 -0700155 priv->sysclk = freq;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000156 return 0;
157}
158
159/*
160 * Sets Max98095 I2S format
161 *
Simon Glassa832a3e2018-12-03 04:37:25 -0700162 * @param priv max98095 information
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000163 * @param fmt i2S format - supports a subset of the options defined
164 * in i2s.h.
165 *
Simon Glassbc581842018-12-10 10:37:49 -0700166 * @return 0 for success or negative error code.
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000167 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700168static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530169 enum en_max_audio_interface aif_id)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000170{
171 u8 regval = 0;
172 int error = 0;
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530173 unsigned short M98095_DAI_CLKCFG_HI;
174 unsigned short M98095_DAI_CLKCFG_LO;
175 unsigned short M98095_DAI_FORMAT;
176 unsigned short M98095_DAI_CLOCK;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000177
Simon Glassa832a3e2018-12-03 04:37:25 -0700178 if (fmt == priv->fmt)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000179 return 0;
180
Simon Glassa832a3e2018-12-03 04:37:25 -0700181 priv->fmt = fmt;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000182
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530183 if (aif_id == AIF1) {
184 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
185 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
186 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
187 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
188 } else {
189 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
190 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
191 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
192 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
193 }
194
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000195 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
196 case SND_SOC_DAIFMT_CBS_CFS:
197 /* Slave mode PLL */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700198 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
199 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000200 break;
201 case SND_SOC_DAIFMT_CBM_CFM:
202 /* Set to master mode */
203 regval |= M98095_DAI_MAS;
204 break;
205 case SND_SOC_DAIFMT_CBS_CFM:
206 case SND_SOC_DAIFMT_CBM_CFS:
207 default:
208 debug("%s: Clock mode unsupported\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700209 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000210 }
211
212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
213 case SND_SOC_DAIFMT_I2S:
214 regval |= M98095_DAI_DLY;
215 break;
216 case SND_SOC_DAIFMT_LEFT_J:
217 break;
218 default:
219 debug("%s: Unrecognized format.\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700220 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000221 }
222
223 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
224 case SND_SOC_DAIFMT_NB_NF:
225 break;
226 case SND_SOC_DAIFMT_NB_IF:
227 regval |= M98095_DAI_WCI;
228 break;
229 case SND_SOC_DAIFMT_IB_NF:
230 regval |= M98095_DAI_BCI;
231 break;
232 case SND_SOC_DAIFMT_IB_IF:
233 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
234 break;
235 default:
236 debug("%s: Unrecognized inversion settings.\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700237 return -EINVAL;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000238 }
239
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700240 error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
Simon Glassa832a3e2018-12-03 04:37:25 -0700241 M98095_DAI_MAS | M98095_DAI_DLY |
242 M98095_DAI_BCI | M98095_DAI_WCI, regval);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000243
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700244 error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000245
246 if (error < 0) {
247 debug("%s: Error setting i2s format.\n", __func__);
Simon Glassbc581842018-12-10 10:37:49 -0700248 return -EIO;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000249 }
250
251 return 0;
252}
253
254/*
255 * resets the audio codec
256 *
Simon Glassa832a3e2018-12-03 04:37:25 -0700257 * @param priv Private data for driver
Simon Glassbc581842018-12-10 10:37:49 -0700258 * @return 0 for success or negative error code.
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000259 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700260static int max98095_reset(struct maxim_priv *priv)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000261{
262 int i, ret;
263
264 /*
265 * Gracefully reset the DSP core and the codec hardware in a proper
266 * sequence.
267 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700268 ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000269 if (ret != 0) {
270 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
271 return ret;
272 }
273
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700274 ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000275 if (ret != 0) {
276 debug("%s: Failed to reset codec: %d\n", __func__, ret);
277 return ret;
278 }
279
280 /*
281 * Reset to hardware default for registers, as there is not a soft
282 * reset hardware control register.
283 */
284 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700285 ret = maxim_i2c_write(priv, i, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000286 if (ret < 0) {
287 debug("%s: Failed to reset: %d\n", __func__, ret);
288 return ret;
289 }
290 }
291
292 return 0;
293}
294
295/*
296 * Intialise max98095 codec device
297 *
Simon Glassa832a3e2018-12-03 04:37:25 -0700298 * @param priv max98095 information
Simon Glassbc581842018-12-10 10:37:49 -0700299 * @return 0 for success or negative error code.
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000300 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700301static int max98095_device_init(struct maxim_priv *priv)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000302{
303 unsigned char id;
Simon Glassbc581842018-12-10 10:37:49 -0700304 int ret;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000305
306 /* reset the codec, the DSP core, and disable all interrupts */
Simon Glassbc581842018-12-10 10:37:49 -0700307 ret = max98095_reset(priv);
308 if (ret != 0) {
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000309 debug("Reset\n");
Simon Glassbc581842018-12-10 10:37:49 -0700310 return ret;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000311 }
312
313 /* initialize private data */
Simon Glassa832a3e2018-12-03 04:37:25 -0700314 priv->sysclk = -1U;
315 priv->rate = -1U;
316 priv->fmt = -1U;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000317
Simon Glassbc581842018-12-10 10:37:49 -0700318 ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
319 if (ret < 0) {
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000320 debug("%s: Failure reading hardware revision: %d\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530321 __func__, id);
Simon Glassbc581842018-12-10 10:37:49 -0700322 return ret;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000323 }
324 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
325
Simon Glass82a27d22018-12-03 04:37:28 -0700326 return 0;
327}
328
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700329static int max98095_setup_interface(struct maxim_priv *priv,
Simon Glass82a27d22018-12-03 04:37:28 -0700330 enum en_max_audio_interface aif_id)
331{
332 int error;
333
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700334 error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000335
336 /*
337 * initialize registers to hardware default configuring audio
338 * interface2 to DAC
339 */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530340 if (aif_id == AIF1)
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700341 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530342 M98095_DAI1L_TO_DACL |
343 M98095_DAI1R_TO_DACR);
344 else
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700345 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530346 M98095_DAI2M_TO_DACL |
347 M98095_DAI2M_TO_DACR);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000348
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700349 error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530350 M98095_SPK_SPREADSPECTRUM);
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700351 error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530352 if (aif_id == AIF1)
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700353 error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530354 M98095_S1NORMAL | M98095_SDATA);
355 else
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700356 error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530357 M98095_S2NORMAL | M98095_SDATA);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000358
359 /* take the codec out of the shut down */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700360 error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
Simon Glassa832a3e2018-12-03 04:37:25 -0700361 M98095_SHDNRUN);
362 /*
363 * route DACL and DACR output to HO and Speakers
364 * Ordering: DACL, DACR, DACL, DACR
365 */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700366 error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
367 error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
368 error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
369 error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000370
371 /* power Enable */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700372 error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000373
374 /* set Volume */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700375 error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
376 error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
377 error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
378 error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000379
380 /* Enable DAIs */
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700381 error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530382 if (aif_id == AIF1)
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700383 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530384 else
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700385 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000386
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000387 if (error < 0)
Simon Glassbc581842018-12-10 10:37:49 -0700388 return -EIO;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000389
390 return 0;
391}
392
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700393static int max98095_do_init(struct maxim_priv *priv,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530394 enum en_max_audio_interface aif_id,
395 int sampling_rate, int mclk_freq,
396 int bits_per_sample)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000397{
398 int ret = 0;
399
Simon Glass04660d62018-12-03 04:37:32 -0700400 ret = max98095_setup_interface(priv, aif_id);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000401 if (ret < 0) {
Simon Glassd6cadd52018-12-10 10:37:39 -0700402 debug("%s: max98095 setup interface failed\n", __func__);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000403 return ret;
404 }
405
Simon Glass04660d62018-12-03 04:37:32 -0700406 ret = max98095_set_sysclk(priv, mclk_freq);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000407 if (ret < 0) {
408 debug("%s: max98095 codec set sys clock failed\n", __func__);
409 return ret;
410 }
411
Simon Glass04660d62018-12-03 04:37:32 -0700412 ret = max98095_hw_params(priv, aif_id, sampling_rate,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530413 bits_per_sample);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000414
415 if (ret == 0) {
Simon Glass04660d62018-12-03 04:37:32 -0700416 ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530417 SND_SOC_DAIFMT_NB_NF |
418 SND_SOC_DAIFMT_CBS_CFS,
419 aif_id);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000420 }
421
422 return ret;
423}
424
Simon Glassd6cadd52018-12-10 10:37:39 -0700425static int max98095_set_params(struct udevice *dev, int interface, int rate,
426 int mclk_freq, int bits_per_sample,
427 uint channels)
428{
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700429 struct maxim_priv *priv = dev_get_priv(dev);
Simon Glassd6cadd52018-12-10 10:37:39 -0700430
431 return max98095_do_init(priv, interface, rate, mclk_freq,
432 bits_per_sample);
433}
434
435static int max98095_probe(struct udevice *dev)
436{
Simon Glass0ab6f0b2018-12-10 10:37:42 -0700437 struct maxim_priv *priv = dev_get_priv(dev);
Simon Glassd6cadd52018-12-10 10:37:39 -0700438 int ret;
439
440 priv->dev = dev;
441 ret = max98095_device_init(priv);
442 if (ret < 0) {
443 debug("%s: max98095 codec chip init failed\n", __func__);
444 return ret;
445 }
446
447 return 0;
448}
449
450static const struct audio_codec_ops max98095_ops = {
451 .set_params = max98095_set_params,
452};
453
454static const struct udevice_id max98095_ids[] = {
455 { .compatible = "maxim,max98095" },
456 { }
457};
458
459U_BOOT_DRIVER(max98095) = {
460 .name = "max98095",
461 .id = UCLASS_AUDIO_CODEC,
462 .of_match = max98095_ids,
463 .probe = max98095_probe,
464 .ops = &max98095_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700465 .priv_auto = sizeof(struct maxim_priv),
Simon Glassd6cadd52018-12-10 10:37:39 -0700466};