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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roese46f37382008-04-08 10:31:00 +02002 * (C) Copyright 2006-2008
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <nand.h>
Stefan Roesec568f772008-01-05 16:49:37 +010023#include <asm/io.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020024
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
Stefan Roese887e2ec2006-09-07 11:51:23 +020026
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
Stefan Roese46f37382008-04-08 10:31:00 +020028/*
29 * NAND command for small page NAND devices (512)
30 */
Stefan Roese42be56f2007-06-01 15:23:04 +020031static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
Stefan Roese887e2ec2006-09-07 11:51:23 +020032{
Wolfgang Denk511d0c72006-10-09 00:42:01 +020033 struct nand_chip *this = mtd->priv;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
Stefan Roese42be56f2007-06-01 15:23:04 +020035
Stefan Roesee29816f2011-05-16 13:04:00 +020036 while (!this->dev_ready(mtd))
37 ;
Stefan Roese887e2ec2006-09-07 11:51:23 +020038
39 /* Begin command latch cycle */
Scott Wood4f32d772008-08-05 11:15:59 -050040 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Stefan Roese887e2ec2006-09-07 11:51:23 +020041 /* Set ALE and clear CLE to start address cycle */
Stefan Roese887e2ec2006-09-07 11:51:23 +020042 /* Column address */
Scott Wood4f32d772008-08-05 11:15:59 -050043 this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
Scott Wood1dac3a52009-06-24 17:23:49 -050044 this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
45 this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
46 NAND_CTRL_ALE); /* A[24:17] */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
Stefan Roese887e2ec2006-09-07 11:51:23 +020048 /* One more address cycle for devices > 32MiB */
Scott Wood1dac3a52009-06-24 17:23:49 -050049 this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
50 NAND_CTRL_ALE); /* A[28:25] */
Stefan Roese887e2ec2006-09-07 11:51:23 +020051#endif
52 /* Latch in address */
Stefan Roesec568f772008-01-05 16:49:37 +010053 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Stefan Roese887e2ec2006-09-07 11:51:23 +020054
55 /*
56 * Wait a while for the data to be ready
57 */
Stefan Roesea9c847c2011-05-04 11:44:14 +020058 while (!this->dev_ready(mtd))
59 ;
Stefan Roese887e2ec2006-09-07 11:51:23 +020060
Stefan Roese42be56f2007-06-01 15:23:04 +020061 return 0;
62}
Stefan Roese46f37382008-04-08 10:31:00 +020063#else
64/*
65 * NAND command for large page NAND devices (2k)
66 */
67static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
68{
69 struct nand_chip *this = mtd->priv;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
Alex Waterman837097832011-05-04 09:10:15 -040071 void (*hwctrl)(struct mtd_info *mtd, int cmd,
72 unsigned int ctrl) = this->cmd_ctrl;
Stefan Roese46f37382008-04-08 10:31:00 +020073
Stefan Roesea9c847c2011-05-04 11:44:14 +020074 while (!this->dev_ready(mtd))
75 ;
Stefan Roese46f37382008-04-08 10:31:00 +020076
77 /* Emulate NAND_CMD_READOOB */
78 if (cmd == NAND_CMD_READOOB) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 offs += CONFIG_SYS_NAND_PAGE_SIZE;
Stefan Roese46f37382008-04-08 10:31:00 +020080 cmd = NAND_CMD_READ0;
81 }
82
Alex Waterman65a9db72011-04-06 16:01:52 -040083 /* Shift the offset from byte addressing to word addressing. */
84 if (this->options & NAND_BUSWIDTH_16)
85 offs >>= 1;
86
Stefan Roese46f37382008-04-08 10:31:00 +020087 /* Begin command latch cycle */
Alex Waterman837097832011-05-04 09:10:15 -040088 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Stefan Roese46f37382008-04-08 10:31:00 +020089 /* Set ALE and clear CLE to start address cycle */
Stefan Roese46f37382008-04-08 10:31:00 +020090 /* Column address */
Alex Waterman837097832011-05-04 09:10:15 -040091 hwctrl(mtd, offs & 0xff,
Wolfgang Denk4b070802008-08-14 14:41:06 +020092 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
Alex Waterman837097832011-05-04 09:10:15 -040093 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
Stefan Roese46f37382008-04-08 10:31:00 +020094 /* Row address */
Alex Waterman837097832011-05-04 09:10:15 -040095 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
96 hwctrl(mtd, ((page_addr >> 8) & 0xff),
Scott Wood1dac3a52009-06-24 17:23:49 -050097 NAND_CTRL_ALE); /* A[27:20] */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
Stefan Roese46f37382008-04-08 10:31:00 +020099 /* One more address cycle for devices > 128MiB */
Alex Waterman837097832011-05-04 09:10:15 -0400100 hwctrl(mtd, (page_addr >> 16) & 0x0f,
Scott Wood1dac3a52009-06-24 17:23:49 -0500101 NAND_CTRL_ALE); /* A[31:28] */
Stefan Roese46f37382008-04-08 10:31:00 +0200102#endif
103 /* Latch in address */
Alex Waterman837097832011-05-04 09:10:15 -0400104 hwctrl(mtd, NAND_CMD_READSTART,
Wolfgang Denk4b070802008-08-14 14:41:06 +0200105 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Alex Waterman837097832011-05-04 09:10:15 -0400106 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Stefan Roese46f37382008-04-08 10:31:00 +0200107
108 /*
109 * Wait a while for the data to be ready
110 */
Stefan Roesea9c847c2011-05-04 11:44:14 +0200111 while (!this->dev_ready(mtd))
112 ;
Stefan Roese46f37382008-04-08 10:31:00 +0200113
114 return 0;
115}
116#endif
Stefan Roese42be56f2007-06-01 15:23:04 +0200117
118static int nand_is_bad_block(struct mtd_info *mtd, int block)
119{
120 struct nand_chip *this = mtd->priv;
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
Stefan Roese42be56f2007-06-01 15:23:04 +0200123
Stefan Roese887e2ec2006-09-07 11:51:23 +0200124 /*
Alex Watermaneced4622011-05-19 15:08:36 -0400125 * Read one byte (or two if it's a 16 bit chip).
Stefan Roese887e2ec2006-09-07 11:51:23 +0200126 */
Alex Watermaneced4622011-05-19 15:08:36 -0400127 if (this->options & NAND_BUSWIDTH_16) {
128 if (readw(this->IO_ADDR_R) != 0xffff)
129 return 1;
130 } else {
131 if (readb(this->IO_ADDR_R) != 0xff)
132 return 1;
133 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200134
135 return 0;
136}
137
138static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
139{
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200140 struct nand_chip *this = mtd->priv;
Stefan Roese42be56f2007-06-01 15:23:04 +0200141 u_char *ecc_calc;
142 u_char *ecc_code;
143 u_char *oob_data;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200144 int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
146 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
147 int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
Stefan Roese42be56f2007-06-01 15:23:04 +0200148 uint8_t *p = dst;
149 int stat;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200150
Stefan Roese42be56f2007-06-01 15:23:04 +0200151 nand_command(mtd, block, page, 0, NAND_CMD_READ0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200152
Stefan Roese42be56f2007-06-01 15:23:04 +0200153 /* No malloc available for now, just use some temporary locations
154 * in SDRAM
Stefan Roese887e2ec2006-09-07 11:51:23 +0200155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
Stefan Roese42be56f2007-06-01 15:23:04 +0200157 ecc_code = ecc_calc + 0x100;
158 oob_data = ecc_calc + 0x200;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159
Stefan Roese42be56f2007-06-01 15:23:04 +0200160 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
Stefan Roesec568f772008-01-05 16:49:37 +0100161 this->ecc.hwctl(mtd, NAND_ECC_READ);
Stefan Roese42be56f2007-06-01 15:23:04 +0200162 this->read_buf(mtd, p, eccsize);
Stefan Roesec568f772008-01-05 16:49:37 +0100163 this->ecc.calculate(mtd, p, &ecc_calc[i]);
Stefan Roese42be56f2007-06-01 15:23:04 +0200164 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
Stefan Roese42be56f2007-06-01 15:23:04 +0200166
167 /* Pick the ECC bytes out of the oob data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
Stefan Roese42be56f2007-06-01 15:23:04 +0200169 ecc_code[i] = oob_data[nand_ecc_pos[i]];
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
Stefan Roese42be56f2007-06-01 15:23:04 +0200172 p = dst;
173
174 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
175 /* No chance to do something with the possible error message
176 * from correct_data(). We just hope that all possible errors
177 * are corrected by this routine.
178 */
Stefan Roesec568f772008-01-05 16:49:37 +0100179 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Stefan Roese42be56f2007-06-01 15:23:04 +0200180 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200181
182 return 0;
183}
184
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200185static int nand_load(struct mtd_info *mtd, unsigned int offs,
Wolfgang Denk4b070802008-08-14 14:41:06 +0200186 unsigned int uboot_size, uchar *dst)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200187{
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200188 unsigned int block, lastblock;
189 unsigned int page;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200190
191 /*
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200192 * offs has to be aligned to a page address!
Stefan Roese887e2ec2006-09-07 11:51:23 +0200193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
195 lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
196 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200197
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200198 while (block <= lastblock) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200199 if (!nand_is_bad_block(mtd, block)) {
200 /*
201 * Skip bad blocks
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200204 nand_read_page(mtd, block, page, dst);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 dst += CONFIG_SYS_NAND_PAGE_SIZE;
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200206 page++;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200207 }
208
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200209 page = 0;
210 } else {
211 lastblock++;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200212 }
213
214 block++;
215 }
216
217 return 0;
218}
219
Stefan Roese64852d02008-06-02 14:35:44 +0200220/*
221 * The main entry for NAND booting. It's necessary that SDRAM is already
222 * configured and available since this code loads the main U-Boot image
223 * from NAND into SDRAM and starts it from there.
224 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200225void nand_boot(void)
226{
Stefan Roese887e2ec2006-09-07 11:51:23 +0200227 struct nand_chip nand_chip;
228 nand_info_t nand_info;
229 int ret;
Scott Woode4c09502008-06-30 14:13:28 -0500230 __attribute__((noreturn)) void (*uboot)(void);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200231
232 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200233 * Init board specific nand support
234 */
Sughosh Ganu48571ff2010-11-30 11:25:01 -0500235 nand_chip.select_chip = NULL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200236 nand_info.priv = &nand_chip;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200238 nand_chip.dev_ready = NULL; /* preset to NULL */
Stefan Roesea89a9902011-05-04 11:44:44 +0200239 nand_chip.options = 0;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200240 board_nand_init(&nand_chip);
241
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200242 if (nand_chip.select_chip)
243 nand_chip.select_chip(&nand_info, 0);
244
Stefan Roese887e2ec2006-09-07 11:51:23 +0200245 /*
246 * Load U-Boot image from NAND into RAM
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
249 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200250
Guennadi Liakhovetskib74ab732009-05-18 16:07:22 +0200251#ifdef CONFIG_NAND_ENV_DST
252 nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
253 (uchar *)CONFIG_NAND_ENV_DST);
254
255#ifdef CONFIG_ENV_OFFSET_REDUND
256 nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
257 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
258#endif
259#endif
260
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200261 if (nand_chip.select_chip)
262 nand_chip.select_chip(&nand_info, -1);
263
Stefan Roese887e2ec2006-09-07 11:51:23 +0200264 /*
265 * Jump to U-Boot image
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200268 (*uboot)();
269}