blob: 72cbcdf6a21a75adaf5075b67f7ccbbed086d428 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunaya6151912018-03-12 10:46:15 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunaya6151912018-03-12 10:46:15 +01004 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <div64.h>
9#include <dm.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Patrick Delaunaya6151912018-03-12 10:46:15 +010012#include <regmap.h>
13#include <spl.h>
14#include <syscon.h>
Simon Glass10453152019-11-14 12:57:30 -070015#include <time.h>
Simon Glass2189d5f2019-11-14 12:57:20 -070016#include <vsprintf.h>
Simon Glasscd93d622020-05-10 11:40:13 -060017#include <linux/bitops.h>
Patrick Delaunaya6151912018-03-12 10:46:15 +010018#include <linux/io.h>
Patrick Delaunay266fa4d2018-03-12 10:46:16 +010019#include <linux/iopoll.h>
Patrick Delaunay37ad8372020-05-25 12:19:44 +020020#include <asm/arch/sys_proto.h>
Patrick Delaunaya6151912018-03-12 10:46:15 +010021#include <dt-bindings/clock/stm32mp1-clks.h>
Patrick Delaunay266fa4d2018-03-12 10:46:16 +010022#include <dt-bindings/clock/stm32mp1-clksrc.h>
23
Patrick Delaunay4de076e2019-07-30 19:16:55 +020024DECLARE_GLOBAL_DATA_PTR;
25
Patrick Delaunay654706b2020-04-01 09:07:33 +020026#ifndef CONFIG_TFABOOT
Patrick Delaunay266fa4d2018-03-12 10:46:16 +010027#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
28/* activate clock tree initialization in the driver */
29#define STM32MP1_CLOCK_TREE_INIT
30#endif
Patrick Delaunayabf26782019-02-12 11:44:39 +010031#endif
Patrick Delaunaya6151912018-03-12 10:46:15 +010032
33#define MAX_HSI_HZ 64000000
34
Patrick Delaunay266fa4d2018-03-12 10:46:16 +010035/* TIMEOUT */
36#define TIMEOUT_200MS 200000
37#define TIMEOUT_1S 1000000
38
Patrick Delaunay938e0e32018-03-20 11:41:25 +010039/* STGEN registers */
40#define STGENC_CNTCR 0x00
41#define STGENC_CNTSR 0x04
42#define STGENC_CNTCVL 0x08
43#define STGENC_CNTCVU 0x0C
44#define STGENC_CNTFID0 0x20
45
46#define STGENC_CNTCR_EN BIT(0)
47
Patrick Delaunaya6151912018-03-12 10:46:15 +010048/* RCC registers */
49#define RCC_OCENSETR 0x0C
50#define RCC_OCENCLRR 0x10
51#define RCC_HSICFGR 0x18
52#define RCC_MPCKSELR 0x20
53#define RCC_ASSCKSELR 0x24
54#define RCC_RCK12SELR 0x28
55#define RCC_MPCKDIVR 0x2C
56#define RCC_AXIDIVR 0x30
57#define RCC_APB4DIVR 0x3C
58#define RCC_APB5DIVR 0x40
59#define RCC_RTCDIVR 0x44
60#define RCC_MSSCKSELR 0x48
61#define RCC_PLL1CR 0x80
62#define RCC_PLL1CFGR1 0x84
63#define RCC_PLL1CFGR2 0x88
64#define RCC_PLL1FRACR 0x8C
65#define RCC_PLL1CSGR 0x90
66#define RCC_PLL2CR 0x94
67#define RCC_PLL2CFGR1 0x98
68#define RCC_PLL2CFGR2 0x9C
69#define RCC_PLL2FRACR 0xA0
70#define RCC_PLL2CSGR 0xA4
71#define RCC_I2C46CKSELR 0xC0
72#define RCC_CPERCKSELR 0xD0
73#define RCC_STGENCKSELR 0xD4
74#define RCC_DDRITFCR 0xD8
75#define RCC_BDCR 0x140
76#define RCC_RDLSICR 0x144
77#define RCC_MP_APB4ENSETR 0x200
78#define RCC_MP_APB5ENSETR 0x208
79#define RCC_MP_AHB5ENSETR 0x210
80#define RCC_MP_AHB6ENSETR 0x218
81#define RCC_OCRDYR 0x808
82#define RCC_DBGCFGR 0x80C
83#define RCC_RCK3SELR 0x820
84#define RCC_RCK4SELR 0x824
85#define RCC_MCUDIVR 0x830
86#define RCC_APB1DIVR 0x834
87#define RCC_APB2DIVR 0x838
88#define RCC_APB3DIVR 0x83C
89#define RCC_PLL3CR 0x880
90#define RCC_PLL3CFGR1 0x884
91#define RCC_PLL3CFGR2 0x888
92#define RCC_PLL3FRACR 0x88C
93#define RCC_PLL3CSGR 0x890
94#define RCC_PLL4CR 0x894
95#define RCC_PLL4CFGR1 0x898
96#define RCC_PLL4CFGR2 0x89C
97#define RCC_PLL4FRACR 0x8A0
98#define RCC_PLL4CSGR 0x8A4
99#define RCC_I2C12CKSELR 0x8C0
100#define RCC_I2C35CKSELR 0x8C4
Patrice Chotard248278d2019-04-30 18:08:27 +0200101#define RCC_SPI2S1CKSELR 0x8D8
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100102#define RCC_SPI45CKSELR 0x8E0
Patrick Delaunaya6151912018-03-12 10:46:15 +0100103#define RCC_UART6CKSELR 0x8E4
104#define RCC_UART24CKSELR 0x8E8
105#define RCC_UART35CKSELR 0x8EC
106#define RCC_UART78CKSELR 0x8F0
107#define RCC_SDMMC12CKSELR 0x8F4
108#define RCC_SDMMC3CKSELR 0x8F8
109#define RCC_ETHCKSELR 0x8FC
110#define RCC_QSPICKSELR 0x900
111#define RCC_FMCCKSELR 0x904
112#define RCC_USBCKSELR 0x91C
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200113#define RCC_DSICKSELR 0x924
Patrick Delaunay5b25eb92018-07-16 10:41:45 +0200114#define RCC_ADCCKSELR 0x928
Patrick Delaunaya6151912018-03-12 10:46:15 +0100115#define RCC_MP_APB1ENSETR 0xA00
116#define RCC_MP_APB2ENSETR 0XA08
Fabrice Gasnierf198bba2018-04-26 17:00:47 +0200117#define RCC_MP_APB3ENSETR 0xA10
Patrick Delaunaya6151912018-03-12 10:46:15 +0100118#define RCC_MP_AHB2ENSETR 0xA18
Benjamin Gaignard283bcd92018-11-27 13:49:51 +0100119#define RCC_MP_AHB3ENSETR 0xA20
Patrick Delaunaya6151912018-03-12 10:46:15 +0100120#define RCC_MP_AHB4ENSETR 0xA28
121
122/* used for most of SELR register */
123#define RCC_SELR_SRC_MASK GENMASK(2, 0)
124#define RCC_SELR_SRCRDY BIT(31)
125
126/* Values of RCC_MPCKSELR register */
127#define RCC_MPCKSELR_HSI 0
128#define RCC_MPCKSELR_HSE 1
129#define RCC_MPCKSELR_PLL 2
130#define RCC_MPCKSELR_PLL_MPUDIV 3
131
132/* Values of RCC_ASSCKSELR register */
133#define RCC_ASSCKSELR_HSI 0
134#define RCC_ASSCKSELR_HSE 1
135#define RCC_ASSCKSELR_PLL 2
136
137/* Values of RCC_MSSCKSELR register */
138#define RCC_MSSCKSELR_HSI 0
139#define RCC_MSSCKSELR_HSE 1
140#define RCC_MSSCKSELR_CSI 2
141#define RCC_MSSCKSELR_PLL 3
142
143/* Values of RCC_CPERCKSELR register */
144#define RCC_CPERCKSELR_HSI 0
145#define RCC_CPERCKSELR_CSI 1
146#define RCC_CPERCKSELR_HSE 2
147
148/* used for most of DIVR register : max div for RTC */
149#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
150#define RCC_DIVR_DIVRDY BIT(31)
151
152/* Masks for specific DIVR registers */
153#define RCC_APBXDIV_MASK GENMASK(2, 0)
154#define RCC_MPUDIV_MASK GENMASK(2, 0)
155#define RCC_AXIDIV_MASK GENMASK(2, 0)
156#define RCC_MCUDIV_MASK GENMASK(3, 0)
157
158/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
159#define RCC_MP_ENCLRR_OFFSET 4
160
161/* Fields of RCC_BDCR register */
162#define RCC_BDCR_LSEON BIT(0)
163#define RCC_BDCR_LSEBYP BIT(1)
164#define RCC_BDCR_LSERDY BIT(2)
Patrick Delaunayd2194152018-07-16 10:41:46 +0200165#define RCC_BDCR_DIGBYP BIT(3)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100166#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
167#define RCC_BDCR_LSEDRV_SHIFT 4
168#define RCC_BDCR_LSECSSON BIT(8)
169#define RCC_BDCR_RTCCKEN BIT(20)
170#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
171#define RCC_BDCR_RTCSRC_SHIFT 16
172
173/* Fields of RCC_RDLSICR register */
174#define RCC_RDLSICR_LSION BIT(0)
175#define RCC_RDLSICR_LSIRDY BIT(1)
176
177/* used for ALL PLLNCR registers */
178#define RCC_PLLNCR_PLLON BIT(0)
179#define RCC_PLLNCR_PLLRDY BIT(1)
Patrick Delaunaybbd108a2019-01-30 13:07:06 +0100180#define RCC_PLLNCR_SSCG_CTRL BIT(2)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100181#define RCC_PLLNCR_DIVPEN BIT(4)
182#define RCC_PLLNCR_DIVQEN BIT(5)
183#define RCC_PLLNCR_DIVREN BIT(6)
184#define RCC_PLLNCR_DIVEN_SHIFT 4
185
186/* used for ALL PLLNCFGR1 registers */
187#define RCC_PLLNCFGR1_DIVM_SHIFT 16
188#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
189#define RCC_PLLNCFGR1_DIVN_SHIFT 0
190#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
191/* only for PLL3 and PLL4 */
192#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
193#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
194
Patrick Delaunayc2fa5dc2018-07-16 10:41:41 +0200195/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
196#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100197#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
Patrick Delaunayc2fa5dc2018-07-16 10:41:41 +0200198#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100199#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
Patrick Delaunayc2fa5dc2018-07-16 10:41:41 +0200200#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100201#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
Patrick Delaunayc2fa5dc2018-07-16 10:41:41 +0200202#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100203#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
204
205/* used for ALL PLLNFRACR registers */
206#define RCC_PLLNFRACR_FRACV_SHIFT 3
207#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
208#define RCC_PLLNFRACR_FRACLE BIT(16)
209
210/* used for ALL PLLNCSGR registers */
211#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
212#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
213#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
214#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
215#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
216#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
217
218/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
219#define RCC_OCENR_HSION BIT(0)
220#define RCC_OCENR_CSION BIT(4)
Patrick Delaunayd2194152018-07-16 10:41:46 +0200221#define RCC_OCENR_DIGBYP BIT(7)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100222#define RCC_OCENR_HSEON BIT(8)
223#define RCC_OCENR_HSEBYP BIT(10)
224#define RCC_OCENR_HSECSSON BIT(11)
225
226/* Fields of RCC_OCRDYR register */
227#define RCC_OCRDYR_HSIRDY BIT(0)
228#define RCC_OCRDYR_HSIDIVRDY BIT(2)
229#define RCC_OCRDYR_CSIRDY BIT(4)
230#define RCC_OCRDYR_HSERDY BIT(8)
231
232/* Fields of DDRITFCR register */
233#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
234#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
235#define RCC_DDRITFCR_DDRCKMOD_SSR 0
236
237/* Fields of RCC_HSICFGR register */
238#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
239
240/* used for MCO related operations */
241#define RCC_MCOCFG_MCOON BIT(12)
242#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
243#define RCC_MCOCFG_MCODIV_SHIFT 4
244#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
245
246enum stm32mp1_parent_id {
247/*
248 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
249 * they are used as index in osc[] as entry point
250 */
251 _HSI,
252 _HSE,
253 _CSI,
254 _LSI,
255 _LSE,
256 _I2S_CKIN,
Patrick Delaunaya6151912018-03-12 10:46:15 +0100257 NB_OSC,
258
259/* other parent source */
260 _HSI_KER = NB_OSC,
261 _HSE_KER,
262 _HSE_KER_DIV2,
263 _CSI_KER,
264 _PLL1_P,
265 _PLL1_Q,
266 _PLL1_R,
267 _PLL2_P,
268 _PLL2_Q,
269 _PLL2_R,
270 _PLL3_P,
271 _PLL3_Q,
272 _PLL3_R,
273 _PLL4_P,
274 _PLL4_Q,
275 _PLL4_R,
276 _ACLK,
277 _PCLK1,
278 _PCLK2,
279 _PCLK3,
280 _PCLK4,
281 _PCLK5,
282 _HCLK6,
283 _HCLK2,
284 _CK_PER,
285 _CK_MPU,
286 _CK_MCU,
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200287 _DSI_PHY,
Patrick Delaunay86617dd2019-01-30 13:07:00 +0100288 _USB_PHY_48,
Patrick Delaunaya6151912018-03-12 10:46:15 +0100289 _PARENT_NB,
290 _UNKNOWN_ID = 0xff,
291};
292
293enum stm32mp1_parent_sel {
294 _I2C12_SEL,
295 _I2C35_SEL,
296 _I2C46_SEL,
297 _UART6_SEL,
298 _UART24_SEL,
299 _UART35_SEL,
300 _UART78_SEL,
301 _SDMMC12_SEL,
302 _SDMMC3_SEL,
303 _ETH_SEL,
304 _QSPI_SEL,
305 _FMC_SEL,
306 _USBPHY_SEL,
307 _USBO_SEL,
308 _STGEN_SEL,
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200309 _DSI_SEL,
Patrick Delaunay5b25eb92018-07-16 10:41:45 +0200310 _ADC12_SEL,
Patrice Chotard248278d2019-04-30 18:08:27 +0200311 _SPI1_SEL,
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100312 _SPI45_SEL,
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200313 _RTC_SEL,
Patrick Delaunaya6151912018-03-12 10:46:15 +0100314 _PARENT_SEL_NB,
315 _UNKNOWN_SEL = 0xff,
316};
317
318enum stm32mp1_pll_id {
319 _PLL1,
320 _PLL2,
321 _PLL3,
322 _PLL4,
323 _PLL_NB
324};
325
326enum stm32mp1_div_id {
327 _DIV_P,
328 _DIV_Q,
329 _DIV_R,
330 _DIV_NB,
331};
332
333enum stm32mp1_clksrc_id {
334 CLKSRC_MPU,
335 CLKSRC_AXI,
336 CLKSRC_MCU,
337 CLKSRC_PLL12,
338 CLKSRC_PLL3,
339 CLKSRC_PLL4,
340 CLKSRC_RTC,
341 CLKSRC_MCO1,
342 CLKSRC_MCO2,
343 CLKSRC_NB
344};
345
346enum stm32mp1_clkdiv_id {
347 CLKDIV_MPU,
348 CLKDIV_AXI,
349 CLKDIV_MCU,
350 CLKDIV_APB1,
351 CLKDIV_APB2,
352 CLKDIV_APB3,
353 CLKDIV_APB4,
354 CLKDIV_APB5,
355 CLKDIV_RTC,
356 CLKDIV_MCO1,
357 CLKDIV_MCO2,
358 CLKDIV_NB
359};
360
361enum stm32mp1_pllcfg {
362 PLLCFG_M,
363 PLLCFG_N,
364 PLLCFG_P,
365 PLLCFG_Q,
366 PLLCFG_R,
367 PLLCFG_O,
368 PLLCFG_NB
369};
370
371enum stm32mp1_pllcsg {
372 PLLCSG_MOD_PER,
373 PLLCSG_INC_STEP,
374 PLLCSG_SSCG_MODE,
375 PLLCSG_NB
376};
377
378enum stm32mp1_plltype {
379 PLL_800,
380 PLL_1600,
381 PLL_TYPE_NB
382};
383
384struct stm32mp1_pll {
385 u8 refclk_min;
386 u8 refclk_max;
387 u8 divn_max;
388};
389
390struct stm32mp1_clk_gate {
391 u16 offset;
392 u8 bit;
393 u8 index;
394 u8 set_clr;
395 u8 sel;
396 u8 fixed;
397};
398
399struct stm32mp1_clk_sel {
400 u16 offset;
401 u8 src;
402 u8 msk;
403 u8 nb_parent;
404 const u8 *parent;
405};
406
407#define REFCLK_SIZE 4
408struct stm32mp1_clk_pll {
409 enum stm32mp1_plltype plltype;
410 u16 rckxselr;
411 u16 pllxcfgr1;
412 u16 pllxcfgr2;
413 u16 pllxfracr;
414 u16 pllxcr;
415 u16 pllxcsgr;
416 u8 refclk[REFCLK_SIZE];
417};
418
419struct stm32mp1_clk_data {
420 const struct stm32mp1_clk_gate *gate;
421 const struct stm32mp1_clk_sel *sel;
422 const struct stm32mp1_clk_pll *pll;
423 const int nb_gate;
424};
425
426struct stm32mp1_clk_priv {
427 fdt_addr_t base;
428 const struct stm32mp1_clk_data *data;
429 ulong osc[NB_OSC];
430 struct udevice *osc_dev[NB_OSC];
431};
432
433#define STM32MP1_CLK(off, b, idx, s) \
434 { \
435 .offset = (off), \
436 .bit = (b), \
437 .index = (idx), \
438 .set_clr = 0, \
439 .sel = (s), \
440 .fixed = _UNKNOWN_ID, \
441 }
442
443#define STM32MP1_CLK_F(off, b, idx, f) \
444 { \
445 .offset = (off), \
446 .bit = (b), \
447 .index = (idx), \
448 .set_clr = 0, \
449 .sel = _UNKNOWN_SEL, \
450 .fixed = (f), \
451 }
452
453#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
454 { \
455 .offset = (off), \
456 .bit = (b), \
457 .index = (idx), \
458 .set_clr = 1, \
459 .sel = (s), \
460 .fixed = _UNKNOWN_ID, \
461 }
462
463#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
464 { \
465 .offset = (off), \
466 .bit = (b), \
467 .index = (idx), \
468 .set_clr = 1, \
469 .sel = _UNKNOWN_SEL, \
470 .fixed = (f), \
471 }
472
473#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
474 [(idx)] = { \
475 .offset = (off), \
476 .src = (s), \
477 .msk = (m), \
478 .parent = (p), \
479 .nb_parent = ARRAY_SIZE((p)) \
480 }
481
482#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
483 p1, p2, p3, p4) \
484 [(idx)] = { \
485 .plltype = (type), \
486 .rckxselr = (off1), \
487 .pllxcfgr1 = (off2), \
488 .pllxcfgr2 = (off3), \
489 .pllxfracr = (off4), \
490 .pllxcr = (off5), \
491 .pllxcsgr = (off6), \
492 .refclk[0] = (p1), \
493 .refclk[1] = (p2), \
494 .refclk[2] = (p3), \
495 .refclk[3] = (p4), \
496 }
497
498static const u8 stm32mp1_clks[][2] = {
499 {CK_PER, _CK_PER},
500 {CK_MPU, _CK_MPU},
501 {CK_AXI, _ACLK},
502 {CK_MCU, _CK_MCU},
503 {CK_HSE, _HSE},
504 {CK_CSI, _CSI},
505 {CK_LSI, _LSI},
506 {CK_LSE, _LSE},
507 {CK_HSI, _HSI},
508 {CK_HSE_DIV2, _HSE_KER_DIV2},
509};
510
511static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
512 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
513 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
514 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
515 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
516 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
517 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
518 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
519 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
520 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
521 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
522 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
523
524 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
525 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
526 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
527 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
529 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
530 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
532 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
533 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
534
Patrice Chotard248278d2019-04-30 18:08:27 +0200535 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100536 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100537 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
538
Fabrice Gasnierf198bba2018-04-26 17:00:47 +0200539 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
540
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200541 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
542 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
543 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100544 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
546 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
547
548 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200549 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100550 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
551
Patrick Delaunay5b25eb92018-07-16 10:41:45 +0200552 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
556
Benjamin Gaignard283bcd92018-11-27 13:49:51 +0100557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
Patrick Delaunayd661f612019-01-30 13:07:01 +0100558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
Benjamin Gaignard283bcd92018-11-27 13:49:51 +0100559
Patrick Delaunaya6151912018-03-12 10:46:15 +0100560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
564 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
567 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
568 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
570 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
571
572 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
Sughosh Ganu82ebf0f2019-12-28 23:58:28 +0530573 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100574
Patrick Delaunayf6ccdda2019-05-17 15:08:42 +0200575 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100576 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
577 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100578 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
579 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
580 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
581 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
582 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
583 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
584
585 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200586
587 STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100588};
589
590static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
591static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
592static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
593static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
594 _HSE_KER};
595static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
596 _HSE_KER};
597static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
598 _HSE_KER};
599static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
600 _HSE_KER};
601static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
602static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
603static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
604static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
605static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
606static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
607static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
608static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200609static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
Patrick Delaunay5b25eb92018-07-16 10:41:45 +0200610static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
Patrice Chotard248278d2019-04-30 18:08:27 +0200611static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
612 _PLL3_R};
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100613static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
614 _HSE_KER};
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200615static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
Patrick Delaunaya6151912018-03-12 10:46:15 +0100616
617static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
618 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
619 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
620 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
621 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
622 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
623 uart24_parents),
624 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
625 uart35_parents),
626 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
627 uart78_parents),
628 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
629 sdmmc12_parents),
630 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
631 sdmmc3_parents),
632 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
Patrick Delaunay69ffb552020-03-09 14:59:22 +0100633 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
634 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100635 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
636 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
637 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200638 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
Patrick Delaunay69ffb552020-03-09 14:59:22 +0100639 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
Patrice Chotard248278d2019-04-30 18:08:27 +0200640 STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100641 STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200642 STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
643 (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
644 rtc_parents),
Patrick Delaunaya6151912018-03-12 10:46:15 +0100645};
646
647#ifdef STM32MP1_CLOCK_TREE_INIT
Patrick Delaunay37ad8372020-05-25 12:19:44 +0200648
Patrick Delaunaya6151912018-03-12 10:46:15 +0100649/* define characteristic of PLL according type */
Patrick Delaunay37ad8372020-05-25 12:19:44 +0200650#define DIVM_MIN 0
651#define DIVM_MAX 63
Patrick Delaunaya6151912018-03-12 10:46:15 +0100652#define DIVN_MIN 24
Patrick Delaunay37ad8372020-05-25 12:19:44 +0200653#define DIVP_MIN 0
654#define DIVP_MAX 127
655#define FRAC_MAX 8192
656
657#define PLL1600_VCO_MIN 800000000
658#define PLL1600_VCO_MAX 1600000000
659
Patrick Delaunaya6151912018-03-12 10:46:15 +0100660static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
661 [PLL_800] = {
662 .refclk_min = 4,
663 .refclk_max = 16,
664 .divn_max = 99,
665 },
666 [PLL_1600] = {
667 .refclk_min = 8,
668 .refclk_max = 16,
669 .divn_max = 199,
670 },
671};
672#endif /* STM32MP1_CLOCK_TREE_INIT */
673
674static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
675 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
676 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
677 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
678 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
679 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
680 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
681 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
682 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
683 STM32MP1_CLK_PLL(_PLL3, PLL_800,
684 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
685 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
686 _HSI, _HSE, _CSI, _UNKNOWN_ID),
687 STM32MP1_CLK_PLL(_PLL4, PLL_800,
688 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
689 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
690 _HSI, _HSE, _CSI, _I2S_CKIN),
691};
692
693/* Prescaler table lookups for clock computation */
694/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
695static const u8 stm32mp1_mcu_div[16] = {
696 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
697};
698
699/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
700#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
701#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
702static const u8 stm32mp1_mpu_apbx_div[8] = {
703 0, 1, 2, 3, 4, 4, 4, 4
704};
705
706/* div = /1 /2 /3 /4 */
707static const u8 stm32mp1_axi_div[8] = {
708 1, 2, 3, 4, 4, 4, 4, 4
709};
710
Patrick Delaunay8d6310a2019-01-30 13:07:04 +0100711static const __maybe_unused
712char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
Patrick Delaunaya6151912018-03-12 10:46:15 +0100713 [_HSI] = "HSI",
714 [_HSE] = "HSE",
715 [_CSI] = "CSI",
716 [_LSI] = "LSI",
717 [_LSE] = "LSE",
718 [_I2S_CKIN] = "I2S_CKIN",
719 [_HSI_KER] = "HSI_KER",
720 [_HSE_KER] = "HSE_KER",
721 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
722 [_CSI_KER] = "CSI_KER",
723 [_PLL1_P] = "PLL1_P",
724 [_PLL1_Q] = "PLL1_Q",
725 [_PLL1_R] = "PLL1_R",
726 [_PLL2_P] = "PLL2_P",
727 [_PLL2_Q] = "PLL2_Q",
728 [_PLL2_R] = "PLL2_R",
729 [_PLL3_P] = "PLL3_P",
730 [_PLL3_Q] = "PLL3_Q",
731 [_PLL3_R] = "PLL3_R",
732 [_PLL4_P] = "PLL4_P",
733 [_PLL4_Q] = "PLL4_Q",
734 [_PLL4_R] = "PLL4_R",
735 [_ACLK] = "ACLK",
736 [_PCLK1] = "PCLK1",
737 [_PCLK2] = "PCLK2",
738 [_PCLK3] = "PCLK3",
739 [_PCLK4] = "PCLK4",
740 [_PCLK5] = "PCLK5",
741 [_HCLK6] = "KCLK6",
742 [_HCLK2] = "HCLK2",
743 [_CK_PER] = "CK_PER",
744 [_CK_MPU] = "CK_MPU",
745 [_CK_MCU] = "CK_MCU",
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200746 [_USB_PHY_48] = "USB_PHY_48",
747 [_DSI_PHY] = "DSI_PHY_PLL",
Patrick Delaunaya6151912018-03-12 10:46:15 +0100748};
749
Patrick Delaunay8d6310a2019-01-30 13:07:04 +0100750static const __maybe_unused
751char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
Patrick Delaunaya6151912018-03-12 10:46:15 +0100752 [_I2C12_SEL] = "I2C12",
753 [_I2C35_SEL] = "I2C35",
754 [_I2C46_SEL] = "I2C46",
755 [_UART6_SEL] = "UART6",
756 [_UART24_SEL] = "UART24",
757 [_UART35_SEL] = "UART35",
758 [_UART78_SEL] = "UART78",
759 [_SDMMC12_SEL] = "SDMMC12",
760 [_SDMMC3_SEL] = "SDMMC3",
761 [_ETH_SEL] = "ETH",
762 [_QSPI_SEL] = "QSPI",
763 [_FMC_SEL] = "FMC",
764 [_USBPHY_SEL] = "USBPHY",
765 [_USBO_SEL] = "USBO",
Patrick Delaunay88fa34d2018-07-16 10:41:43 +0200766 [_STGEN_SEL] = "STGEN",
767 [_DSI_SEL] = "DSI",
Patrick Delaunay5b25eb92018-07-16 10:41:45 +0200768 [_ADC12_SEL] = "ADC12",
Patrice Chotard248278d2019-04-30 18:08:27 +0200769 [_SPI1_SEL] = "SPI1",
Patrick Delaunay0c90e0c2020-03-09 14:59:23 +0100770 [_SPI45_SEL] = "SPI45",
Patrick Delaunayfd7fe1b2019-07-11 12:03:37 +0200771 [_RTC_SEL] = "RTC",
Patrick Delaunaya6151912018-03-12 10:46:15 +0100772};
Patrick Delaunaya6151912018-03-12 10:46:15 +0100773
774static const struct stm32mp1_clk_data stm32mp1_data = {
775 .gate = stm32mp1_clk_gate,
776 .sel = stm32mp1_clk_sel,
777 .pll = stm32mp1_clk_pll,
778 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
779};
780
781static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
782{
783 if (idx >= NB_OSC) {
784 debug("%s: clk id %d not found\n", __func__, idx);
785 return 0;
786 }
787
Patrick Delaunaya6151912018-03-12 10:46:15 +0100788 return priv->osc[idx];
789}
790
791static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
792{
793 const struct stm32mp1_clk_gate *gate = priv->data->gate;
794 int i, nb_clks = priv->data->nb_gate;
795
796 for (i = 0; i < nb_clks; i++) {
797 if (gate[i].index == id)
798 break;
799 }
800
801 if (i == nb_clks) {
802 printf("%s: clk id %d not found\n", __func__, (u32)id);
803 return -EINVAL;
804 }
805
806 return i;
807}
808
809static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
810 int i)
811{
812 const struct stm32mp1_clk_gate *gate = priv->data->gate;
813
814 if (gate[i].sel > _PARENT_SEL_NB) {
815 printf("%s: parents for clk id %d not found\n",
816 __func__, i);
817 return -EINVAL;
818 }
819
820 return gate[i].sel;
821}
822
823static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
824 int i)
825{
826 const struct stm32mp1_clk_gate *gate = priv->data->gate;
827
828 if (gate[i].fixed == _UNKNOWN_ID)
829 return -ENOENT;
830
831 return gate[i].fixed;
832}
833
834static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
835 unsigned long id)
836{
837 const struct stm32mp1_clk_sel *sel = priv->data->sel;
838 int i;
839 int s, p;
Patrick Delaunay67d74ce2019-06-21 15:26:48 +0200840 unsigned int idx;
Patrick Delaunaya6151912018-03-12 10:46:15 +0100841
Patrick Delaunay67d74ce2019-06-21 15:26:48 +0200842 for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
843 if (stm32mp1_clks[idx][0] == id)
844 return stm32mp1_clks[idx][1];
Patrick Delaunaya6151912018-03-12 10:46:15 +0100845
846 i = stm32mp1_clk_get_id(priv, id);
847 if (i < 0)
848 return i;
849
850 p = stm32mp1_clk_get_fixed_parent(priv, i);
851 if (p >= 0 && p < _PARENT_NB)
852 return p;
853
854 s = stm32mp1_clk_get_sel(priv, i);
855 if (s < 0)
856 return s;
857
858 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
859
860 if (p < sel[s].nb_parent) {
861#ifdef DEBUG
862 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
863 stm32mp1_clk_parent_name[sel[s].parent[p]],
864 stm32mp1_clk_parent_sel_name[s],
865 (u32)id);
866#endif
867 return sel[s].parent[p];
868 }
869
870 pr_err("%s: no parents defined for clk id %d\n",
871 __func__, (u32)id);
872
873 return -EINVAL;
874}
875
Patrick Delaunay61105032018-07-16 10:41:42 +0200876static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
877 int pll_id)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100878{
879 const struct stm32mp1_clk_pll *pll = priv->data->pll;
Patrick Delaunay61105032018-07-16 10:41:42 +0200880 u32 selr;
881 int src;
882 ulong refclk;
Patrick Delaunaya6151912018-03-12 10:46:15 +0100883
Patrick Delaunay61105032018-07-16 10:41:42 +0200884 /* Get current refclk */
Patrick Delaunaya6151912018-03-12 10:46:15 +0100885 selr = readl(priv->base + pll[pll_id].rckxselr);
Patrick Delaunay61105032018-07-16 10:41:42 +0200886 src = selr & RCC_SELR_SRC_MASK;
Patrick Delaunaya6151912018-03-12 10:46:15 +0100887
Patrick Delaunay61105032018-07-16 10:41:42 +0200888 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
Patrick Delaunay61105032018-07-16 10:41:42 +0200889
890 return refclk;
891}
892
893/*
894 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
895 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
896 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
897 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
898 */
899static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
900 int pll_id)
901{
902 const struct stm32mp1_clk_pll *pll = priv->data->pll;
903 int divm, divn;
904 ulong refclk, fvco;
905 u32 cfgr1, fracr;
906
907 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
908 fracr = readl(priv->base + pll[pll_id].pllxfracr);
Patrick Delaunaya6151912018-03-12 10:46:15 +0100909
910 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
911 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
Patrick Delaunaya6151912018-03-12 10:46:15 +0100912
Patrick Delaunay61105032018-07-16 10:41:42 +0200913 refclk = pll_get_fref_ck(priv, pll_id);
Patrick Delaunaya6151912018-03-12 10:46:15 +0100914
Patrick Delaunay61105032018-07-16 10:41:42 +0200915 /* with FRACV :
916 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100917 * without FRACV
Patrick Delaunay61105032018-07-16 10:41:42 +0200918 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
Patrick Delaunaya6151912018-03-12 10:46:15 +0100919 */
920 if (fracr & RCC_PLLNFRACR_FRACLE) {
921 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
922 >> RCC_PLLNFRACR_FRACV_SHIFT;
Patrick Delaunay61105032018-07-16 10:41:42 +0200923 fvco = (ulong)lldiv((unsigned long long)refclk *
Patrick Delaunaya6151912018-03-12 10:46:15 +0100924 (((divn + 1) << 13) + fracv),
Patrick Delaunay61105032018-07-16 10:41:42 +0200925 ((unsigned long long)(divm + 1)) << 13);
Patrick Delaunaya6151912018-03-12 10:46:15 +0100926 } else {
Patrick Delaunay61105032018-07-16 10:41:42 +0200927 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
Patrick Delaunaya6151912018-03-12 10:46:15 +0100928 }
Patrick Delaunay61105032018-07-16 10:41:42 +0200929
930 return fvco;
931}
932
933static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
934 int pll_id, int div_id)
935{
936 const struct stm32mp1_clk_pll *pll = priv->data->pll;
937 int divy;
938 ulong dfout;
939 u32 cfgr2;
940
Patrick Delaunay61105032018-07-16 10:41:42 +0200941 if (div_id >= _DIV_NB)
942 return 0;
943
944 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
945 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
946
Patrick Delaunay61105032018-07-16 10:41:42 +0200947 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
Patrick Delaunaya6151912018-03-12 10:46:15 +0100948
949 return dfout;
950}
951
952static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
953{
954 u32 reg;
955 ulong clock = 0;
956
957 switch (p) {
958 case _CK_MPU:
959 /* MPU sub system */
960 reg = readl(priv->base + RCC_MPCKSELR);
961 switch (reg & RCC_SELR_SRC_MASK) {
962 case RCC_MPCKSELR_HSI:
963 clock = stm32mp1_clk_get_fixed(priv, _HSI);
964 break;
965 case RCC_MPCKSELR_HSE:
966 clock = stm32mp1_clk_get_fixed(priv, _HSE);
967 break;
968 case RCC_MPCKSELR_PLL:
969 case RCC_MPCKSELR_PLL_MPUDIV:
970 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
Lionel Debieve36911fc2020-04-24 15:47:57 +0200971 if ((reg & RCC_SELR_SRC_MASK) ==
972 RCC_MPCKSELR_PLL_MPUDIV) {
Patrick Delaunaya6151912018-03-12 10:46:15 +0100973 reg = readl(priv->base + RCC_MPCKDIVR);
Lionel Debieve36911fc2020-04-24 15:47:57 +0200974 clock >>= stm32mp1_mpu_div[reg &
975 RCC_MPUDIV_MASK];
Patrick Delaunaya6151912018-03-12 10:46:15 +0100976 }
977 break;
978 }
979 break;
980 /* AXI sub system */
981 case _ACLK:
982 case _HCLK2:
983 case _HCLK6:
984 case _PCLK4:
985 case _PCLK5:
986 reg = readl(priv->base + RCC_ASSCKSELR);
987 switch (reg & RCC_SELR_SRC_MASK) {
988 case RCC_ASSCKSELR_HSI:
989 clock = stm32mp1_clk_get_fixed(priv, _HSI);
990 break;
991 case RCC_ASSCKSELR_HSE:
992 clock = stm32mp1_clk_get_fixed(priv, _HSE);
993 break;
994 case RCC_ASSCKSELR_PLL:
995 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
996 break;
997 }
998
999 /* System clock divider */
1000 reg = readl(priv->base + RCC_AXIDIVR);
1001 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1002
1003 switch (p) {
1004 case _PCLK4:
1005 reg = readl(priv->base + RCC_APB4DIVR);
1006 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1007 break;
1008 case _PCLK5:
1009 reg = readl(priv->base + RCC_APB5DIVR);
1010 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1011 break;
1012 default:
1013 break;
1014 }
1015 break;
1016 /* MCU sub system */
1017 case _CK_MCU:
1018 case _PCLK1:
1019 case _PCLK2:
1020 case _PCLK3:
1021 reg = readl(priv->base + RCC_MSSCKSELR);
1022 switch (reg & RCC_SELR_SRC_MASK) {
1023 case RCC_MSSCKSELR_HSI:
1024 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1025 break;
1026 case RCC_MSSCKSELR_HSE:
1027 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1028 break;
1029 case RCC_MSSCKSELR_CSI:
1030 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1031 break;
1032 case RCC_MSSCKSELR_PLL:
1033 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1034 break;
1035 }
1036
1037 /* MCU clock divider */
1038 reg = readl(priv->base + RCC_MCUDIVR);
1039 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1040
1041 switch (p) {
1042 case _PCLK1:
1043 reg = readl(priv->base + RCC_APB1DIVR);
1044 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1045 break;
1046 case _PCLK2:
1047 reg = readl(priv->base + RCC_APB2DIVR);
1048 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1049 break;
1050 case _PCLK3:
1051 reg = readl(priv->base + RCC_APB3DIVR);
1052 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1053 break;
1054 case _CK_MCU:
1055 default:
1056 break;
1057 }
1058 break;
1059 case _CK_PER:
1060 reg = readl(priv->base + RCC_CPERCKSELR);
1061 switch (reg & RCC_SELR_SRC_MASK) {
1062 case RCC_CPERCKSELR_HSI:
1063 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1064 break;
1065 case RCC_CPERCKSELR_HSE:
1066 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1067 break;
1068 case RCC_CPERCKSELR_CSI:
1069 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1070 break;
1071 }
1072 break;
1073 case _HSI:
1074 case _HSI_KER:
1075 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1076 break;
1077 case _CSI:
1078 case _CSI_KER:
1079 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1080 break;
1081 case _HSE:
1082 case _HSE_KER:
1083 case _HSE_KER_DIV2:
1084 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1085 if (p == _HSE_KER_DIV2)
1086 clock >>= 1;
1087 break;
1088 case _LSI:
1089 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1090 break;
1091 case _LSE:
1092 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1093 break;
1094 /* PLL */
1095 case _PLL1_P:
1096 case _PLL1_Q:
1097 case _PLL1_R:
1098 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1099 break;
1100 case _PLL2_P:
1101 case _PLL2_Q:
1102 case _PLL2_R:
1103 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1104 break;
1105 case _PLL3_P:
1106 case _PLL3_Q:
1107 case _PLL3_R:
1108 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1109 break;
1110 case _PLL4_P:
1111 case _PLL4_Q:
1112 case _PLL4_R:
1113 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1114 break;
1115 /* other */
1116 case _USB_PHY_48:
Patrick Delaunay86617dd2019-01-30 13:07:00 +01001117 clock = 48000000;
Patrick Delaunaya6151912018-03-12 10:46:15 +01001118 break;
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02001119 case _DSI_PHY:
1120 {
1121 struct clk clk;
1122 struct udevice *dev = NULL;
Patrick Delaunaya6151912018-03-12 10:46:15 +01001123
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02001124 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1125 &dev)) {
1126 if (clk_request(dev, &clk)) {
1127 pr_err("ck_dsi_phy request");
1128 } else {
1129 clk.id = 0;
1130 clock = clk_get_rate(&clk);
1131 }
1132 }
1133 break;
1134 }
Patrick Delaunaya6151912018-03-12 10:46:15 +01001135 default:
1136 break;
1137 }
1138
1139 debug("%s(%d) clock = %lx : %ld kHz\n",
1140 __func__, p, clock, clock / 1000);
1141
1142 return clock;
1143}
1144
1145static int stm32mp1_clk_enable(struct clk *clk)
1146{
1147 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1148 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1149 int i = stm32mp1_clk_get_id(priv, clk->id);
1150
1151 if (i < 0)
1152 return i;
1153
1154 if (gate[i].set_clr)
1155 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1156 else
1157 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1158
1159 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1160
1161 return 0;
1162}
1163
1164static int stm32mp1_clk_disable(struct clk *clk)
1165{
1166 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1167 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1168 int i = stm32mp1_clk_get_id(priv, clk->id);
1169
1170 if (i < 0)
1171 return i;
1172
1173 if (gate[i].set_clr)
1174 writel(BIT(gate[i].bit),
1175 priv->base + gate[i].offset
1176 + RCC_MP_ENCLRR_OFFSET);
1177 else
1178 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1179
1180 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1181
1182 return 0;
1183}
1184
1185static ulong stm32mp1_clk_get_rate(struct clk *clk)
1186{
1187 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1188 int p = stm32mp1_clk_get_parent(priv, clk->id);
1189 ulong rate;
1190
1191 if (p < 0)
1192 return 0;
1193
1194 rate = stm32mp1_clk_get(priv, p);
1195
1196#ifdef DEBUG
1197 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1198 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1199#endif
1200 return rate;
1201}
1202
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001203#ifdef STM32MP1_CLOCK_TREE_INIT
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001204
1205bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
1206{
1207 unsigned int id;
1208
1209 switch (opp_id) {
1210 case 1:
1211 case 2:
1212 id = opp_id;
1213 break;
1214 default:
1215 id = 1; /* default value */
1216 break;
1217 }
1218
1219 switch (cpu_type) {
1220 case CPU_STM32MP157Fxx:
1221 case CPU_STM32MP157Dxx:
1222 case CPU_STM32MP153Fxx:
1223 case CPU_STM32MP153Dxx:
1224 case CPU_STM32MP151Fxx:
1225 case CPU_STM32MP151Dxx:
1226 return true;
1227 default:
1228 return id == 1;
1229 }
1230}
1231
Patrick Delaunay4e626422020-05-25 12:19:45 +02001232__weak void board_vddcore_init(u32 voltage_mv)
1233{
1234}
1235
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001236/*
1237 * gets OPP parameters (frequency in KHz and voltage in mV) from
1238 * an OPP table subnode. Platform HW support capabilities are also checked.
1239 * Returns 0 on success and a negative FDT error code on failure.
1240 */
1241static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
1242 u32 *freq_khz, u32 *voltage_mv)
1243{
1244 u32 opp_hw;
1245 u64 read_freq_64;
1246 u32 read_voltage_32;
1247
1248 *freq_khz = 0;
1249 *voltage_mv = 0;
1250
1251 opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
1252 if (opp_hw)
1253 if (!stm32mp1_supports_opp(opp_hw, cpu_type))
1254 return -FDT_ERR_BADVALUE;
1255
1256 read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
1257 1000ULL;
1258 read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
1259 1000U;
1260
1261 if (!read_voltage_32 || !read_freq_64)
1262 return -FDT_ERR_NOTFOUND;
1263
1264 /* Frequency value expressed in KHz must fit on 32 bits */
1265 if (read_freq_64 > U32_MAX)
1266 return -FDT_ERR_BADVALUE;
1267
1268 /* Millivolt value must fit on 16 bits */
1269 if (read_voltage_32 > U16_MAX)
1270 return -FDT_ERR_BADVALUE;
1271
1272 *freq_khz = (u32)read_freq_64;
1273 *voltage_mv = read_voltage_32;
1274
1275 return 0;
1276}
1277
1278/*
1279 * parses OPP table in DT and finds the parameters for the
1280 * highest frequency supported by the HW platform.
1281 * Returns 0 on success and a negative FDT error code on failure.
1282 */
1283int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
1284{
1285 ofnode node, subnode;
1286 int ret;
1287 u32 freq = 0U, voltage = 0U;
1288 u32 cpu_type = get_cpu_type();
1289
1290 node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
1291 if (!ofnode_valid(node))
1292 return -FDT_ERR_NOTFOUND;
1293
1294 ofnode_for_each_subnode(subnode, node) {
1295 unsigned int read_freq;
1296 unsigned int read_voltage;
1297
1298 ret = stm32mp1_get_opp(cpu_type, subnode,
1299 &read_freq, &read_voltage);
1300 if (ret)
1301 continue;
1302
1303 if (read_freq > freq) {
1304 freq = read_freq;
1305 voltage = read_voltage;
1306 }
1307 }
1308
1309 if (!freq || !voltage)
1310 return -FDT_ERR_NOTFOUND;
1311
1312 *freq_hz = (u64)1000U * freq;
Patrick Delaunay4e626422020-05-25 12:19:45 +02001313 board_vddcore_init(voltage);
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001314
1315 return 0;
1316}
1317
1318static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
1319 u32 *pllcfg, u32 *fracv)
1320{
1321 u32 post_divm;
1322 u32 input_freq;
1323 u64 output_freq;
1324 u64 freq;
1325 u64 vco;
1326 u32 divm, divn, divp, frac;
1327 int i, ret;
1328 u32 diff;
1329 u32 best_diff = U32_MAX;
1330
1331 /* PLL1 is 1600 */
1332 const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
1333 const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
1334 const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
1335
1336 ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
1337 if (ret) {
1338 debug("PLL1 OPP configuration not found (%d).\n", ret);
1339 return ret;
1340 }
1341
1342 switch (clksrc) {
1343 case CLK_PLL12_HSI:
1344 input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
1345 break;
1346 case CLK_PLL12_HSE:
1347 input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
1348 break;
1349 default:
1350 return -EINTR;
1351 }
1352
1353 /* Following parameters have always the same value */
1354 pllcfg[PLLCFG_Q] = 0;
1355 pllcfg[PLLCFG_R] = 0;
1356 pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1357
1358 for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
1359 post_divm = (u32)(input_freq / (divm + 1));
1360 if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
1361 continue;
1362
1363 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1364 freq = output_freq * (divm + 1) * (divp + 1);
1365 divn = (u32)((freq / input_freq) - 1);
1366 if (divn < DIVN_MIN || divn > DIVN_MAX)
1367 continue;
1368
1369 frac = (u32)(((freq * FRAC_MAX) / input_freq) -
1370 ((divn + 1) * FRAC_MAX));
1371 /* 2 loops to refine the fractional part */
1372 for (i = 2; i != 0; i--) {
1373 if (frac > FRAC_MAX)
1374 break;
1375
1376 vco = (post_divm * (divn + 1)) +
1377 ((post_divm * (u64)frac) /
1378 FRAC_MAX);
1379 if (vco < (PLL1600_VCO_MIN / 2) ||
1380 vco > (PLL1600_VCO_MAX / 2)) {
1381 frac++;
1382 continue;
1383 }
1384 freq = vco / (divp + 1);
1385 if (output_freq < freq)
1386 diff = (u32)(freq - output_freq);
1387 else
1388 diff = (u32)(output_freq - freq);
1389 if (diff < best_diff) {
1390 pllcfg[PLLCFG_M] = divm;
1391 pllcfg[PLLCFG_N] = divn;
1392 pllcfg[PLLCFG_P] = divp;
1393 *fracv = frac;
1394
1395 if (diff == 0)
1396 return 0;
1397
1398 best_diff = diff;
1399 }
1400 frac++;
1401 }
1402 }
1403 }
1404
1405 if (best_diff == U32_MAX)
1406 return -1;
1407
1408 return 0;
1409}
1410
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001411static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1412 u32 mask_on)
1413{
1414 u32 address = rcc + offset;
1415
1416 if (enable)
1417 setbits_le32(address, mask_on);
1418 else
1419 clrbits_le32(address, mask_on);
1420}
1421
1422static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1423{
Patrick Delaunay63201282019-01-30 13:07:02 +01001424 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001425}
1426
1427static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1428 u32 mask_rdy)
1429{
1430 u32 mask_test = 0;
1431 u32 address = rcc + offset;
1432 u32 val;
1433 int ret;
1434
1435 if (enable)
1436 mask_test = mask_rdy;
1437
1438 ret = readl_poll_timeout(address, val,
1439 (val & mask_rdy) == mask_test,
1440 TIMEOUT_1S);
1441
1442 if (ret)
1443 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1444 mask_rdy, address, enable, readl(address));
1445
1446 return ret;
1447}
1448
Patrick Delaunayd2194152018-07-16 10:41:46 +02001449static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
Patrick Delaunayeb49dce2020-01-28 10:44:15 +01001450 u32 lsedrv)
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001451{
1452 u32 value;
1453
Patrick Delaunayd2194152018-07-16 10:41:46 +02001454 if (digbyp)
1455 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1456
1457 if (bypass || digbyp)
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001458 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1459
1460 /*
1461 * warning: not recommended to switch directly from "high drive"
1462 * to "medium low drive", and vice-versa.
1463 */
1464 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1465 >> RCC_BDCR_LSEDRV_SHIFT;
1466
1467 while (value != lsedrv) {
1468 if (value > lsedrv)
1469 value--;
1470 else
1471 value++;
1472
1473 clrsetbits_le32(rcc + RCC_BDCR,
1474 RCC_BDCR_LSEDRV_MASK,
1475 value << RCC_BDCR_LSEDRV_SHIFT);
1476 }
1477
1478 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1479}
1480
1481static void stm32mp1_lse_wait(fdt_addr_t rcc)
1482{
1483 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1484}
1485
1486static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1487{
1488 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1489 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1490}
1491
Patrick Delaunayd2194152018-07-16 10:41:46 +02001492static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001493{
Patrick Delaunayd2194152018-07-16 10:41:46 +02001494 if (digbyp)
Patrick Delaunay63201282019-01-30 13:07:02 +01001495 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
Patrick Delaunayd2194152018-07-16 10:41:46 +02001496 if (bypass || digbyp)
Patrick Delaunay63201282019-01-30 13:07:02 +01001497 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001498
1499 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1500 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1501
1502 if (css)
Patrick Delaunay63201282019-01-30 13:07:02 +01001503 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001504}
1505
1506static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1507{
Patrick Delaunay63201282019-01-30 13:07:02 +01001508 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001509 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1510}
1511
1512static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1513{
1514 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1515 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1516}
1517
1518static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1519{
1520 u32 address = rcc + RCC_OCRDYR;
1521 u32 val;
1522 int ret;
1523
1524 clrsetbits_le32(rcc + RCC_HSICFGR,
1525 RCC_HSICFGR_HSIDIV_MASK,
1526 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1527
1528 ret = readl_poll_timeout(address, val,
1529 val & RCC_OCRDYR_HSIDIVRDY,
1530 TIMEOUT_200MS);
1531 if (ret)
1532 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1533 address, readl(address));
1534
1535 return ret;
1536}
1537
1538static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1539{
1540 u8 hsidiv;
1541 u32 hsidivfreq = MAX_HSI_HZ;
1542
1543 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1544 hsidivfreq = hsidivfreq / 2)
1545 if (hsidivfreq == hsifreq)
1546 break;
1547
1548 if (hsidiv == 4) {
1549 pr_err("clk-hsi frequency invalid");
1550 return -1;
1551 }
1552
1553 if (hsidiv > 0)
1554 return stm32mp1_set_hsidiv(rcc, hsidiv);
1555
1556 return 0;
1557}
1558
1559static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1560{
1561 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1562
Patrick Delaunaybbd108a2019-01-30 13:07:06 +01001563 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1564 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1565 RCC_PLLNCR_DIVREN,
1566 RCC_PLLNCR_PLLON);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001567}
1568
1569static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1570{
1571 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1572 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1573 u32 val;
1574 int ret;
1575
1576 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1577 TIMEOUT_200MS);
1578
1579 if (ret) {
1580 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1581 pll_id, pllxcr, readl(pllxcr));
1582 return ret;
1583 }
1584
1585 /* start the requested output */
1586 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1587
1588 return 0;
1589}
1590
1591static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1592{
1593 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1594 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1595 u32 val;
1596
1597 /* stop all output */
1598 clrbits_le32(pllxcr,
1599 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1600
1601 /* stop PLL */
1602 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1603
1604 /* wait PLL stopped */
1605 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1606 TIMEOUT_200MS);
1607}
1608
1609static void pll_config_output(struct stm32mp1_clk_priv *priv,
1610 int pll_id, u32 *pllcfg)
1611{
1612 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1613 fdt_addr_t rcc = priv->base;
1614 u32 value;
1615
1616 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1617 & RCC_PLLNCFGR2_DIVP_MASK;
1618 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1619 & RCC_PLLNCFGR2_DIVQ_MASK;
1620 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1621 & RCC_PLLNCFGR2_DIVR_MASK;
1622 writel(value, rcc + pll[pll_id].pllxcfgr2);
1623}
1624
1625static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1626 u32 *pllcfg, u32 fracv)
1627{
1628 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1629 fdt_addr_t rcc = priv->base;
1630 enum stm32mp1_plltype type = pll[pll_id].plltype;
1631 int src;
1632 ulong refclk;
1633 u8 ifrge = 0;
1634 u32 value;
1635
1636 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1637
1638 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1639 (pllcfg[PLLCFG_M] + 1);
1640
1641 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1642 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1643 debug("invalid refclk = %x\n", (u32)refclk);
1644 return -EINVAL;
1645 }
1646 if (type == PLL_800 && refclk >= 8000000)
1647 ifrge = 1;
1648
1649 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1650 & RCC_PLLNCFGR1_DIVN_MASK;
1651 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1652 & RCC_PLLNCFGR1_DIVM_MASK;
1653 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1654 & RCC_PLLNCFGR1_IFRGE_MASK;
1655 writel(value, rcc + pll[pll_id].pllxcfgr1);
1656
1657 /* fractional configuration: load sigma-delta modulator (SDM) */
1658
1659 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1660 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1661 rcc + pll[pll_id].pllxfracr);
1662
1663 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1664 setbits_le32(rcc + pll[pll_id].pllxfracr,
1665 RCC_PLLNFRACR_FRACLE);
1666
1667 pll_config_output(priv, pll_id, pllcfg);
1668
1669 return 0;
1670}
1671
1672static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1673{
1674 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1675 u32 pllxcsg;
1676
1677 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1678 RCC_PLLNCSGR_MOD_PER_MASK) |
1679 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1680 RCC_PLLNCSGR_INC_STEP_MASK) |
1681 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1682 RCC_PLLNCSGR_SSCG_MODE_MASK);
1683
1684 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
Patrick Delaunaybbd108a2019-01-30 13:07:06 +01001685
1686 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001687}
1688
Patrick Delaunayc3e828b2019-04-18 17:32:48 +02001689static __maybe_unused int pll_set_rate(struct udevice *dev,
1690 int pll_id,
1691 int div_id,
1692 unsigned long clk_rate)
1693{
1694 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1695 unsigned int pllcfg[PLLCFG_NB];
1696 ofnode plloff;
1697 char name[12];
1698 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1699 enum stm32mp1_plltype type = pll[pll_id].plltype;
1700 int divm, divn, divy;
1701 int ret;
1702 ulong fck_ref;
1703 u32 fracv;
1704 u64 value;
1705
1706 if (div_id > _DIV_NB)
1707 return -EINVAL;
1708
1709 sprintf(name, "st,pll@%d", pll_id);
1710 plloff = dev_read_subnode(dev, name);
1711 if (!ofnode_valid(plloff))
1712 return -FDT_ERR_NOTFOUND;
1713
1714 ret = ofnode_read_u32_array(plloff, "cfg",
1715 pllcfg, PLLCFG_NB);
1716 if (ret < 0)
1717 return -FDT_ERR_NOTFOUND;
1718
1719 fck_ref = pll_get_fref_ck(priv, pll_id);
1720
1721 divm = pllcfg[PLLCFG_M];
1722 /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1723 divy = pllcfg[PLLCFG_P + div_id];
1724
1725 /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1726 * So same final result than PLL2 et 4
1727 * with FRACV
1728 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1729 * / (DIVy + 1) * (DIVM + 1)
1730 * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1731 * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1732 */
1733 value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1734 value = lldiv(value, fck_ref);
1735
1736 divn = (value >> 13) - 1;
1737 if (divn < DIVN_MIN ||
1738 divn > stm32mp1_pll[type].divn_max) {
1739 pr_err("divn invalid = %d", divn);
1740 return -EINVAL;
1741 }
1742 fracv = value - ((divn + 1) << 13);
1743 pllcfg[PLLCFG_N] = divn;
1744
1745 /* reconfigure PLL */
1746 pll_stop(priv, pll_id);
1747 pll_config(priv, pll_id, pllcfg, fracv);
1748 pll_start(priv, pll_id);
1749 pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1750
1751 return 0;
1752}
1753
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001754static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1755{
1756 u32 address = priv->base + (clksrc >> 4);
1757 u32 val;
1758 int ret;
1759
1760 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1761 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1762 TIMEOUT_200MS);
1763 if (ret)
1764 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1765 clksrc, address, readl(address));
1766
1767 return ret;
1768}
1769
Patrick Delaunay938e0e32018-03-20 11:41:25 +01001770static void stgen_config(struct stm32mp1_clk_priv *priv)
1771{
1772 int p;
1773 u32 stgenc, cntfid0;
1774 ulong rate;
1775
Patrick Delaunaydfda7d42019-07-05 17:20:11 +02001776 stgenc = STM32_STGEN_BASE;
Patrick Delaunay938e0e32018-03-20 11:41:25 +01001777 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1778 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1779 rate = stm32mp1_clk_get(priv, p);
1780
1781 if (cntfid0 != rate) {
Patrick Delaunayf3a23c22019-01-30 13:07:03 +01001782 u64 counter;
1783
Patrick Delaunay938e0e32018-03-20 11:41:25 +01001784 pr_debug("System Generic Counter (STGEN) update\n");
1785 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
Patrick Delaunayf3a23c22019-01-30 13:07:03 +01001786 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1787 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1788 counter = lldiv(counter * (u64)rate, cntfid0);
1789 writel((u32)counter, stgenc + STGENC_CNTCVL);
1790 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
Patrick Delaunay938e0e32018-03-20 11:41:25 +01001791 writel(rate, stgenc + STGENC_CNTFID0);
1792 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1793
1794 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1795
1796 /* need to update gd->arch.timer_rate_hz with new frequency */
1797 timer_init();
Patrick Delaunay938e0e32018-03-20 11:41:25 +01001798 }
1799}
1800
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001801static int set_clkdiv(unsigned int clkdiv, u32 address)
1802{
1803 u32 val;
1804 int ret;
1805
1806 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1807 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1808 TIMEOUT_200MS);
1809 if (ret)
1810 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1811 clkdiv, address, readl(address));
1812
1813 return ret;
1814}
1815
1816static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1817 u32 clksrc, u32 clkdiv)
1818{
1819 u32 address = priv->base + (clksrc >> 4);
1820
1821 /*
1822 * binding clksrc : bit15-4 offset
1823 * bit3: disable
1824 * bit2-0: MCOSEL[2:0]
1825 */
1826 if (clksrc & 0x8) {
1827 clrbits_le32(address, RCC_MCOCFG_MCOON);
1828 } else {
1829 clrsetbits_le32(address,
1830 RCC_MCOCFG_MCOSRC_MASK,
1831 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1832 clrsetbits_le32(address,
1833 RCC_MCOCFG_MCODIV_MASK,
1834 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1835 setbits_le32(address, RCC_MCOCFG_MCOON);
1836 }
1837}
1838
1839static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1840 unsigned int clksrc,
1841 int lse_css)
1842{
1843 u32 address = priv->base + RCC_BDCR;
1844
1845 if (readl(address) & RCC_BDCR_RTCCKEN)
1846 goto skip_rtc;
1847
1848 if (clksrc == CLK_RTC_DISABLED)
1849 goto skip_rtc;
1850
1851 clrsetbits_le32(address,
1852 RCC_BDCR_RTCSRC_MASK,
1853 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1854
1855 setbits_le32(address, RCC_BDCR_RTCCKEN);
1856
1857skip_rtc:
1858 if (lse_css)
1859 setbits_le32(address, RCC_BDCR_LSECSSON);
1860}
1861
1862static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1863{
1864 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1865 u32 value = pkcs & 0xF;
1866 u32 mask = 0xF;
1867
1868 if (pkcs & BIT(31)) {
1869 mask <<= 4;
1870 value <<= 4;
1871 }
1872 clrsetbits_le32(address, mask, value);
1873}
1874
1875static int stm32mp1_clktree(struct udevice *dev)
1876{
1877 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1878 fdt_addr_t rcc = priv->base;
1879 unsigned int clksrc[CLKSRC_NB];
1880 unsigned int clkdiv[CLKDIV_NB];
1881 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001882 unsigned int pllfracv[_PLL_NB];
1883 unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
1884 bool pllcfg_valid[_PLL_NB];
1885 bool pllcsg_set[_PLL_NB];
1886 int ret;
1887 int i, len;
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001888 int lse_css = 0;
1889 const u32 *pkcs_cell;
1890
1891 /* check mandatory field */
1892 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1893 if (ret < 0) {
1894 debug("field st,clksrc invalid: error %d\n", ret);
1895 return -FDT_ERR_NOTFOUND;
1896 }
1897
1898 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1899 if (ret < 0) {
1900 debug("field st,clkdiv invalid: error %d\n", ret);
1901 return -FDT_ERR_NOTFOUND;
1902 }
1903
1904 /* check mandatory field in each pll */
1905 for (i = 0; i < _PLL_NB; i++) {
1906 char name[12];
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001907 ofnode node;
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001908
1909 sprintf(name, "st,pll@%d", i);
Patrick Delaunay37ad8372020-05-25 12:19:44 +02001910 node = dev_read_subnode(dev, name);
1911 pllcfg_valid[i] = ofnode_valid(node);
1912 pllcsg_set[i] = false;
1913 if (pllcfg_valid[i]) {
1914 debug("DT for PLL %d @ %s\n", i, name);
1915 ret = ofnode_read_u32_array(node, "cfg",
1916 pllcfg[i], PLLCFG_NB);
1917 if (ret < 0) {
1918 debug("field cfg invalid: error %d\n", ret);
1919 return -FDT_ERR_NOTFOUND;
1920 }
1921 pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
1922
1923 ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
1924 PLLCSG_NB);
1925 if (!ret) {
1926 pllcsg_set[i] = true;
1927 } else if (ret != -FDT_ERR_NOTFOUND) {
1928 debug("invalid csg node for pll@%d res=%d\n",
1929 i, ret);
1930 return ret;
1931 }
1932 } else if (i == _PLL1) {
1933 /* use OPP for PLL1 for A7 CPU */
1934 debug("DT for PLL %d with OPP\n", i);
1935 ret = stm32mp1_pll1_opp(priv,
1936 clksrc[CLKSRC_PLL12],
1937 pllcfg[i],
1938 &pllfracv[i]);
1939 if (ret) {
1940 debug("PLL %d with OPP error = %d\n", i, ret);
1941 return ret;
1942 }
1943 pllcfg_valid[i] = true;
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001944 }
1945 }
1946
1947 debug("configuration MCO\n");
1948 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1949 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1950
1951 debug("switch ON osillator\n");
1952 /*
1953 * switch ON oscillator found in device-tree,
1954 * HSI already ON after bootrom
1955 */
1956 if (priv->osc[_LSI])
1957 stm32mp1_lsi_set(rcc, 1);
1958
1959 if (priv->osc[_LSE]) {
Patrick Delaunayeb49dce2020-01-28 10:44:15 +01001960 int bypass, digbyp;
1961 u32 lsedrv;
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001962 struct udevice *dev = priv->osc_dev[_LSE];
1963
1964 bypass = dev_read_bool(dev, "st,bypass");
Patrick Delaunayd2194152018-07-16 10:41:46 +02001965 digbyp = dev_read_bool(dev, "st,digbypass");
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001966 lse_css = dev_read_bool(dev, "st,css");
1967 lsedrv = dev_read_u32_default(dev, "st,drive",
1968 LSEDRV_MEDIUM_HIGH);
1969
Patrick Delaunayd2194152018-07-16 10:41:46 +02001970 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001971 }
1972
1973 if (priv->osc[_HSE]) {
Patrick Delaunayd2194152018-07-16 10:41:46 +02001974 int bypass, digbyp, css;
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001975 struct udevice *dev = priv->osc_dev[_HSE];
1976
1977 bypass = dev_read_bool(dev, "st,bypass");
Patrick Delaunayd2194152018-07-16 10:41:46 +02001978 digbyp = dev_read_bool(dev, "st,digbypass");
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001979 css = dev_read_bool(dev, "st,css");
1980
Patrick Delaunayd2194152018-07-16 10:41:46 +02001981 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01001982 }
1983 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1984 * => switch on CSI even if node is not present in device tree
1985 */
1986 stm32mp1_csi_set(rcc, 1);
1987
1988 /* come back to HSI */
1989 debug("come back to HSI\n");
1990 set_clksrc(priv, CLK_MPU_HSI);
1991 set_clksrc(priv, CLK_AXI_HSI);
1992 set_clksrc(priv, CLK_MCU_HSI);
1993
1994 debug("pll stop\n");
1995 for (i = 0; i < _PLL_NB; i++)
1996 pll_stop(priv, i);
1997
1998 /* configure HSIDIV */
1999 debug("configure HSIDIV\n");
Patrick Delaunay938e0e32018-03-20 11:41:25 +01002000 if (priv->osc[_HSI]) {
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002001 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
Patrick Delaunay938e0e32018-03-20 11:41:25 +01002002 stgen_config(priv);
2003 }
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002004
2005 /* select DIV */
2006 debug("select DIV\n");
2007 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
2008 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
2009 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
2010 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
2011 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
2012 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
2013 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
2014 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
2015 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
2016
2017 /* no ready bit for RTC */
2018 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
2019
2020 /* configure PLLs source */
2021 debug("configure PLLs source\n");
2022 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
2023 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
2024 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
2025
2026 /* configure and start PLLs */
2027 debug("configure PLLs\n");
2028 for (i = 0; i < _PLL_NB; i++) {
Patrick Delaunay37ad8372020-05-25 12:19:44 +02002029 if (!pllcfg_valid[i])
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002030 continue;
Patrick Delaunay37ad8372020-05-25 12:19:44 +02002031 debug("configure PLL %d\n", i);
2032 pll_config(priv, i, pllcfg[i], pllfracv[i]);
2033 if (pllcsg_set[i])
2034 pll_csg(priv, i, pllcsg[i]);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002035 pll_start(priv, i);
2036 }
2037
2038 /* wait and start PLLs ouptut when ready */
2039 for (i = 0; i < _PLL_NB; i++) {
Patrick Delaunay37ad8372020-05-25 12:19:44 +02002040 if (!pllcfg_valid[i])
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002041 continue;
2042 debug("output PLL %d\n", i);
2043 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
2044 }
2045
2046 /* wait LSE ready before to use it */
2047 if (priv->osc[_LSE])
2048 stm32mp1_lse_wait(rcc);
2049
2050 /* configure with expected clock source */
2051 debug("CLKSRC\n");
2052 set_clksrc(priv, clksrc[CLKSRC_MPU]);
2053 set_clksrc(priv, clksrc[CLKSRC_AXI]);
2054 set_clksrc(priv, clksrc[CLKSRC_MCU]);
2055 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
2056
2057 /* configure PKCK */
2058 debug("PKCK\n");
2059 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
2060 if (pkcs_cell) {
2061 bool ckper_disabled = false;
2062
2063 for (i = 0; i < len / sizeof(u32); i++) {
2064 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
2065
2066 if (pkcs == CLK_CKPER_DISABLED) {
2067 ckper_disabled = true;
2068 continue;
2069 }
2070 pkcs_config(priv, pkcs);
2071 }
2072 /* CKPER is source for some peripheral clock
2073 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2074 * only if previous clock is still ON
2075 * => deactivated CKPER only after switching clock
2076 */
2077 if (ckper_disabled)
2078 pkcs_config(priv, CLK_CKPER_DISABLED);
2079 }
2080
Patrick Delaunay938e0e32018-03-20 11:41:25 +01002081 /* STGEN clock source can change with CLK_STGEN_XXX */
2082 stgen_config(priv);
2083
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002084 debug("oscillator off\n");
2085 /* switch OFF HSI if not found in device-tree */
2086 if (!priv->osc[_HSI])
2087 stm32mp1_hsi_set(rcc, 0);
2088
2089 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2090 clrsetbits_le32(priv->base + RCC_DDRITFCR,
2091 RCC_DDRITFCR_DDRCKMOD_MASK,
2092 RCC_DDRITFCR_DDRCKMOD_SSR <<
2093 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2094
2095 return 0;
2096}
2097#endif /* STM32MP1_CLOCK_TREE_INIT */
2098
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002099static int pll_set_output_rate(struct udevice *dev,
2100 int pll_id,
2101 int div_id,
2102 unsigned long clk_rate)
2103{
2104 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2105 const struct stm32mp1_clk_pll *pll = priv->data->pll;
2106 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
2107 int div;
2108 ulong fvco;
2109
2110 if (div_id > _DIV_NB)
2111 return -EINVAL;
2112
2113 fvco = pll_get_fvco(priv, pll_id);
2114
2115 if (fvco <= clk_rate)
2116 div = 1;
2117 else
2118 div = DIV_ROUND_UP(fvco, clk_rate);
2119
2120 if (div > 128)
2121 div = 128;
2122
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002123 /* stop the requested output */
2124 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2125 /* change divider */
2126 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
2127 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
2128 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
2129 /* start the requested output */
2130 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2131
2132 return 0;
2133}
2134
2135static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
2136{
2137 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
2138 int p;
2139
2140 switch (clk->id) {
Patrick Delaunayc3e828b2019-04-18 17:32:48 +02002141#if defined(STM32MP1_CLOCK_TREE_INIT) && \
2142 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2143 case DDRPHYC:
2144 break;
2145#endif
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002146 case LTDC_PX:
2147 case DSI_PX:
2148 break;
2149 default:
2150 pr_err("not supported");
2151 return -EINVAL;
2152 }
2153
2154 p = stm32mp1_clk_get_parent(priv, clk->id);
Patrick Delaunay7879a7d2019-07-30 19:16:54 +02002155#ifdef DEBUG
2156 debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
2157#endif
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002158 if (p < 0)
2159 return -EINVAL;
2160
2161 switch (p) {
Patrick Delaunayc3e828b2019-04-18 17:32:48 +02002162#if defined(STM32MP1_CLOCK_TREE_INIT) && \
2163 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2164 case _PLL2_R: /* DDRPHYC */
2165 {
2166 /* only for change DDR clock in interactive mode */
2167 ulong result;
2168
2169 set_clksrc(priv, CLK_AXI_HSI);
2170 result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
2171 set_clksrc(priv, CLK_AXI_PLL2P);
2172 return result;
2173 }
2174#endif
Patrick Delaunay7879a7d2019-07-30 19:16:54 +02002175
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002176 case _PLL4_Q:
2177 /* for LTDC_PX and DSI_PX case */
2178 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
2179 }
2180
2181 return -EINVAL;
2182}
2183
Patrick Delaunaya6151912018-03-12 10:46:15 +01002184static void stm32mp1_osc_clk_init(const char *name,
2185 struct stm32mp1_clk_priv *priv,
2186 int index)
2187{
2188 struct clk clk;
2189 struct udevice *dev = NULL;
2190
2191 priv->osc[index] = 0;
2192 clk.id = 0;
2193 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
2194 if (clk_request(dev, &clk))
2195 pr_err("%s request", name);
2196 else
2197 priv->osc[index] = clk_get_rate(&clk);
2198 }
2199 priv->osc_dev[index] = dev;
2200}
2201
2202static void stm32mp1_osc_init(struct udevice *dev)
2203{
2204 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2205 int i;
2206 const char *name[NB_OSC] = {
2207 [_LSI] = "clk-lsi",
2208 [_LSE] = "clk-lse",
2209 [_HSI] = "clk-hsi",
2210 [_HSE] = "clk-hse",
2211 [_CSI] = "clk-csi",
2212 [_I2S_CKIN] = "i2s_ckin",
Patrick Delaunay86617dd2019-01-30 13:07:00 +01002213 };
Patrick Delaunaya6151912018-03-12 10:46:15 +01002214
2215 for (i = 0; i < NB_OSC; i++) {
2216 stm32mp1_osc_clk_init(name[i], priv, i);
2217 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
2218 }
2219}
2220
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002221static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
2222{
2223 char buf[32];
2224 int i, s, p;
2225
2226 printf("Clocks:\n");
2227 for (i = 0; i < _PARENT_NB; i++) {
2228 printf("- %s : %s MHz\n",
2229 stm32mp1_clk_parent_name[i],
2230 strmhz(buf, stm32mp1_clk_get(priv, i)));
2231 }
2232 printf("Source Clocks:\n");
2233 for (i = 0; i < _PARENT_SEL_NB; i++) {
2234 p = (readl(priv->base + priv->data->sel[i].offset) >>
2235 priv->data->sel[i].src) & priv->data->sel[i].msk;
2236 if (p < priv->data->sel[i].nb_parent) {
2237 s = priv->data->sel[i].parent[p];
2238 printf("- %s(%d) => parent %s(%d)\n",
2239 stm32mp1_clk_parent_sel_name[i], i,
2240 stm32mp1_clk_parent_name[s], s);
2241 } else {
2242 printf("- %s(%d) => parent index %d is invalid\n",
2243 stm32mp1_clk_parent_sel_name[i], i, p);
2244 }
2245 }
2246}
2247
2248#ifdef CONFIG_CMD_CLK
2249int soc_clk_dump(void)
2250{
2251 struct udevice *dev;
2252 struct stm32mp1_clk_priv *priv;
2253 int ret;
2254
2255 ret = uclass_get_device_by_driver(UCLASS_CLK,
2256 DM_GET_DRIVER(stm32mp1_clock),
2257 &dev);
2258 if (ret)
2259 return ret;
2260
2261 priv = dev_get_priv(dev);
2262
2263 stm32mp1_clk_dump(priv);
2264
2265 return 0;
2266}
2267#endif
2268
Patrick Delaunaya6151912018-03-12 10:46:15 +01002269static int stm32mp1_clk_probe(struct udevice *dev)
2270{
2271 int result = 0;
2272 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2273
2274 priv->base = dev_read_addr(dev->parent);
2275 if (priv->base == FDT_ADDR_T_NONE)
2276 return -EINVAL;
2277
2278 priv->data = (void *)&stm32mp1_data;
2279
2280 if (!priv->data->gate || !priv->data->sel ||
2281 !priv->data->pll)
2282 return -EINVAL;
2283
2284 stm32mp1_osc_init(dev);
2285
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002286#ifdef STM32MP1_CLOCK_TREE_INIT
2287 /* clock tree init is done only one time, before relocation */
2288 if (!(gd->flags & GD_FLG_RELOC))
2289 result = stm32mp1_clktree(dev);
Patrick Delaunay37ad8372020-05-25 12:19:44 +02002290 if (result)
2291 printf("clock tree initialization failed (%d)\n", result);
Patrick Delaunay266fa4d2018-03-12 10:46:16 +01002292#endif
2293
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002294#ifndef CONFIG_SPL_BUILD
2295#if defined(DEBUG)
2296 /* display debug information for probe after relocation */
2297 if (gd->flags & GD_FLG_RELOC)
2298 stm32mp1_clk_dump(priv);
2299#endif
2300
Patrick Delaunay4de076e2019-07-30 19:16:55 +02002301 gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2302 gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2303 /* DDRPHYC father */
2304 gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002305#if defined(CONFIG_DISPLAY_CPUINFO)
2306 if (gd->flags & GD_FLG_RELOC) {
2307 char buf[32];
2308
2309 printf("Clocks:\n");
Patrick Delaunay4de076e2019-07-30 19:16:55 +02002310 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002311 printf("- MCU : %s MHz\n",
2312 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
Patrick Delaunay4de076e2019-07-30 19:16:55 +02002313 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002314 printf("- PER : %s MHz\n",
2315 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
Patrick Delaunay4de076e2019-07-30 19:16:55 +02002316 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
Patrick Delaunay8d6310a2019-01-30 13:07:04 +01002317 }
2318#endif /* CONFIG_DISPLAY_CPUINFO */
2319#endif
2320
Patrick Delaunaya6151912018-03-12 10:46:15 +01002321 return result;
2322}
2323
2324static const struct clk_ops stm32mp1_clk_ops = {
2325 .enable = stm32mp1_clk_enable,
2326 .disable = stm32mp1_clk_disable,
2327 .get_rate = stm32mp1_clk_get_rate,
Patrick Delaunay88fa34d2018-07-16 10:41:43 +02002328 .set_rate = stm32mp1_clk_set_rate,
Patrick Delaunaya6151912018-03-12 10:46:15 +01002329};
2330
Patrick Delaunaya6151912018-03-12 10:46:15 +01002331U_BOOT_DRIVER(stm32mp1_clock) = {
2332 .name = "stm32mp1_clk",
2333 .id = UCLASS_CLK,
Patrick Delaunaya6151912018-03-12 10:46:15 +01002334 .ops = &stm32mp1_clk_ops,
Simon Glass41575d82020-12-03 16:55:17 -07002335 .priv_auto = sizeof(struct stm32mp1_clk_priv),
Patrick Delaunaya6151912018-03-12 10:46:15 +01002336 .probe = stm32mp1_clk_probe,
2337};