Blame - board/ti/dra7xx/mux_data.h - platform/external/u-boot

blob: 2cc4be31b2a788b47bbf7ee1d854686f72f6cea0 [file] [log] [blame]

Lokesh Vutla	687054a	2013-02-12 21:29:08 +0000	[diff] [blame]	1	/*
				2	* (C) Copyright 2013
				3	* Texas Instruments Incorporated, <www.ti.com>
				4	*
				5	* Sricharan R <r.sricharan@ti.com>
				6	* Nishant Kamat <nskamat@ti.com>
				7	*
Wolfgang Denk	1a45966	2013-07-08 09:37:19 +0200	[diff] [blame]	8	* SPDX-License-Identifier: GPL-2.0+
Lokesh Vutla	687054a	2013-02-12 21:29:08 +0000	[diff] [blame]	9	*/
				10	#ifndef _MUX_DATA_DRA7XX_H_
				11	#define _MUX_DATA_DRA7XX_H_
				12
				13	#include <asm/arch/mux_dra7xx.h>
				14
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	15	const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	16	{GPMC_AD0, (M3 \| PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
				17	{GPMC_AD1, (M3 \| PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
				18	{GPMC_AD2, (M3 \| PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
				19	{GPMC_AD3, (M3 \| PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
				20	{GPMC_AD4, (M3 \| PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
				21	{GPMC_AD5, (M3 \| PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
				22	{GPMC_AD6, (M3 \| PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
				23	{GPMC_AD7, (M3 \| PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
				24	{GPMC_AD8, (M3 \| PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
				25	{GPMC_AD9, (M3 \| PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
				26	{GPMC_AD10, (M3 \| PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
				27	{GPMC_AD11, (M3 \| PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
				28	{GPMC_AD12, (M3 \| PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
				29	{GPMC_AD13, (M3 \| PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
				30	{GPMC_AD14, (M3 \| PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
				31	{GPMC_AD15, (M3 \| PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
				32	{GPMC_A0, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
				33	{GPMC_A1, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
				34	{GPMC_A2, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
				35	{GPMC_A3, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
				36	{GPMC_A4, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
				37	{GPMC_A5, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
				38	{GPMC_A6, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
				39	{GPMC_A7, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
				40	{GPMC_A8, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
				41	{GPMC_A9, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
				42	{GPMC_A10, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
				43	{GPMC_A11, (M14 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
				44	{GPMC_A13, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
				45	{GPMC_A14, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
				46	{GPMC_A15, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
				47	{GPMC_A16, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
				48	{GPMC_A17, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
				49	{GPMC_A18, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
				50	{GPMC_A19, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
				51	{GPMC_A20, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
				52	{GPMC_A21, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
				53	{GPMC_A22, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
				54	{GPMC_A23, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
				55	{GPMC_A24, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
				56	{GPMC_A25, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
				57	{GPMC_A26, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
				58	{GPMC_A27, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
				59	{GPMC_CS1, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
				60	{GPMC_CS2, (M1 \| PIN_INPUT_PULLUP \| MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
				61	{GPMC_CS3, (M3 \| PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
				62	{VIN2A_CLK0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
				63	{VIN2A_HSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
				64	{VIN2A_VSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
				65	{VIN2A_D0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
				66	{VIN2A_D1, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
				67	{VIN2A_D2, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
				68	{VIN2A_D3, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
				69	{VIN2A_D4, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
				70	{VIN2A_D5, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
				71	{VIN2A_D6, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
				72	{VIN2A_D7, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
				73	{VIN2A_D8, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
				74	{VIN2A_D9, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
				75	{VIN2A_D10, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
				76	{VIN2A_D11, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
				77	{VOUT1_CLK, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
				78	{VOUT1_DE, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
				79	{VOUT1_HSYNC, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
				80	{VOUT1_VSYNC, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
				81	{VOUT1_D0, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
				82	{VOUT1_D1, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
				83	{VOUT1_D2, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
				84	{VOUT1_D3, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
				85	{VOUT1_D4, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
				86	{VOUT1_D5, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
				87	{VOUT1_D6, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
				88	{VOUT1_D7, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
				89	{VOUT1_D8, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
				90	{VOUT1_D9, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
				91	{VOUT1_D10, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
				92	{VOUT1_D11, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
				93	{VOUT1_D12, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
				94	{VOUT1_D13, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
				95	{VOUT1_D14, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
				96	{VOUT1_D15, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
				97	{VOUT1_D16, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
				98	{VOUT1_D17, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
				99	{VOUT1_D18, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
				100	{VOUT1_D19, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
				101	{VOUT1_D20, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
				102	{VOUT1_D21, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
				103	{VOUT1_D22, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
				104	{VOUT1_D23, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
				105	{MDIO_MCLK, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
				106	{MDIO_D, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_d.mdio_d */
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	107	{USB1_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
				108	{USB2_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
				109	{GPIO6_14, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
				110	{GPIO6_15, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
				111	{GPIO6_16, (M14 \| PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	112	{MCASP1_AXR0, (M10 \| PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
				113	{MCASP1_AXR1, (M10 \| PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
				114	{MCASP1_AXR2, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
				115	{MCASP1_AXR3, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
				116	{MCASP1_AXR4, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
				117	{MCASP1_AXR5, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
				118	{MCASP1_AXR6, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
				119	{MCASP1_AXR7, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
				120	{MCASP1_AXR12, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
				121	{MCASP1_AXR13, (M1 \| PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
				122	{MCASP1_AXR14, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
				123	{MCASP1_AXR15, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
				124	{MCASP2_ACLKR, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
				125	{MCASP3_ACLKX, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
				126	{MCASP3_FSX, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
				127	{MCASP3_AXR0, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
				128	{MCASP3_AXR1, (M0 \| PIN_INPUT_SLEW \| VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
				129	{MMC1_CLK, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
				130	{MMC1_CMD, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
				131	{MMC1_DAT0, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
				132	{MMC1_DAT1, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
				133	{MMC1_DAT2, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
				134	{MMC1_DAT3, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
				135	{MMC1_SDCD, (M14 \| PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
				136	{MMC1_SDWP, (M14 \| PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	137	{SPI1_SCLK, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
				138	{SPI1_D1, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
				139	{SPI1_D0, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
				140	{SPI1_CS0, (M0 \| PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
				141	{SPI1_CS1, (M14 \| PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
				142	{SPI1_CS2, (M14 \| PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
				143	{SPI1_CS3, (M6 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
				144	{SPI2_SCLK, (M1 \| PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
				145	{SPI2_D1, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
				146	{SPI2_D0, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
				147	{SPI2_CS0, (M1 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
				148	{DCAN1_TX, (M15 \| PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
				149	{DCAN1_RX, (M14 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
				150	{UART1_RXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
				151	{UART1_TXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_txd.uart1_txd */
				152	{UART1_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
				153	{UART1_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
				154	{UART2_RXD, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
				155	{UART2_TXD, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
				156	{UART2_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
				157	{UART2_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
				158	{I2C2_SDA, (M1 \| PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
				159	{I2C2_SCL, (M1 \| PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
				160	{WAKEUP0, (M15 \| PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
				161	{WAKEUP3, (M1 \| PULL_ENA \| PULL_UP)}, /* Wakeup3.sys_nirq1 */
Lokesh Vutla	687054a	2013-02-12 21:29:08 +0000	[diff] [blame]	162	};
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	163
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	164	const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
				165	{GPIO6_11, (M14 \| PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
				166	{RGMII0_TXC, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
				167	{RGMII0_TXCTL, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
				168	{RGMII0_TXD3, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
				169	{RGMII0_TXD2, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
				170	{RGMII0_TXD1, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
				171	{RGMII0_TXD0, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
				172	{RGMII0_RXC, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
				173	{RGMII0_RXCTL, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
				174	{RGMII0_RXD3, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
				175	{RGMII0_RXD2, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
				176	{RGMII0_RXD1, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
				177	{RGMII0_RXD0, (M0 \| PIN_INPUT \| MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
				178	{VIN2A_D12, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
				179	{VIN2A_D13, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
				180	{VIN2A_D14, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
				181	{VIN2A_D15, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
				182	{VIN2A_D16, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
				183	{VIN2A_D17, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
				184	{VIN2A_D18, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
				185	{VIN2A_D19, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
				186	{VIN2A_D20, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
				187	{VIN2A_D21, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
				188	{VIN2A_D22, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
				189	{VIN2A_D23, (M3 \| PIN_INPUT \| MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
				190	{XREF_CLK1, (M5 \| PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
				191	{XREF_CLK2, (M5 \| PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
				192	};
				193
				194	const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
				195	{VIN2A_FLD0, (M14 \| PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
Nishanth Menon	4596cf9	2016-11-23 13:25:26 +0530	[diff] [blame^]	196	{RGMII0_TXC, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
				197	{RGMII0_TXCTL, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
				198	{RGMII0_TXD3, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
				199	{RGMII0_TXD2, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
				200	{RGMII0_TXD1, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
				201	{RGMII0_TXD0, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
				202	{RGMII0_RXC, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
				203	{RGMII0_RXCTL, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
				204	{RGMII0_RXD3, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
				205	{RGMII0_RXD2, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
				206	{RGMII0_RXD1, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
				207	{RGMII0_RXD0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
				208	{VIN2A_D12, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
				209	{VIN2A_D13, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
				210	{VIN2A_D14, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
				211	{VIN2A_D15, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
				212	{VIN2A_D16, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
				213	{VIN2A_D17, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
				214	{VIN2A_D18, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
				215	{VIN2A_D19, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
				216	{VIN2A_D20, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
				217	{VIN2A_D21, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
				218	{VIN2A_D22, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
				219	{VIN2A_D23, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	220	{XREF_CLK2, (M5 \| PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
				221	};
				222
Lokesh Vutla	4d74804	2016-11-23 13:25:25 +0530	[diff] [blame]	223	const struct pad_conf_entry dra71x_core_padconf_array[] = {
				224	{GPMC_AD0, (M3 \| PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
				225	{GPMC_AD1, (M3 \| PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
				226	{GPMC_AD2, (M3 \| PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
				227	{GPMC_AD3, (M3 \| PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
				228	{GPMC_AD4, (M3 \| PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
				229	{GPMC_AD5, (M3 \| PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
				230	{GPMC_AD6, (M3 \| PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
				231	{GPMC_AD7, (M3 \| PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
				232	{GPMC_AD8, (M3 \| PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
				233	{GPMC_AD9, (M3 \| PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
				234	{GPMC_AD10, (M3 \| PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
				235	{GPMC_AD11, (M3 \| PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
				236	{GPMC_AD12, (M3 \| PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
				237	{GPMC_AD13, (M3 \| PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
				238	{GPMC_AD14, (M3 \| PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
				239	{GPMC_AD15, (M3 \| PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
				240	{GPMC_A0, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
				241	{GPMC_A1, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
				242	{GPMC_A2, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
				243	{GPMC_A3, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
				244	{GPMC_A4, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
				245	{GPMC_A5, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
				246	{GPMC_A6, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
				247	{GPMC_A7, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
				248	{GPMC_A8, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
				249	{GPMC_A9, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
				250	{GPMC_A10, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
				251	{GPMC_A11, (M14 \| PIN_INPUT)}, /* gpmc_a11.gpio2_1 */
				252	{GPMC_A13, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
				253	{GPMC_A14, (M1 \| PIN_INPUT_PULLUP \| MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
				254	{GPMC_A15, (M1 \| PIN_INPUT_PULLUP \| MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
				255	{GPMC_A16, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
				256	{GPMC_A17, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
				257	{GPMC_A18, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
				258	{GPMC_A19, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
				259	{GPMC_A20, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
				260	{GPMC_A21, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
				261	{GPMC_A22, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
				262	{GPMC_A23, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
				263	{GPMC_A24, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
				264	{GPMC_A25, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
				265	{GPMC_A26, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
				266	{GPMC_A27, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
				267	{GPMC_CS1, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
				268	{GPMC_CS2, (M1 \| PIN_INPUT_PULLUP \| MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
				269	{GPMC_CS3, (M3 \| PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
				270	{VIN2A_CLK0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
				271	{VIN2A_FLD0, (M14 \| PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
				272	{VIN2A_HSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
				273	{VIN2A_VSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
				274	{VIN2A_D0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
				275	{VIN2A_D1, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
				276	{VIN2A_D2, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
				277	{VIN2A_D3, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
				278	{VIN2A_D4, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
				279	{VIN2A_D5, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
				280	{VIN2A_D6, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
				281	{VIN2A_D7, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
				282	{VIN2A_D8, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
				283	{VIN2A_D9, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
				284	{VIN2A_D10, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
				285	{VIN2A_D11, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
				286	{VIN2A_D12, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
				287	{VIN2A_D13, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
				288	{VIN2A_D14, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
				289	{VIN2A_D15, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
				290	{VIN2A_D16, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
				291	{VIN2A_D17, (M3 \| PIN_OUTPUT \| MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
				292	{VIN2A_D18, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
				293	{VIN2A_D19, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
				294	{VIN2A_D20, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
				295	{VIN2A_D21, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
				296	{VIN2A_D22, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
				297	{VIN2A_D23, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
				298	{VOUT1_D2, (M0 \| PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
				299	{VOUT1_D10, (M0 \| PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
				300	{VOUT1_D18, (M0 \| PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
				301	{MDIO_MCLK, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
				302	{MDIO_D, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_d.mdio_d */
				303	{RGMII0_TXC, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
				304	{RGMII0_TXCTL, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
				305	{RGMII0_TXD3, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
				306	{RGMII0_TXD2, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
				307	{RGMII0_TXD1, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
				308	{RGMII0_TXD0, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
				309	{RGMII0_RXC, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
				310	{RGMII0_RXCTL, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
				311	{RGMII0_RXD3, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
				312	{RGMII0_RXD2, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
				313	{RGMII0_RXD1, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
				314	{RGMII0_RXD0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
				315	{USB1_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
				316	{USB2_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
				317	{GPIO6_14, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
				318	{GPIO6_15, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
				319	{GPIO6_16, (M14 \| PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
				320	{XREF_CLK2, (M5 \| PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
				321	{MCASP1_ACLKX, (M14 \| PIN_INPUT)}, /* mcasp1_aclkx.gpio7_31 */
				322	{MCASP1_FSX, (M14 \| 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
				323	{MCASP1_AXR0, (M10 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
				324	{MCASP1_AXR1, (M10 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
				325	{MCASP1_AXR2, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
				326	{MCASP1_AXR3, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
				327	{MCASP1_AXR4, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
				328	{MCASP1_AXR5, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
				329	{MCASP1_AXR6, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
				330	{MCASP1_AXR7, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
				331	{MCASP1_AXR12, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
				332	{MCASP1_AXR13, (M1 \| PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
				333	{MCASP1_AXR14, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
				334	{MCASP1_AXR15, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
				335	{MCASP3_ACLKX, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
				336	{MCASP3_FSX, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
				337	{MCASP3_AXR0, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
				338	{MCASP3_AXR1, (M0 \| PIN_INPUT_SLEW \| VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
				339	{MMC1_CLK, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
				340	{MMC1_CMD, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
				341	{MMC1_DAT0, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
				342	{MMC1_DAT1, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
				343	{MMC1_DAT2, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
				344	{MMC1_DAT3, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
				345	{MMC1_SDCD, (M14 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
				346	{MMC1_SDWP, (M14 \| PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
				347	{SPI1_SCLK, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
				348	{SPI1_D1, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
				349	{SPI1_D0, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
				350	{SPI1_CS0, (M0 \| PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
				351	{SPI1_CS1, (M14 \| PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
				352	{SPI1_CS2, (M14 \| PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
				353	{SPI1_CS3, (M6 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
				354	{SPI2_SCLK, (M1 \| PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
				355	{SPI2_D1, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
				356	{SPI2_D0, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
				357	{SPI2_CS0, (M1 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
				358	{DCAN1_TX, (M15 \| PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
				359	{DCAN1_RX, (M14 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
				360	{UART1_RXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
				361	{UART1_TXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_txd.uart1_txd */
				362	{UART1_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
				363	{UART1_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
				364	{UART2_RXD, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
				365	{UART2_TXD, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
				366	{UART2_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
				367	{UART2_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
				368	{I2C2_SDA, (M1 \| PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
				369	{I2C2_SCL, (M1 \| PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
				370	{WAKEUP0, (M15 \| PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
				371	{WAKEUP3, (M1 \| PULL_ENA \| PULL_UP)}, /* Wakeup3.sys_nirq1 */
				372	};
				373
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	374	const struct pad_conf_entry early_padconf[] = {
				375	#if (CONFIG_CONS_INDEX == 1)
				376	{UART1_RXD, (PIN_INPUT_SLEW \| M0)}, /* UART1_RXD */
				377	{UART1_TXD, (PIN_INPUT_SLEW \| M0)}, /* UART1_TXD */
				378	#elif (CONFIG_CONS_INDEX == 3)
				379	{UART3_RXD, (PIN_INPUT_SLEW \| M0)}, /* UART3_RXD */
				380	{UART3_TXD, (PIN_INPUT_SLEW \| M0)}, /* UART3_TXD */
				381	#endif
				382	{I2C1_SDA, (PIN_INPUT \| M0)}, /* I2C1_SDA */
				383	{I2C1_SCL, (PIN_INPUT \| M0)}, /* I2C1_SCL */
				384	};
				385
				386	#ifdef CONFIG_IODELAY_RECALIBRATION
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	387	const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
Mugunthan V N	0a888f5	2015-06-22 14:43:10 +0530	[diff] [blame]	388	{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
				389	{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
				390	{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
				391	{0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
				392	{0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
				393	{0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
				394	{0x740, 0, 220}, /* RGMMI0_TXC_OUT */
				395	{0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
				396	{0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
				397	{0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
				398	{0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
				399	{0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
				400	/* These values are for using RGMII1 configuration on VIN2a_x pins. */
				401	{0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
				402	{0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
				403	{0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
				404	{0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
				405	{0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
				406	{0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
				407	{0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
				408	{0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
				409	{0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
				410	{0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
				411	{0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
				412	{0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	413	{0x144, 0, 0}, /* CFG_GPMC_A13_IN */
				414	{0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
				415	{0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
				416	{0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
				417	{0x170, 0, 0 }, /* CFG_GPMC_A16_OUT */
				418	{0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
				419	{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
				420	{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	421	};
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	422
				423	const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
				424	{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
				425	{0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
				426	{0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
				427	{0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
				428	{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
				429	{0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
				430	{0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
Nishanth Menon	4596cf9	2016-11-23 13:25:26 +0530	[diff] [blame^]	431	{0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
				432	{0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
				433	{0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
				434	{0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
				435	{0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
				436	{0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
				437	{0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
				438	{0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
				439	{0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
				440	{0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
				441	{0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
				442	{0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
				443	{0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
				444	{0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
				445	{0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
				446	{0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
				447	{0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
				448	{0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
				449	{0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
				450	{0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
				451	{0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
				452	{0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
				453	{0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
				454	{0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
				455	{0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
				456	{0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
Nishanth Menon	8cac147	2016-03-15 18:09:17 -0500	[diff] [blame]	457	};
				458
Lokesh Vutla	4d74804	2016-11-23 13:25:25 +0530	[diff] [blame]	459	const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
				460	{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
				461	{0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
				462	{0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
				463	{0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
				464	{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
				465	{0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
				466	{0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
				467	{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
				468	{0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
				469	{0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
				470	{0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
				471	{0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
				472	{0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
				473	{0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
				474	{0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
				475	{0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
				476	{0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
				477	{0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
				478	{0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
				479	{0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
				480	{0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
				481	{0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
				482	{0x0A50, 2031, 0}, /* CFG_VIN2A_D10_IN */
				483	{0x0A5C, 1702, 0}, /* CFG_VIN2A_D11_IN */
				484	{0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
				485	{0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
				486	{0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
				487	{0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
				488	{0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
				489	{0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
				490	{0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
				491	{0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
				492	{0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
				493	{0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
				494	{0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
				495	{0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
				496	{0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
				497	{0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
				498	{0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
				499	{0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
				500	{0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
				501	{0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
				502	{0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
				503	{0x0B4C, 1224, 618}, /* CFG_VIN2A_D8_IN */
				504	{0x0B58, 1373, 509}, /* CFG_VIN2A_D9_IN */
				505	{0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
				506	{0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
				507	};
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	508	#endif
				509
				510	const struct pad_conf_entry dra74x_core_padconf_array[] = {
				511	{GPMC_AD0, (M3 \| PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
				512	{GPMC_AD1, (M3 \| PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
				513	{GPMC_AD2, (M3 \| PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
				514	{GPMC_AD3, (M3 \| PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
				515	{GPMC_AD4, (M3 \| PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
				516	{GPMC_AD5, (M3 \| PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
				517	{GPMC_AD6, (M3 \| PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
				518	{GPMC_AD7, (M3 \| PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
				519	{GPMC_AD8, (M3 \| PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
				520	{GPMC_AD9, (M3 \| PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
				521	{GPMC_AD10, (M3 \| PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
				522	{GPMC_AD11, (M3 \| PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
				523	{GPMC_AD12, (M3 \| PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
				524	{GPMC_AD13, (M3 \| PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
				525	{GPMC_AD14, (M3 \| PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
				526	{GPMC_AD15, (M3 \| PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
				527	{GPMC_A0, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
				528	{GPMC_A1, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
				529	{GPMC_A2, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
				530	{GPMC_A3, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
				531	{GPMC_A4, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
				532	{GPMC_A5, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
				533	{GPMC_A6, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
				534	{GPMC_A7, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
				535	{GPMC_A8, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
				536	{GPMC_A9, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
				537	{GPMC_A10, (M3 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
				538	{GPMC_A11, (M14 \| PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
Vignesh R	900e210	2016-02-10 10:51:43 +0530	[diff] [blame]	539	{GPMC_A13, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
				540	{GPMC_A14, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
				541	{GPMC_A15, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
				542	{GPMC_A16, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
				543	{GPMC_A17, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
				544	{GPMC_A18, (M1 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	545	{GPMC_A19, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
				546	{GPMC_A20, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
				547	{GPMC_A21, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
				548	{GPMC_A22, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
				549	{GPMC_A23, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
				550	{GPMC_A24, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
				551	{GPMC_A25, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
				552	{GPMC_A26, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
				553	{GPMC_A27, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
				554	{GPMC_CS1, (M1 \| PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
Vignesh R	900e210	2016-02-10 10:51:43 +0530	[diff] [blame]	555	{GPMC_CS2, (M1 \| PIN_INPUT_PULLUP \| MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	556	{GPMC_CS3, (M3 \| PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
				557	{VIN1A_CLK0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
				558	{VIN1A_DE0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
				559	{VIN1A_FLD0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
				560	{VIN1A_HSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
				561	{VIN1A_VSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
				562	{VIN1A_D0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
				563	{VIN1A_D1, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
				564	{VIN1A_D2, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
				565	{VIN1A_D3, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
				566	{VIN1A_D4, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
				567	{VIN1A_D5, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
				568	{VIN1A_D6, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
				569	{VIN1A_D7, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
				570	{VIN1A_D8, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
				571	{VIN1A_D9, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
				572	{VIN1A_D10, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
				573	{VIN1A_D11, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
				574	{VIN1A_D12, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
				575	{VIN1A_D13, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
				576	{VIN1A_D14, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
				577	{VIN1A_D15, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
				578	{VIN1A_D16, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
				579	{VIN1A_D17, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
				580	{VIN1A_D18, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
				581	{VIN1A_D19, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
				582	{VIN1A_D20, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
				583	{VIN1A_D21, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
				584	{VIN1A_D22, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
				585	{VIN1A_D23, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
				586	{VIN2A_D12, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
				587	{VIN2A_D13, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
				588	{VIN2A_D14, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
				589	{VIN2A_D15, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
				590	{VIN2A_D16, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
				591	{VIN2A_D17, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
				592	{VIN2A_D18, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
				593	{VIN2A_D19, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
				594	{VIN2A_D20, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
				595	{VIN2A_D21, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
				596	{VIN2A_D22, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
				597	{VIN2A_D23, (M3 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
				598	{VOUT1_CLK, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
				599	{VOUT1_DE, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
				600	{VOUT1_HSYNC, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
				601	{VOUT1_VSYNC, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
				602	{VOUT1_D0, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
				603	{VOUT1_D1, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
				604	{VOUT1_D2, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
				605	{VOUT1_D3, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
				606	{VOUT1_D4, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
				607	{VOUT1_D5, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
				608	{VOUT1_D6, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
				609	{VOUT1_D7, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
				610	{VOUT1_D8, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
				611	{VOUT1_D9, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
				612	{VOUT1_D10, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
				613	{VOUT1_D11, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
				614	{VOUT1_D12, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
				615	{VOUT1_D13, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
				616	{VOUT1_D14, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
				617	{VOUT1_D15, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
				618	{VOUT1_D16, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
				619	{VOUT1_D17, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
				620	{VOUT1_D18, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
				621	{VOUT1_D19, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
				622	{VOUT1_D20, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
				623	{VOUT1_D21, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
				624	{VOUT1_D22, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
				625	{VOUT1_D23, (M0 \| PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
				626	{MDIO_MCLK, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
				627	{MDIO_D, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* mdio_d.mdio_d */
				628	{RGMII0_TXC, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
				629	{RGMII0_TXCTL, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
				630	{RGMII0_TXD3, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
				631	{RGMII0_TXD2, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
				632	{RGMII0_TXD1, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
				633	{RGMII0_TXD0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
				634	{RGMII0_RXC, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
				635	{RGMII0_RXCTL, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
				636	{RGMII0_RXD3, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
				637	{RGMII0_RXD2, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
				638	{RGMII0_RXD1, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
				639	{RGMII0_RXD0, (M0 \| PIN_INPUT_PULLDOWN \| MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
				640	{USB1_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
				641	{USB2_DRVVBUS, (M0 \| PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
				642	{GPIO6_14, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
				643	{GPIO6_15, (M9 \| PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
				644	{GPIO6_16, (M14 \| PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
				645	{XREF_CLK2, (M5 \| PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
				646	{MCASP1_ACLKX, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
				647	{MCASP1_FSX, (M0 \| PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
				648	{MCASP1_AXR0, (M0 \| PIN_INPUT_SLEW \| VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
				649	{MCASP1_AXR1, (M0 \| PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
				650	{MCASP1_AXR2, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
				651	{MCASP1_AXR3, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
				652	{MCASP1_AXR4, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
				653	{MCASP1_AXR5, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
				654	{MCASP1_AXR6, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
				655	{MCASP1_AXR7, (M14 \| PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
				656	{MCASP1_AXR12, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
				657	{MCASP1_AXR13, (M1 \| PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
				658	{MCASP1_AXR14, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
				659	{MCASP1_AXR15, (M1 \| PIN_INPUT_SLEW \| VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
				660	{MCASP2_ACLKR, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
				661	{MCASP3_ACLKX, (M0 \| PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
				662	{MCASP3_FSX, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
				663	{MCASP3_AXR0, (M0 \| PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
				664	{MCASP3_AXR1, (M0 \| PIN_INPUT_SLEW \| VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
				665	{MMC1_CLK, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
				666	{MMC1_CMD, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
				667	{MMC1_DAT0, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
				668	{MMC1_DAT1, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
				669	{MMC1_DAT2, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
				670	{MMC1_DAT3, (M0 \| PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
Lokesh Vutla	26eccf3	2016-03-08 10:10:20 +0530	[diff] [blame]	671	{MMC1_SDCD, (M14 \| PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	672	{MMC1_SDWP, (M14 \| PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
				673	{GPIO6_11, (M14 \| PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
				674	{SPI1_SCLK, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
				675	{SPI1_D1, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
				676	{SPI1_D0, (M0 \| PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
				677	{SPI1_CS0, (M0 \| PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
				678	{SPI1_CS1, (M14 \| PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
				679	{SPI1_CS2, (M14 \| PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
				680	{SPI1_CS3, (M6 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
				681	{SPI2_SCLK, (M1 \| PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
				682	{SPI2_D1, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
				683	{SPI2_D0, (M1 \| PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
				684	{SPI2_CS0, (M1 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
Roger Quadros	a5878f1	2015-06-24 17:00:11 +0300	[diff] [blame]	685	{DCAN1_TX, (M15 \| PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	686	{DCAN1_RX, (M14 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
				687	{UART1_RXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
				688	{UART1_TXD, (M0 \| PIN_INPUT_PULLUP \| SLEWCONTROL)}, /* uart1_txd.uart1_txd */
				689	{UART1_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
				690	{UART1_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
				691	{UART2_RXD, (M3 \| PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
				692	{UART2_TXD, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
				693	{UART2_CTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
				694	{UART2_RTSN, (M3 \| PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
				695	{I2C2_SDA, (M0 \| PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
				696	{I2C2_SCL, (M0 \| PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
Roger Quadros	a5878f1	2015-06-24 17:00:11 +0300	[diff] [blame]	697	{WAKEUP0, (M15 \| PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
Cooper Jr., Franklin	bc62296	2015-11-19 08:03:54 -0600	[diff] [blame]	698	{WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	699	};
				700
				701	#ifdef CONFIG_IODELAY_RECALIBRATION
Nishanth Menon	0358923	2015-08-13 09:50:59 -0500	[diff] [blame]	702	const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	703	{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
				704	{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
				705	{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
				706	{0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
				707	{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
				708	{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
				709	{0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
				710	{0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
				711	{0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
				712	{0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
				713	{0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
				714	{0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
				715	{0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
				716	{0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
				717	{0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
				718	{0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
				719	{0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
				720	{0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
				721	{0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
				722	{0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
				723	{0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
				724	{0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
				725	{0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
				726	{0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
				727	{0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
				728	{0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
				729	{0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
				730	{0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
				731	{0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
				732	{0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
				733	{0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
				734	{0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
				735	{0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
				736	{0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
				737	{0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
				738	{0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
				739	{0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
				740	{0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
				741	{0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
				742	{0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
				743	{0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
				744	{0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
				745	{0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
				746	{0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
				747	{0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
				748	{0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
				749	{0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
				750	{0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
				751	{0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
				752	{0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
				753	{0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
				754	{0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
				755	{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
Vignesh R	900e210	2016-02-10 10:51:43 +0530	[diff] [blame]	756	{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
				757	{0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
				758	{0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
				759	{0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
				760	{0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
				761	{0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
				762	{0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
				763	{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	764	};
Nishanth Menon	0358923	2015-08-13 09:50:59 -0500	[diff] [blame]	765
				766	const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
				767	{0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
				768	{0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
				769	{0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
				770	{0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
				771	{0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
				772	{0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
				773	{0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
				774	{0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
				775	{0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
				776	{0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
				777	{0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
				778	{0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
				779	{0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
				780	{0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
				781	{0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
				782	{0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
				783	{0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
				784	{0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
				785	{0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
				786	{0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
				787	{0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
				788	{0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
				789	{0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
				790	{0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
				791	{0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
				792	{0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
				793	{0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
				794	{0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
				795	{0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
				796	{0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
				797	{0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
				798	{0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
				799	{0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
				800	{0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
				801	{0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
				802	{0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
				803	{0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
				804	{0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
				805	{0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
				806	{0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
				807	{0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
				808	{0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
				809	{0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
				810	{0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
				811	{0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
				812	{0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
				813	{0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
				814	{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
				815	{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
				816	{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
				817	{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
				818	{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
				819	{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
Vignesh R	900e210	2016-02-10 10:51:43 +0530	[diff] [blame]	820	{0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
				821	{0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
				822	{0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
				823	{0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
				824	{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
				825	{0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
				826	{0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
				827	{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
Nishanth Menon	0358923	2015-08-13 09:50:59 -0500	[diff] [blame]	828	};
Nishanth Menon	27d170a	2015-06-04 16:42:39 +0530	[diff] [blame]	829	#endif
				830
Lokesh Vutla	687054a	2013-02-12 21:29:08 +0000	[diff] [blame]	831	#endif /* _MUX_DATA_DRA7XX_H_ */