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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
Michal Simekf4c7a4a2018-06-04 14:57:34 +020016static long do_fpga_get_device(char *arg)
17{
18 long dev = FPGA_INVALID_DEVICE;
19 char *devstr = env_get("fpga");
20
21 if (devstr)
22 /* Should be strtol to handle -1 cases */
23 dev = simple_strtol(devstr, NULL, 16);
24
25 if (arg)
26 dev = simple_strtol(arg, NULL, 16);
27
28 debug("%s: device = %ld\n", __func__, dev);
29
30 return dev;
31}
32
Michal Simek85754792018-06-04 15:51:23 +020033static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
34 cmd_tbl_t *cmdtp, int argc, char *const argv[])
35{
36 size_t local_data_size;
37 long local_fpga_data;
38
39 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
40
41 if (argc != cmdtp->maxargs) {
42 debug("fpga: incorrect parameters passed\n");
43 return CMD_RET_USAGE;
44 }
45
46 *dev = do_fpga_get_device(argv[0]);
47
48 local_fpga_data = simple_strtol(argv[1], NULL, 16);
49 if (!local_fpga_data) {
50 debug("fpga: zero fpga_data address\n");
51 return CMD_RET_USAGE;
52 }
53 *fpga_data = local_fpga_data;
54
55 local_data_size = simple_strtoul(argv[2], NULL, 16);
56 if (!local_data_size) {
57 debug("fpga: zero size\n");
58 return CMD_RET_USAGE;
59 }
60 *data_size = local_data_size;
61
62 return 0;
63}
64
wdenk4a9cbbe2002-08-27 09:48:53 +000065/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010066enum {
67 FPGA_NONE = -1,
Michal Simek5cf22282017-01-06 11:20:54 +010068 FPGA_LOADMK,
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053069 FPGA_LOADS,
Michal Simek5cf22282017-01-06 11:20:54 +010070};
wdenk4a9cbbe2002-08-27 09:48:53 +000071
Michal Simek323fe382018-05-30 10:00:40 +020072/*
73 * Map op to supported operations. We don't use a table since we
74 * would just have to relocate it from flash anyway.
75 */
76static int fpga_get_op(char *opstr)
77{
78 int op = FPGA_NONE;
79
Michal Simek323fe382018-05-30 10:00:40 +020080#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simek49503f92018-06-04 15:51:16 +020081 if (!strcmp("loadmk", opstr))
Michal Simek323fe382018-05-30 10:00:40 +020082 op = FPGA_LOADMK;
83#endif
Michal Simek323fe382018-05-30 10:00:40 +020084#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
85 else if (!strcmp("loads", opstr))
86 op = FPGA_LOADS;
87#endif
88
89 return op;
90}
91
wdenk4a9cbbe2002-08-27 09:48:53 +000092/* ------------------------------------------------------------------------- */
93/* command form:
94 * fpga <op> <device number> <data addr> <datasize>
95 * where op is 'load', 'dump', or 'info'
96 * If there is no device number field, the fpga environment variable is used.
97 * If there is no data addr field, the fpgadata environment variable is used.
98 * The info command requires no data address field.
99 */
Michal Simekfc598412013-04-26 13:10:07 +0200100int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000101{
wdenkd4ca31c2004-01-02 14:00:00 +0000102 int op, dev = FPGA_INVALID_DEVICE;
103 size_t data_size = 0;
104 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -0600105 char *devstr = env_get("fpga");
106 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +0000107 int rc = FPGA_FAIL;
Michal Simekfc598412013-04-26 13:10:07 +0200108#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100109 const char *fit_uname = NULL;
110 ulong fit_addr;
111#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530112#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
113 struct fpga_secure_info fpga_sec_info;
114
115 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
116#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000117
wdenkd4ca31c2004-01-02 14:00:00 +0000118 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +0200119 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +0000120 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +0200121 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000122
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530123 if (argc > 9 || argc < 2) {
124 debug("%s: Too many or too few args (%d)\n", __func__, argc);
125 return CMD_RET_USAGE;
126 }
127
Michal Simek323fe382018-05-30 10:00:40 +0200128 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530129
130 switch (op) {
Michal Simek55010962018-05-30 09:57:42 +0200131 case FPGA_NONE:
132 printf("Unknown fpga operation \"%s\"\n", argv[1]);
133 return CMD_RET_USAGE;
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530134#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
135 case FPGA_LOADS:
136 if (argc < 7)
137 return CMD_RET_USAGE;
138 if (argc == 8)
139 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
140 simple_strtoull(argv[7],
141 NULL, 16);
142 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
143 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +0200144
145 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
146 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
147 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
148 return CMD_RET_USAGE;
149 }
150
151 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
152 !fpga_sec_info.userkey_addr) {
153 puts("ERR: User key not provided\n");
154 return CMD_RET_USAGE;
155 }
156
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530157 argc = 5;
158 break;
159#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530160 default:
161 break;
162 }
163
164 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +0000165 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +0200166 data_size = simple_strtoul(argv[4], NULL, 16);
Michal Simek5cadab62018-05-30 11:28:57 +0200167 if (!data_size) {
168 puts("Zero data_size\n");
169 return CMD_RET_USAGE;
170 }
wdenkd4ca31c2004-01-02 14:00:00 +0000171 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100172#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200173 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
174 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100175 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200176 debug("* fpga: subimage '%s' from FIT image ",
177 fit_uname);
178 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100179 } else
180#endif
181 {
Michal Simekfc598412013-04-26 13:10:07 +0200182 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000183 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200184 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100185 }
Michal Simek455ad582016-01-05 13:51:48 +0100186 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Michal Simek5cadab62018-05-30 11:28:57 +0200187 if (!fpga_data) {
188 puts("Zero fpga_data address\n");
189 return CMD_RET_USAGE;
190 }
wdenkd4ca31c2004-01-02 14:00:00 +0000191 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200192 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000193 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000194 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000195
Stefano Babica790b5b2010-10-19 09:22:52 +0200196 if (dev == FPGA_INVALID_DEVICE) {
197 puts("FPGA device not specified\n");
Michal Simekccd65202018-05-30 10:04:34 +0200198 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200199 }
200
201 switch (op) {
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530202#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
203 case FPGA_LOADS:
204 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
205 break;
206#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530207#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200208 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200209 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200210#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100211 case IMAGE_FORMAT_LEGACY:
212 {
Michal Simekfc598412013-04-26 13:10:07 +0200213 image_header_t *hdr =
214 (image_header_t *)fpga_data;
215 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200216 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200217
Michal Simek32d7cdd2013-10-04 10:51:01 +0200218 comp = image_get_comp(hdr);
219 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200220#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200221 ulong image_buf = image_get_data(hdr);
222 data = image_get_load(hdr);
223 ulong image_size = ~0UL;
224
225 if (gunzip((void *)data, ~0UL,
226 (void *)image_buf,
227 &image_size) != 0) {
228 puts("GUNZIP: error\n");
229 return 1;
230 }
231 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200232#else
233 puts("Gunzip image is not supported\n");
234 return 1;
235#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200236 } else {
237 data = (ulong)image_get_data(hdr);
238 data_size = image_get_data_size(hdr);
239 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200240 rc = fpga_load(dev, (void *)data, data_size,
241 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200242 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100243 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200244#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100245#if defined(CONFIG_FIT)
246 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100247 {
248 const void *fit_hdr = (const void *)fpga_data;
249 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000250 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100251
252 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200253 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100254 return 1;
255 }
256
Michal Simekfc598412013-04-26 13:10:07 +0200257 if (!fit_check_format(fit_hdr)) {
258 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100259 return 1;
260 }
261
262 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200263 noffset = fit_image_get_node(fit_hdr,
264 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100265 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200266 printf("Can't find '%s' FIT subimage\n",
267 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100268 return 1;
269 }
270
271 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000272 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100273 puts ("Bad Data Hash\n");
274 return 1;
275 }
276
277 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200278 if (fit_image_get_data(fit_hdr, noffset,
279 &fit_data, &data_size)) {
280 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100281 return 1;
282 }
283
Michal Simek7a78bd22014-05-02 14:09:30 +0200284 rc = fpga_load(dev, fit_data, data_size,
285 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100286 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100287 break;
288#endif
289 default:
Michal Simekfc598412013-04-26 13:10:07 +0200290 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100291 rc = FPGA_FAIL;
292 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200293 }
294 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530295#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200296
wdenkd4ca31c2004-01-02 14:00:00 +0000297 default:
Michal Simekfc598412013-04-26 13:10:07 +0200298 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000299 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000300 }
Michal Simekfc598412013-04-26 13:10:07 +0200301 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000302}
303
Michal Simek49503f92018-06-04 15:51:16 +0200304#if defined(CONFIG_CMD_FPGA_LOADFS)
305static int do_fpga_loadfs(cmd_tbl_t *cmdtp, int flag, int argc,
306 char *const argv[])
307{
308 size_t data_size = 0;
309 long fpga_data, dev;
310 int ret;
311 fpga_fs_info fpga_fsinfo;
312
313 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
314 cmdtp, argc, argv);
315 if (ret)
316 return ret;
317
318 fpga_fsinfo.fstype = FS_TYPE_ANY;
319 fpga_fsinfo.blocksize = (unsigned int)simple_strtoul(argv[3], NULL, 16);
320 fpga_fsinfo.interface = argv[4];
321 fpga_fsinfo.dev_part = argv[5];
322 fpga_fsinfo.filename = argv[6];
323
324 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
325}
326#endif
327
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200328static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
329 char * const argv[])
330{
331 long dev = do_fpga_get_device(argv[0]);
332
333 return fpga_info(dev);
334}
335
Michal Simek85754792018-06-04 15:51:23 +0200336static int do_fpga_dump(cmd_tbl_t *cmdtp, int flag, int argc,
337 char * const argv[])
338{
339 size_t data_size = 0;
340 long fpga_data, dev;
341 int ret;
342
343 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
344 cmdtp, argc, argv);
345 if (ret)
346 return ret;
347
348 return fpga_dump(dev, (void *)fpga_data, data_size);
349}
350
351static int do_fpga_load(cmd_tbl_t *cmdtp, int flag, int argc,
352 char * const argv[])
353{
354 size_t data_size = 0;
355 long fpga_data, dev;
356 int ret;
357
358 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
359 cmdtp, argc, argv);
360 if (ret)
361 return ret;
362
363 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
364}
365
366static int do_fpga_loadb(cmd_tbl_t *cmdtp, int flag, int argc,
367 char * const argv[])
368{
369 size_t data_size = 0;
370 long fpga_data, dev;
371 int ret;
372
373 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
374 cmdtp, argc, argv);
375 if (ret)
376 return ret;
377
378 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
379}
380
381#if defined(CONFIG_CMD_FPGA_LOADP)
382static int do_fpga_loadp(cmd_tbl_t *cmdtp, int flag, int argc,
383 char * const argv[])
384{
385 size_t data_size = 0;
386 long fpga_data, dev;
387 int ret;
388
389 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
390 cmdtp, argc, argv);
391 if (ret)
392 return ret;
393
394 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
395}
396#endif
397
398#if defined(CONFIG_CMD_FPGA_LOADBP)
399static int do_fpga_loadbp(cmd_tbl_t *cmdtp, int flag, int argc,
400 char * const argv[])
401{
402 size_t data_size = 0;
403 long fpga_data, dev;
404 int ret;
405
406 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
407 cmdtp, argc, argv);
408 if (ret)
409 return ret;
410
411 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
412 BIT_PARTIAL);
413}
414#endif
415
Michal Simek9657d972018-06-04 14:55:20 +0200416static cmd_tbl_t fpga_commands[] = {
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200417 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek85754792018-06-04 15:51:23 +0200418 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
419 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
420 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
421#if defined(CONFIG_CMD_FPGA_LOADP)
422 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
423#endif
424#if defined(CONFIG_CMD_FPGA_LOADBP)
425 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
426#endif
Michal Simek49503f92018-06-04 15:51:16 +0200427#if defined(CONFIG_CMD_FPGA_LOADFS)
428 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
429#endif
Michal Simek9657d972018-06-04 14:55:20 +0200430};
431
432static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
433 char *const argv[])
434{
435 cmd_tbl_t *fpga_cmd;
436 int ret;
437
438 if (argc < 2)
439 return CMD_RET_USAGE;
440
441 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
442 ARRAY_SIZE(fpga_commands));
443
444 /* This should be removed when all functions are converted */
445 if (!fpga_cmd)
446 return do_fpga(cmdtp, flag, argc, argv);
447
448 /* FIXME This can't be reached till all functions are converted */
449 if (!fpga_cmd) {
450 debug("fpga: non existing command\n");
451 return CMD_RET_USAGE;
452 }
453
454 argc -= 2;
455 argv += 2;
456
457 if (argc > fpga_cmd->maxargs) {
458 debug("fpga: more parameters passed\n");
459 return CMD_RET_USAGE;
460 }
461
462 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
463
464 return cmd_process_error(fpga_cmd, ret);
465}
466
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530467#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9657d972018-06-04 14:55:20 +0200468U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530469#else
Michal Simek9657d972018-06-04 14:55:20 +0200470U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530471#endif
Michal Simekfc598412013-04-26 13:10:07 +0200472 "loadable FPGA image support",
473 "[operation type] [device number] [image address] [image size]\n"
474 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100475 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200476 " info\t[dev]\t\t\tlist known device information\n"
477 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200478#if defined(CONFIG_CMD_FPGA_LOADP)
479 " loadp\t[dev] [address] [size]\t"
480 "Load device from memory buffer with partial bitstream\n"
481#endif
Michal Simekfc598412013-04-26 13:10:07 +0200482 " loadb\t[dev] [address] [size]\t"
483 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200484#if defined(CONFIG_CMD_FPGA_LOADBP)
485 " loadbp\t[dev] [address] [size]\t"
486 "Load device from bitstream buffer with partial bitstream"
487 "(Xilinx only)\n"
488#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530489#if defined(CONFIG_CMD_FPGA_LOADFS)
490 "Load device from filesystem (FAT by default) (Xilinx only)\n"
491 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
492 " [<dev[:part]>] <filename>\n"
493#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530494#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200495 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100496#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200497 "\n"
498 "\tFor loadmk operating on FIT format uImage address must include\n"
499 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100500#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530501#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530502#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
503 "Load encrypted bitstream (Xilinx only)\n"
504 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
505 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
506 "Loads the secure bistreams(authenticated/encrypted/both\n"
507 "authenticated and encrypted) of [size] from [address].\n"
508 "The auth-OCM/DDR flag specifies to perform authentication\n"
509 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
510 "The enc flag specifies which key to be used for decryption\n"
511 "0-device key, 1-user key, 2-no encryption.\n"
512 "The optional Userkey address specifies from which address key\n"
513 "has to be used for decryption if user key is selected.\n"
514 "NOTE: the sceure bitstream has to be created using xilinx\n"
515 "bootgen tool only.\n"
516#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100517);