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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4baa0ab67d504f3b4318f999631e3f83d0c52c4a / . / arch / mips / Kconfig
blob: 76714379a4cec17302adfec8ad82cfbd092c1bc0 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]5 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]7config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +0100[diff] [blame]8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]10
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]11choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]13 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]14
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +0100[diff] [blame]21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]23
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame]26 select DM
27 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]28 select DYNAMIC_IO_PORT_BASE
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame]29 select OF_CONTROL
30 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +0100[diff] [blame]35 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +0100[diff] [blame]36 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]39 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]40 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]41
42config TARGET_VCT
43 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]44 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]48
49config TARGET_DBAU1X00
50 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]56 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]57
58config TARGET_PB1X00
59 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]60 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]61 select SUPPORTS_CPU_MIPS32_R1
62 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]63 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]64 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]65
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]66config ARCH_ATH79
67 bool "Support QCA/Atheros ath79"
68 select OF_CONTROL
69 select DM
70
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]71config MACH_PIC32
72 bool "Support Microchip PIC32"
73 select OF_CONTROL
74 select DM
75
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100[diff] [blame]76config TARGET_XILFPGA
77 bool "Support Imagination Xilfpga"
78 select OF_CONTROL
79 select DM
80 select DM_SERIAL
81 select DM_GPIO
82 select DM_ETH
83 select SUPPORTS_LITTLE_ENDIAN
84 select SUPPORTS_CPU_MIPS32_R1
85 select SUPPORTS_CPU_MIPS32_R2
86 select MIPS_L1_CACHE_SHIFT_4
87 help
88 This supports IMGTEC MIPSfpga platform
89
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]90endchoice
91
92source "board/dbau1x00/Kconfig"
93source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100[diff] [blame]94source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]95source "board/micronas/vct/Kconfig"
96source "board/pb1x00/Kconfig"
97source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]98source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]99source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]100
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]101if MIPS
102
103choice
104 prompt "Endianness selection"
105 help
106 Some MIPS boards can be configured for either little or big endian
107 byte order. These modes require different U-Boot images. In general there
108 is one preferred byteorder for a particular system but some systems are
109 just as commonly used in the one or the other endianness.
110
111config SYS_BIG_ENDIAN
112 bool "Big endian"
113 depends on SUPPORTS_BIG_ENDIAN
114
115config SYS_LITTLE_ENDIAN
116 bool "Little endian"
117 depends on SUPPORTS_LITTLE_ENDIAN
118
119endchoice
120
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]121choice
122 prompt "CPU selection"
123 default CPU_MIPS32_R2
124
125config CPU_MIPS32_R1
126 bool "MIPS32 Release 1"
127 depends on SUPPORTS_CPU_MIPS32_R1
128 select 32BIT
129 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]130 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]131 MIPS32 architecture.
132
133config CPU_MIPS32_R2
134 bool "MIPS32 Release 2"
135 depends on SUPPORTS_CPU_MIPS32_R2
136 select 32BIT
137 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]138 Choose this option to build an U-Boot for release 2 through 5 of the
139 MIPS32 architecture.
140
141config CPU_MIPS32_R6
142 bool "MIPS32 Release 6"
143 depends on SUPPORTS_CPU_MIPS32_R6
144 select 32BIT
145 help
146 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]147 MIPS32 architecture.
148
149config CPU_MIPS64_R1
150 bool "MIPS64 Release 1"
151 depends on SUPPORTS_CPU_MIPS64_R1
152 select 64BIT
153 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]154 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]155 MIPS64 architecture.
156
157config CPU_MIPS64_R2
158 bool "MIPS64 Release 2"
159 depends on SUPPORTS_CPU_MIPS64_R2
160 select 64BIT
161 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]162 Choose this option to build a kernel for release 2 through 5 of the
163 MIPS64 architecture.
164
165config CPU_MIPS64_R6
166 bool "MIPS64 Release 6"
167 depends on SUPPORTS_CPU_MIPS64_R6
168 select 64BIT
169 help
170 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]171 MIPS64 architecture.
172
173endchoice
174
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]175menu "OS boot interface"
176
177config MIPS_BOOT_CMDLINE_LEGACY
178 bool "Hand over legacy command line to Linux kernel"
179 default y
180 help
181 Enable this option if you want U-Boot to hand over the Yamon-style
182 command line to the kernel. All bootargs will be prepared as argc/argv
183 compatible list. The argument count (argc) is stored in register $a0.
184 The address of the argument list (argv) is stored in register $a1.
185
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]186config MIPS_BOOT_ENV_LEGACY
187 bool "Hand over legacy environment to Linux kernel"
188 default y
189 help
190 Enable this option if you want U-Boot to hand over the Yamon-style
191 environment to the kernel. Information like memory size, initrd
192 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400[diff] [blame]193 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]194
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]195config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]196 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]197 default n
198 help
199 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]200 device tree to the kernel. According to UHI register $a0 will be set
201 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]202
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]203endmenu
204
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]205config SUPPORTS_BIG_ENDIAN
206 bool
207
208config SUPPORTS_LITTLE_ENDIAN
209 bool
210
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]211config SUPPORTS_CPU_MIPS32_R1
212 bool
213
214config SUPPORTS_CPU_MIPS32_R2
215 bool
216
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]217config SUPPORTS_CPU_MIPS32_R6
218 bool
219
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]220config SUPPORTS_CPU_MIPS64_R1
221 bool
222
223config SUPPORTS_CPU_MIPS64_R2
224 bool
225
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]226config SUPPORTS_CPU_MIPS64_R6
227 bool
228
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]229config CPU_MIPS32
230 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]231 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]232
233config CPU_MIPS64
234 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]235 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]236
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]237config MIPS_TUNE_4KC
238 bool
239
240config MIPS_TUNE_14KC
241 bool
242
243config MIPS_TUNE_24KC
244 bool
245
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200[diff] [blame]246config MIPS_TUNE_34KC
247 bool
248
Marek Vasut0a0a9582016-05-06 20:10:33 +0200[diff] [blame]249config MIPS_TUNE_74KC
250 bool
251
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]252config 32BIT
253 bool
254
255config 64BIT
256 bool
257
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]258config SWAP_IO_SPACE
259 bool
260
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]261config SYS_MIPS_CACHE_INIT_RAM_LOAD
262 bool
263
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]264config SYS_DCACHE_SIZE
265 int
266 default 0
267 help
268 The total size of the L1 Dcache, if known at compile time.
269
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]270config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100[diff] [blame]271 int
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]272 default 0
273 help
274 The size of L1 Dcache lines, if known at compile time.
275
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]276config SYS_ICACHE_SIZE
277 int
278 default 0
279 help
280 The total size of the L1 ICache, if known at compile time.
281
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]282config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]283 int
284 default 0
285 help
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]286 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]287
288config SYS_CACHE_SIZE_AUTO
289 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]290 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]291 help
292 Select this (or let it be auto-selected by not defining any cache
293 sizes) in order to allow U-Boot to automatically detect the sizes
294 of caches at runtime. This has a small cost in code size & runtime
295 so if you know the cache configuration for your system at compile
296 time it would be beneficial to configure it.
297
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]298config MIPS_L1_CACHE_SHIFT_4
299 bool
300
301config MIPS_L1_CACHE_SHIFT_5
302 bool
303
304config MIPS_L1_CACHE_SHIFT_6
305 bool
306
307config MIPS_L1_CACHE_SHIFT_7
308 bool
309
310config MIPS_L1_CACHE_SHIFT
311 int
312 default "7" if MIPS_L1_CACHE_SHIFT_7
313 default "6" if MIPS_L1_CACHE_SHIFT_6
314 default "5" if MIPS_L1_CACHE_SHIFT_5
315 default "4" if MIPS_L1_CACHE_SHIFT_4
316 default "5"
317
Paul Burton4baa0ab2016-09-21 11:18:54 +0100[diff] [blame^]318config MIPS_L2_CACHE
319 bool
320 help
321 Select this if your system includes an L2 cache and you want U-Boot
322 to initialise & maintain it.
323
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]324config DYNAMIC_IO_PORT_BASE
325 bool
326
Paul Burtonb2b135d2016-09-21 11:18:53 +0100[diff] [blame]327config MIPS_CM
328 bool
329 help
330 Select this if your system contains a MIPS Coherence Manager and you
331 wish U-Boot to configure it or make use of it to retrieve system
332 information such as cache configuration.
333
334config MIPS_CM_BASE
335 hex
336 default 0x1fbf8000
337 help
338 The physical base address at which to map the MIPS Coherence Manager
339 Global Configuration Registers (GCRs). This should be set such that
340 the GCRs occupy a region of the physical address space which is
341 otherwise unused, or at minimum that software doesn't need to access.
342
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]343endif
344
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]345endmenu