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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6242aa137427f6da6ca47e7a8c9a9f78ad63e00d / . / arch / mips / Kconfig
blob: 53363e38fe4309fa751716ce1d25a12d6d0e3d58 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]5 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]7config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +0100[diff] [blame]8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]10
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]11choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]13 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]14
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +0100[diff] [blame]21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]23
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame^]26 select DM
27 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]28 select DYNAMIC_IO_PORT_BASE
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame^]29 select OF_CONTROL
30 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +0100[diff] [blame]35 select SUPPORTS_CPU_MIPS32_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]36 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]37 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]38
39config TARGET_VCT
40 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]41 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]42 select SUPPORTS_CPU_MIPS32_R1
43 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]44 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]45
46config TARGET_DBAU1X00
47 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]48 select SUPPORTS_BIG_ENDIAN
49 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]50 select SUPPORTS_CPU_MIPS32_R1
51 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]52 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]53 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]54
55config TARGET_PB1X00
56 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]57 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]58 select SUPPORTS_CPU_MIPS32_R1
59 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]60 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]61 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]62
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]63config ARCH_ATH79
64 bool "Support QCA/Atheros ath79"
65 select OF_CONTROL
66 select DM
67
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]68config MACH_PIC32
69 bool "Support Microchip PIC32"
70 select OF_CONTROL
71 select DM
72
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]73endchoice
74
75source "board/dbau1x00/Kconfig"
76source "board/imgtec/malta/Kconfig"
77source "board/micronas/vct/Kconfig"
78source "board/pb1x00/Kconfig"
79source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]80source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]81source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]82
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]83if MIPS
84
85choice
86 prompt "Endianness selection"
87 help
88 Some MIPS boards can be configured for either little or big endian
89 byte order. These modes require different U-Boot images. In general there
90 is one preferred byteorder for a particular system but some systems are
91 just as commonly used in the one or the other endianness.
92
93config SYS_BIG_ENDIAN
94 bool "Big endian"
95 depends on SUPPORTS_BIG_ENDIAN
96
97config SYS_LITTLE_ENDIAN
98 bool "Little endian"
99 depends on SUPPORTS_LITTLE_ENDIAN
100
101endchoice
102
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]103choice
104 prompt "CPU selection"
105 default CPU_MIPS32_R2
106
107config CPU_MIPS32_R1
108 bool "MIPS32 Release 1"
109 depends on SUPPORTS_CPU_MIPS32_R1
110 select 32BIT
111 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]112 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]113 MIPS32 architecture.
114
115config CPU_MIPS32_R2
116 bool "MIPS32 Release 2"
117 depends on SUPPORTS_CPU_MIPS32_R2
118 select 32BIT
119 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]120 Choose this option to build an U-Boot for release 2 through 5 of the
121 MIPS32 architecture.
122
123config CPU_MIPS32_R6
124 bool "MIPS32 Release 6"
125 depends on SUPPORTS_CPU_MIPS32_R6
126 select 32BIT
127 help
128 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]129 MIPS32 architecture.
130
131config CPU_MIPS64_R1
132 bool "MIPS64 Release 1"
133 depends on SUPPORTS_CPU_MIPS64_R1
134 select 64BIT
135 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]136 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]137 MIPS64 architecture.
138
139config CPU_MIPS64_R2
140 bool "MIPS64 Release 2"
141 depends on SUPPORTS_CPU_MIPS64_R2
142 select 64BIT
143 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]144 Choose this option to build a kernel for release 2 through 5 of the
145 MIPS64 architecture.
146
147config CPU_MIPS64_R6
148 bool "MIPS64 Release 6"
149 depends on SUPPORTS_CPU_MIPS64_R6
150 select 64BIT
151 help
152 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]153 MIPS64 architecture.
154
155endchoice
156
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]157menu "OS boot interface"
158
159config MIPS_BOOT_CMDLINE_LEGACY
160 bool "Hand over legacy command line to Linux kernel"
161 default y
162 help
163 Enable this option if you want U-Boot to hand over the Yamon-style
164 command line to the kernel. All bootargs will be prepared as argc/argv
165 compatible list. The argument count (argc) is stored in register $a0.
166 The address of the argument list (argv) is stored in register $a1.
167
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]168config MIPS_BOOT_ENV_LEGACY
169 bool "Hand over legacy environment to Linux kernel"
170 default y
171 help
172 Enable this option if you want U-Boot to hand over the Yamon-style
173 environment to the kernel. Information like memory size, initrd
174 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400[diff] [blame]175 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]176
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]177config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]178 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]179 default n
180 help
181 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]182 device tree to the kernel. According to UHI register $a0 will be set
183 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]184
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]185endmenu
186
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]187config SUPPORTS_BIG_ENDIAN
188 bool
189
190config SUPPORTS_LITTLE_ENDIAN
191 bool
192
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]193config SUPPORTS_CPU_MIPS32_R1
194 bool
195
196config SUPPORTS_CPU_MIPS32_R2
197 bool
198
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]199config SUPPORTS_CPU_MIPS32_R6
200 bool
201
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]202config SUPPORTS_CPU_MIPS64_R1
203 bool
204
205config SUPPORTS_CPU_MIPS64_R2
206 bool
207
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]208config SUPPORTS_CPU_MIPS64_R6
209 bool
210
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]211config CPU_MIPS32
212 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]213 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]214
215config CPU_MIPS64
216 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]217 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]218
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]219config MIPS_TUNE_4KC
220 bool
221
222config MIPS_TUNE_14KC
223 bool
224
225config MIPS_TUNE_24KC
226 bool
227
Marek Vasut0a0a9582016-05-06 20:10:33 +0200[diff] [blame]228config MIPS_TUNE_74KC
229 bool
230
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]231config 32BIT
232 bool
233
234config 64BIT
235 bool
236
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]237config SWAP_IO_SPACE
238 bool
239
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]240config SYS_MIPS_CACHE_INIT_RAM_LOAD
241 bool
242
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]243config MIPS_L1_CACHE_SHIFT_4
244 bool
245
246config MIPS_L1_CACHE_SHIFT_5
247 bool
248
249config MIPS_L1_CACHE_SHIFT_6
250 bool
251
252config MIPS_L1_CACHE_SHIFT_7
253 bool
254
255config MIPS_L1_CACHE_SHIFT
256 int
257 default "7" if MIPS_L1_CACHE_SHIFT_7
258 default "6" if MIPS_L1_CACHE_SHIFT_6
259 default "5" if MIPS_L1_CACHE_SHIFT_5
260 default "4" if MIPS_L1_CACHE_SHIFT_4
261 default "5"
262
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]263config DYNAMIC_IO_PORT_BASE
264 bool
265
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]266endif
267
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]268endmenu