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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4dc7412afa4fe47a02805525e415656d67764839 / . / arch / mips / cpu / mips32 / start.S
blob: 65acf7d2a12958b54aaa946e8025724dacb0ca1a [file] [log] [blame]
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]1/*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]25#include <asm-offsets.h>
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]26#include <config.h>
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29
Daniel Schwierzeckab2a98b2011-07-27 13:22:38 +0200[diff] [blame]30#ifndef CONFIG_SYS_MIPS_CACHE_MODE
31#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
32#endif
33
Shinya Kuribayashidecaba62008-03-25 21:30:07 +0900[diff] [blame]34 /*
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
37 * 64-bit addresses.
38 */
39 .macro setup_c0_status set clr
40 .set push
41 mfc0 t0, CP0_STATUS
42 or t0, ST0_CU0 | \set | 0x1f | \clr
43 xor t0, 0x1f | \clr
44 mtc0 t0, CP0_STATUS
45 .set noreorder
46 sll zero, 3 # ehb
47 .set pop
48 .endm
49
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]50#define RVECENT(f,n) \
51 b f; nop
52#define XVECENT(f,bev) \
53 b f ; \
54 li k0,bev
55
56 .set noreorder
57
58 .globl _start
59 .text
60_start:
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]61 RVECENT(reset,0) # U-boot entry point
62 RVECENT(reset,1) # software reboot
Daniel Schwierzeck7185adb2011-07-27 13:22:37 +0200[diff] [blame]63#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
64 /*
65 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
66 * access external NOR flashes. If the board boots from NOR flash the
67 * internal BootROM does a blind read at address 0xB0000010 to read the
68 * initial configuration for that EBU in order to access the flash
69 * device with correct parameters. This config option is board-specific.
70 */
71 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
72 .word 0x00000000
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]73#else
74 RVECENT(romReserved,2)
75#endif
76 RVECENT(romReserved,3)
77 RVECENT(romReserved,4)
78 RVECENT(romReserved,5)
79 RVECENT(romReserved,6)
80 RVECENT(romReserved,7)
81 RVECENT(romReserved,8)
82 RVECENT(romReserved,9)
83 RVECENT(romReserved,10)
84 RVECENT(romReserved,11)
85 RVECENT(romReserved,12)
86 RVECENT(romReserved,13)
87 RVECENT(romReserved,14)
88 RVECENT(romReserved,15)
89 RVECENT(romReserved,16)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]90 RVECENT(romReserved,17)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]91 RVECENT(romReserved,18)
92 RVECENT(romReserved,19)
93 RVECENT(romReserved,20)
94 RVECENT(romReserved,21)
95 RVECENT(romReserved,22)
96 RVECENT(romReserved,23)
97 RVECENT(romReserved,24)
98 RVECENT(romReserved,25)
99 RVECENT(romReserved,26)
100 RVECENT(romReserved,27)
101 RVECENT(romReserved,28)
102 RVECENT(romReserved,29)
103 RVECENT(romReserved,30)
104 RVECENT(romReserved,31)
105 RVECENT(romReserved,32)
106 RVECENT(romReserved,33)
107 RVECENT(romReserved,34)
108 RVECENT(romReserved,35)
109 RVECENT(romReserved,36)
110 RVECENT(romReserved,37)
111 RVECENT(romReserved,38)
112 RVECENT(romReserved,39)
113 RVECENT(romReserved,40)
114 RVECENT(romReserved,41)
115 RVECENT(romReserved,42)
116 RVECENT(romReserved,43)
117 RVECENT(romReserved,44)
118 RVECENT(romReserved,45)
119 RVECENT(romReserved,46)
120 RVECENT(romReserved,47)
121 RVECENT(romReserved,48)
122 RVECENT(romReserved,49)
123 RVECENT(romReserved,50)
124 RVECENT(romReserved,51)
125 RVECENT(romReserved,52)
126 RVECENT(romReserved,53)
127 RVECENT(romReserved,54)
128 RVECENT(romReserved,55)
129 RVECENT(romReserved,56)
130 RVECENT(romReserved,57)
131 RVECENT(romReserved,58)
132 RVECENT(romReserved,59)
133 RVECENT(romReserved,60)
134 RVECENT(romReserved,61)
135 RVECENT(romReserved,62)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]136 RVECENT(romReserved,63)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]137 XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]138 RVECENT(romReserved,65)
139 RVECENT(romReserved,66)
140 RVECENT(romReserved,67)
141 RVECENT(romReserved,68)
142 RVECENT(romReserved,69)
143 RVECENT(romReserved,70)
144 RVECENT(romReserved,71)
145 RVECENT(romReserved,72)
146 RVECENT(romReserved,73)
147 RVECENT(romReserved,74)
148 RVECENT(romReserved,75)
149 RVECENT(romReserved,76)
150 RVECENT(romReserved,77)
151 RVECENT(romReserved,78)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]152 RVECENT(romReserved,79)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]153 XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]154 RVECENT(romReserved,81)
155 RVECENT(romReserved,82)
156 RVECENT(romReserved,83)
157 RVECENT(romReserved,84)
158 RVECENT(romReserved,85)
159 RVECENT(romReserved,86)
160 RVECENT(romReserved,87)
161 RVECENT(romReserved,88)
162 RVECENT(romReserved,89)
163 RVECENT(romReserved,90)
164 RVECENT(romReserved,91)
165 RVECENT(romReserved,92)
166 RVECENT(romReserved,93)
167 RVECENT(romReserved,94)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]168 RVECENT(romReserved,95)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]169 XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]170 RVECENT(romReserved,97)
171 RVECENT(romReserved,98)
172 RVECENT(romReserved,99)
173 RVECENT(romReserved,100)
174 RVECENT(romReserved,101)
175 RVECENT(romReserved,102)
176 RVECENT(romReserved,103)
177 RVECENT(romReserved,104)
178 RVECENT(romReserved,105)
179 RVECENT(romReserved,106)
180 RVECENT(romReserved,107)
181 RVECENT(romReserved,108)
182 RVECENT(romReserved,109)
183 RVECENT(romReserved,110)
184 RVECENT(romReserved,111)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]185 XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]186 RVECENT(romReserved,113)
187 RVECENT(romReserved,114)
188 RVECENT(romReserved,115)
189 RVECENT(romReserved,116)
190 RVECENT(romReserved,116)
191 RVECENT(romReserved,118)
192 RVECENT(romReserved,119)
193 RVECENT(romReserved,120)
194 RVECENT(romReserved,121)
195 RVECENT(romReserved,122)
196 RVECENT(romReserved,123)
197 RVECENT(romReserved,124)
198 RVECENT(romReserved,125)
199 RVECENT(romReserved,126)
200 RVECENT(romReserved,127)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]201
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]202 /*
203 * We hope there are no more reserved vectors!
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]204 * 128 * 8 == 1024 == 0x400
205 * so this is address R_VEC+0x400 == 0xbfc00400
206 */
207 .align 4
208reset:
209
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]210 /* Clear watch registers */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]211 mtc0 zero, CP0_WATCHLO
212 mtc0 zero, CP0_WATCHHI
213
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]214 /* WP(Watch Pending), SW0/1 should be cleared */
Shinya Kuribayashid43d43e2008-03-25 21:30:07 +0900[diff] [blame]215 mtc0 zero, CP0_CAUSE
216
Daniel Schwierzeck4dc74122013-02-12 22:22:12 +0100[diff] [blame^]217 setup_c0_status 0 0
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]218
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]219 /* Init Timer */
220 mtc0 zero, CP0_COUNT
221 mtc0 zero, CP0_COMPARE
222
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]223#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]224 /* CONFIG0 register */
225 li t0, CONF_CM_UNCACHED
226 mtc0 t0, CP0_CONFIG
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]227#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]228
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]229 /* Initialize $gp */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]230 bal 1f
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]231 nop
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]232 .word _gp
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]2331:
Shinya Kuribayashi16664f72007-11-17 20:05:26 +0900[diff] [blame]234 lw gp, 0(ra)
Wolfgang Denkc75eba32005-12-01 02:15:07 +0100[diff] [blame]235
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]236#ifndef CONFIG_SKIP_LOWLEVEL_INIT
237 /* Initialize any external memory */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]238 la t9, lowlevel_init
239 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]240 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]241
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]242 /* Initialize caches... */
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]243 la t9, mips_cache_reset
244 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]245 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]246
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]247 /* ... and enable them */
Daniel Schwierzeckab2a98b2011-07-27 13:22:38 +0200[diff] [blame]248 li t0, CONFIG_SYS_MIPS_CACHE_MODE
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]249 mtc0 t0, CP0_CONFIG
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]250#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]251
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]252 /* Set up temporary stack */
Gabor Juhosf321b0f2013-01-24 06:27:52 +0000[diff] [blame]253 li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]254
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]255 la t9, board_init_f
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]256 jr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]257 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]258
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]259/*
260 * void relocate_code (addr_sp, gd, addr_moni)
261 *
262 * This "function" does not return, instead it continues in RAM
263 * after relocating the monitor code.
264 *
265 * a0 = addr_sp
266 * a1 = gd
267 * a2 = destination address
268 */
269 .globl relocate_code
270 .ent relocate_code
271relocate_code:
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]272 move sp, a0 # set new stack pointer
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]273
Gabor Juhosb2fe86f2013-01-24 06:27:53 +0000[diff] [blame]274 move s0, a1 # save gd in s0
275 move s2, a2 # save destination address in s2
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]277 li t0, CONFIG_SYS_MONITOR_BASE
Gabor Juhos248fe032013-01-24 06:27:54 +0000[diff] [blame]278 sub s1, s2, t0 # s1 <-- relocation offset
279
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]280 la t3, in_ram
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]281 lw t2, -12(t3) # t2 <-- uboot_end_data
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]282 move t1, a2
283
Gabor Juhos248fe032013-01-24 06:27:54 +0000[diff] [blame]284 add gp, s1 # adjust gp
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]285
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]286 /*
287 * t0 = source address
288 * t1 = target address
289 * t2 = source end address
290 */
2911:
292 lw t3, 0(t0)
293 sw t3, 0(t1)
294 addu t0, 4
Gabor Juhos5b7dd812013-01-24 06:27:51 +0000[diff] [blame]295 blt t0, t2, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]296 addu t1, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]297
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]298 /* If caches were enabled, we would have to flush them here. */
Gabor Juhos67d80c92013-01-24 06:27:55 +0000[diff] [blame]299 sub a1, t1, s2 # a1 <-- size
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]300 la t9, flush_cache
301 jalr t9
Gabor Juhos67d80c92013-01-24 06:27:55 +0000[diff] [blame]302 move a0, s2 # a0 <-- destination address
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]303
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]304 /* Jump to where we've relocated ourselves */
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]305 addi t0, s2, in_ram - _start
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]306 jr t0
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]307 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]308
Vlad Lungu0f8c62a2008-05-05 14:04:00 +0300[diff] [blame]309 .word _GLOBAL_OFFSET_TABLE_
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]310 .word uboot_end_data
311 .word uboot_end
312 .word num_got_entries
313
314in_ram:
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900[diff] [blame]315 /*
316 * Now we want to update GOT.
317 *
318 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
319 * generated by GNU ld. Skip these reserved entries from relocation.
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]320 */
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]321 lw t3, -4(t0) # t3 <-- num_got_entries
322 lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
Gabor Juhos025f2b32013-01-30 04:56:37 +0000[diff] [blame]323 add t4, s1 # t4 now holds relocated _G_O_T_
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]324 addi t4, t4, 8 # skipping first two entries
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]325 li t2, 2
3261:
327 lw t1, 0(t4)
328 beqz t1, 2f
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]329 add t1, s1
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]330 sw t1, 0(t4)
3312:
332 addi t2, 1
333 blt t2, t3, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]334 addi t4, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]335
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]336 /* Clear BSS */
337 lw t1, -12(t0) # t1 <-- uboot_end_data
338 lw t2, -8(t0) # t2 <-- uboot_end
339 add t1, s1 # adjust pointers
Stefan Roese71fa0712008-11-18 16:36:12 +0100[diff] [blame]340 add t2, s1
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]341
342 sub t1, 4
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]3431:
344 addi t1, 4
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]345 bltl t1, t2, 1b
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]346 sw zero, 0(t1)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]347
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]348 move a0, s0 # a0 <-- gd
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]349 la t9, board_init_r
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900[diff] [blame]350 jr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]351 move a1, s2
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]352
353 .end relocate_code
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]354
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900[diff] [blame]355 /* Exception handlers */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]356romReserved:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]357 b romReserved
Gabor Juhos14fdd1a2013-01-16 03:05:01 +0000[diff] [blame]358 nop
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]359
360romExcHandle:
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900[diff] [blame]361 b romExcHandle
Gabor Juhos14fdd1a2013-01-16 03:05:01 +0000[diff] [blame]362 nop