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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000010 */
11
Andy Fleming75b9d4a2008-08-31 16:33:26 -050012#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000013#include <common.h>
14#include <watchdog.h>
15#include <command.h>
Andy Fleming80522dc2008-10-30 16:51:33 -050016#include <fsl_esdhc.h>
wdenk42d1f032003-10-15 23:53:47 +000017#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020018#include <asm/io.h>
Becky Bruce199e2622010-06-17 11:37:25 -050019#include <asm/mmu.h>
York Sun0b665132013-10-22 12:39:02 -070020#include <fsl_ifc.h>
Becky Bruce199e2622010-06-17 11:37:25 -050021#include <asm/fsl_law.h>
Becky Bruce38dba0c2010-12-17 17:17:56 -060022#include <asm/fsl_lbc.h>
York Sunebbe11d2010-09-28 15:20:33 -070023#include <post.h>
24#include <asm/processor.h>
York Sun5614e712013-09-30 09:22:09 -070025#include <fsl_ddr_sdram.h>
wdenk42d1f032003-10-15 23:53:47 +000026
James Yang591933c2008-02-08 16:44:53 -060027DECLARE_GLOBAL_DATA_PTR;
28
Ira W. Snyderc18de0d2011-11-21 13:20:32 -080029/*
30 * Default board reset function
31 */
32static void
33__board_reset(void)
34{
35 /* Do nothing */
36}
37void board_reset(void) __attribute__((weak, alias("__board_reset")));
38
wdenk42d1f032003-10-15 23:53:47 +000039int checkcpu (void)
40{
wdenk97d80fc2004-06-09 00:34:46 +000041 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000042 uint pvr, svr;
43 uint ver;
44 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050045 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020046 char buf1[32], buf2[32];
York Sunf165bc32013-06-25 11:37:43 -070047#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 ccsr_gur_t __iomem *gur =
49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50#endif
York Sun98ffa192012-10-08 07:44:31 +000051
52 /*
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
56 */
57#ifdef CONFIG_FSL_CORENET
58#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
60#else
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64#else /* CONFIG_FSL_CORENET */
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080065#ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
68#else
Kumar Galaee1e35b2008-05-29 01:21:24 -050069 u32 ddr_ratio = 0;
Kumar Gala39aaca12009-03-19 02:46:19 -050070#endif /* CONFIG_DDR_CLK_FREQ */
York Sun98ffa192012-10-08 07:44:31 +000071#endif /* CONFIG_FSL_CORENET */
72
Timur Tabifbb9ecf2011-08-05 16:15:24 -050073 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
wdenk42d1f032003-10-15 23:53:47 +000075
wdenk97d80fc2004-06-09 00:34:46 +000076 svr = get_svr();
wdenk97d80fc2004-06-09 00:34:46 +000077 major = SVR_MAJ(svr);
78 minor = SVR_MIN(svr);
79
Shengzhou Liu5122dfa2014-04-25 16:31:22 +080080#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
81 if (SVR_SOC_VER(svr) == SVR_T4080) {
82 ccsr_rcpm_t *rcpm =
83 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
84
85 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
86 FSL_CORENET_DEVDISR2_DTSEC1_9);
87 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
88 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
89
90 /* It needs SW to disable core4~7 as HW design sake on T4080 */
91 for (i = 4; i < 8; i++)
92 cpu_disable(i);
93
94 /* request core4~7 into PH20 state, prior to entering PCL10
95 * state, all cores in cluster should be placed in PH20 state.
96 */
97 setbits_be32(&rcpm->pcph20setr, 0xf0);
98
99 /* put the 2nd cluster into PCL10 state */
100 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
101 }
102#endif
103
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530104 if (cpu_numcores() > 1) {
Poonam Aggrwal21170c82009-09-03 19:42:40 +0530105#ifndef CONFIG_MP
106 puts("Unicore software on multiprocessor system!!\n"
107 "To enable mutlticore build define CONFIG_MP\n");
108#endif
Kim Phillips680c6132010-08-09 18:39:57 -0500109 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530110 printf("CPU%d: ", pic->whoami);
111 } else {
112 puts("CPU: ");
113 }
Andy Fleming1ced1212008-02-06 01:19:40 -0600114
Simon Glass67ac13b2012-12-13 20:48:48 +0000115 cpu = gd->arch.cpu;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530116
Poonam Aggrwal58442dc2009-09-02 13:35:21 +0530117 puts(cpu->name);
118 if (IS_E_PROCESSOR(svr))
119 puts("E");
Andy Fleming1ced1212008-02-06 01:19:40 -0600120
wdenk97d80fc2004-06-09 00:34:46 +0000121 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +0000122
wdenk6c9e7892005-03-15 22:56:53 +0000123 pvr = get_pvr();
124 ver = PVR_VER(pvr);
125 major = PVR_MAJ(pvr);
126 minor = PVR_MIN(pvr);
127
128 printf("Core: ");
Kumar Gala89927382011-07-25 09:28:39 -0500129 switch(ver) {
130 case PVR_VER_E500_V1:
131 case PVR_VER_E500_V2:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300132 puts("e500");
Kumar Gala89927382011-07-25 09:28:39 -0500133 break;
134 case PVR_VER_E500MC:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300135 puts("e500mc");
Kumar Gala89927382011-07-25 09:28:39 -0500136 break;
137 case PVR_VER_E5500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300138 puts("e5500");
Kumar Gala89927382011-07-25 09:28:39 -0500139 break;
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000140 case PVR_VER_E6500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300141 puts("e6500");
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000142 break;
Kumar Gala89927382011-07-25 09:28:39 -0500143 default:
Kumar Gala2a3a96c2009-10-21 13:23:54 -0500144 puts("Unknown");
Kumar Gala89927382011-07-25 09:28:39 -0500145 break;
wdenk6c9e7892005-03-15 22:56:53 +0000146 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500147
wdenk6c9e7892005-03-15 22:56:53 +0000148 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
149
York Sun2f1712b2012-10-08 07:44:10 +0000150 if (nr_cores > CONFIG_MAX_CPUS) {
151 panic("\nUnexpected number of cores: %d, max is %d\n",
152 nr_cores, CONFIG_MAX_CPUS);
153 }
154
wdenk97d80fc2004-06-09 00:34:46 +0000155 get_sys_info(&sysinfo);
156
vijay rai0c12a152014-04-15 11:34:12 +0530157#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
158 if (sysinfo.diff_sysclk == 1)
159 puts("Single Source Clock Configuration\n");
160#endif
161
Kumar Galab29dee32009-02-04 09:35:57 -0600162 puts("Clock Configuration:");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500163 for_each_cpu(i, core, nr_cores, mask) {
Wolfgang Denk1bba30e2009-02-19 00:41:08 +0100164 if (!(i & 3))
165 printf ("\n ");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500166 printf("CPU%d:%-4s MHz, ", core,
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530167 strmhz(buf1, sysinfo.freq_processor[core]));
Kumar Galab29dee32009-02-04 09:35:57 -0600168 }
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530169 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
170 printf("\n");
Kumar Galaee1e35b2008-05-29 01:21:24 -0500171
Kumar Gala39aaca12009-03-19 02:46:19 -0500172#ifdef CONFIG_FSL_CORENET
173 if (ddr_sync == 1) {
174 printf(" DDR:%-4s MHz (%s MT/s data rate) "
175 "(Synchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530176 strmhz(buf1, sysinfo.freq_ddrbus/2),
177 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500178 } else {
179 printf(" DDR:%-4s MHz (%s MT/s data rate) "
180 "(Asynchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530181 strmhz(buf1, sysinfo.freq_ddrbus/2),
182 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500183 }
184#else
Kumar Galad4357932007-12-07 04:59:26 -0600185 switch (ddr_ratio) {
186 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200187 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530188 strmhz(buf1, sysinfo.freq_ddrbus/2),
189 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600190 break;
191 case 0x7:
Kumar Gala39aaca12009-03-19 02:46:19 -0500192 printf(" DDR:%-4s MHz (%s MT/s data rate) "
193 "(Synchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530194 strmhz(buf1, sysinfo.freq_ddrbus/2),
195 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600196 break;
197 default:
Kumar Gala39aaca12009-03-19 02:46:19 -0500198 printf(" DDR:%-4s MHz (%s MT/s data rate) "
199 "(Asynchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530200 strmhz(buf1, sysinfo.freq_ddrbus/2),
201 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600202 break;
203 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500204#endif
wdenk97d80fc2004-06-09 00:34:46 +0000205
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530206#if defined(CONFIG_FSL_LBC)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530207 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
208 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500209 } else {
Trent Piephoada591d2008-12-03 15:16:37 -0800210 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530211 sysinfo.freq_localbus);
Kumar Gala39aaca12009-03-19 02:46:19 -0500212 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530213#endif
wdenk97d80fc2004-06-09 00:34:46 +0000214
Kumar Gala800c73c2012-10-08 07:44:06 +0000215#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530216 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala800c73c2012-10-08 07:44:06 +0000217#endif
218
Andy Fleming1ced1212008-02-06 01:19:40 -0600219#ifdef CONFIG_CPM2
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530220 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600221#endif
wdenk97d80fc2004-06-09 00:34:46 +0000222
Haiying Wangb3d7f202009-05-20 12:30:29 -0400223#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530224 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
Haiying Wangb3d7f202009-05-20 12:30:29 -0400225#endif
226
Kumar Gala39aaca12009-03-19 02:46:19 -0500227#ifdef CONFIG_SYS_DPAA_FMAN
228 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
Emil Medve7eda1f82010-06-17 00:08:29 -0500229 printf(" FMAN%d: %s MHz\n", i + 1,
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530230 strmhz(buf1, sysinfo.freq_fman[i]));
Kumar Gala39aaca12009-03-19 02:46:19 -0500231 }
232#endif
233
Haiying Wang990e1a82012-10-11 07:13:39 +0000234#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530235 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
Haiying Wang990e1a82012-10-11 07:13:39 +0000236#endif
237
Kumar Gala39aaca12009-03-19 02:46:19 -0500238#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530239 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
Kumar Gala39aaca12009-03-19 02:46:19 -0500240#endif
241
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500242 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000243
York Sunf165bc32013-06-25 11:37:43 -0700244#ifdef CONFIG_FSL_CORENET
245 /* Display the RCW, so that no one gets confused as to what RCW
246 * we're actually using for this boot.
247 */
248 puts("Reset Configuration Word (RCW):");
249 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
250 u32 rcw = in_be32(&gur->rcwsr[i]);
251
252 if ((i % 4) == 0)
253 printf("\n %08x:", i * 4);
254 printf(" %08x", rcw);
255 }
256 puts("\n");
257#endif
258
wdenk42d1f032003-10-15 23:53:47 +0000259 return 0;
260}
261
262
263/* ------------------------------------------------------------------------- */
264
Mike Frysinger882b7d72010-10-20 03:41:17 -0400265int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk42d1f032003-10-15 23:53:47 +0000266{
Kumar Galac3483222009-09-08 13:46:46 -0500267/* Everything after the first generation of PQ3 parts has RSTCR */
268#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
269 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
Sergei Poselenov793670c2008-05-08 14:17:08 +0200270 unsigned long val, msr;
271
wdenk42d1f032003-10-15 23:53:47 +0000272 /*
273 * Initiate hard reset in debug control register DBCR0
Kumar Galac3483222009-09-08 13:46:46 -0500274 * Make sure MSR[DE] = 1. This only resets the core.
wdenk42d1f032003-10-15 23:53:47 +0000275 */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200276 msr = mfmsr ();
277 msr |= MSR_DE;
278 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400279
Sergei Poselenov793670c2008-05-08 14:17:08 +0200280 val = mfspr(DBCR0);
281 val |= 0x70000000;
282 mtspr(DBCR0,val);
Kumar Galac3483222009-09-08 13:46:46 -0500283#else
284 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Ira W. Snyderc18de0d2011-11-21 13:20:32 -0800285
286 /* Attempt board-specific reset */
287 board_reset();
288
289 /* Next try asserting HRESET_REQ */
290 out_be32(&gur->rstcr, 0x2);
Kumar Galac3483222009-09-08 13:46:46 -0500291 udelay(100);
292#endif
Sergei Poselenov793670c2008-05-08 14:17:08 +0200293
wdenk42d1f032003-10-15 23:53:47 +0000294 return 1;
295}
296
297
298/*
299 * Get timebase clock frequency
300 */
Kumar Gala66412c62011-02-18 05:40:54 -0600301#ifndef CONFIG_SYS_FSL_TBCLK_DIV
302#define CONFIG_SYS_FSL_TBCLK_DIV 8
303#endif
Alexander Graffa08d392014-04-11 17:09:45 +0200304__weak unsigned long get_tbclk (void)
wdenk42d1f032003-10-15 23:53:47 +0000305{
Kumar Gala66412c62011-02-18 05:40:54 -0600306 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
307
308 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
wdenk42d1f032003-10-15 23:53:47 +0000309}
310
311
312#if defined(CONFIG_WATCHDOG)
313void
wdenk42d1f032003-10-15 23:53:47 +0000314reset_85xx_watchdog(void)
315{
316 /*
317 * Clear TSR(WIS) bit by writing 1
318 */
Mark Marshall320d53d2012-09-09 23:06:03 +0000319 mtspr(SPRN_TSR, TSR_WIS);
wdenk42d1f032003-10-15 23:53:47 +0000320}
Horst Kronstorferdf616ca2013-03-13 10:14:05 +0000321
322void
323watchdog_reset(void)
324{
325 int re_enable = disable_interrupts();
326
327 reset_85xx_watchdog();
328 if (re_enable)
329 enable_interrupts();
330}
wdenk42d1f032003-10-15 23:53:47 +0000331#endif /* CONFIG_WATCHDOG */
332
Sergei Poselenov740280e2008-06-06 15:42:40 +0200333/*
Andy Fleming80522dc2008-10-30 16:51:33 -0500334 * Initializes on-chip MMC controllers.
335 * to override, implement board_mmc_init()
336 */
337int cpu_mmc_init(bd_t *bis)
338{
339#ifdef CONFIG_FSL_ESDHC
340 return fsl_esdhc_mmc_init(bis);
341#else
342 return 0;
343#endif
344}
Becky Bruce199e2622010-06-17 11:37:25 -0500345
346/*
347 * Print out the state of various machine registers.
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530348 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
349 * parameters for IFC and TLBs
Becky Bruce199e2622010-06-17 11:37:25 -0500350 */
351void mpc85xx_reginfo(void)
352{
353 print_tlbcam();
354 print_laws();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530355#if defined(CONFIG_FSL_LBC)
Becky Bruce199e2622010-06-17 11:37:25 -0500356 print_lbc_regs();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530357#endif
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530358#ifdef CONFIG_FSL_IFC
359 print_ifc_regs();
360#endif
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530361
Becky Bruce199e2622010-06-17 11:37:25 -0500362}
York Sunebbe11d2010-09-28 15:20:33 -0700363
Becky Bruce38dba0c2010-12-17 17:17:56 -0600364/* Common ddr init for non-corenet fsl 85xx platforms */
365#ifndef CONFIG_FSL_CORENET
Scott Woodc97cd1b2012-09-20 19:02:18 -0500366#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
367 !defined(CONFIG_SYS_INIT_L2_ADDR)
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800368phys_size_t initdram(int board_type)
369{
Alexander Graffa08d392014-04-11 17:09:45 +0200370#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
371 defined(CONFIG_QEMU_E500)
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800372 return fsl_ddr_sdram_size();
373#else
Mingkai Hu76d354f2013-04-12 15:56:28 +0800374 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800375#endif
376}
377#else /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600378phys_size_t initdram(int board_type)
379{
380 phys_size_t dram_size = 0;
381
Becky Bruce810c4422010-12-17 17:17:58 -0600382#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600383 {
384 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
385 unsigned int x = 10;
386 unsigned int i;
387
388 /*
389 * Work around to stabilize DDR DLL
390 */
391 out_be32(&gur->ddrdllcr, 0x81000000);
392 asm("sync;isync;msync");
393 udelay(200);
394 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
395 setbits_be32(&gur->devdisr, 0x00010000);
396 for (i = 0; i < x; i++)
397 ;
398 clrbits_be32(&gur->devdisr, 0x00010000);
399 x++;
400 }
401 }
402#endif
403
York Sun1b3e3c42011-06-07 09:42:16 +0800404#if defined(CONFIG_SPD_EEPROM) || \
405 defined(CONFIG_DDR_SPD) || \
406 defined(CONFIG_SYS_DDR_RAW_TIMING)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600407 dram_size = fsl_ddr_sdram();
408#else
409 dram_size = fixed_sdram();
410#endif
411 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
412 dram_size *= 0x100000;
413
414#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
415 /*
416 * Initialize and enable DDR ECC.
417 */
418 ddr_enable_ecc(dram_size);
419#endif
420
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530421#if defined(CONFIG_FSL_LBC)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600422 /* Some boards also have sdram on the lbc */
Becky Bruce70961ba2010-12-17 17:17:57 -0600423 lbc_sdram_init();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530424#endif
Becky Bruce38dba0c2010-12-17 17:17:56 -0600425
Wolfgang Denk21cd5812011-07-25 10:13:53 +0200426 debug("DDR: ");
Becky Bruce38dba0c2010-12-17 17:17:56 -0600427 return dram_size;
428}
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800429#endif /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600430#endif
431
York Sunebbe11d2010-09-28 15:20:33 -0700432#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
433
434/* Board-specific functions defined in each board's ddr.c */
435void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
436 unsigned int ctrl_num);
437void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
438 phys_addr_t *rpn);
439unsigned int
440 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
441
Becky Bruce9cdfe282011-07-18 18:49:15 -0500442void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
443
York Sunebbe11d2010-09-28 15:20:33 -0700444static void dump_spd_ddr_reg(void)
445{
446 int i, j, k, m;
447 u8 *p_8;
448 u32 *p_32;
York Sun9a17eb52013-11-18 10:29:32 -0800449 struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
York Sunebbe11d2010-09-28 15:20:33 -0700450 generic_spd_eeprom_t
451 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
452
453 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
454 fsl_ddr_get_spd(spd[i], i);
455
456 puts("SPD data of all dimms (zero vaule is omitted)...\n");
457 puts("Byte (hex) ");
458 k = 1;
459 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
460 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
461 printf("Dimm%d ", k++);
462 }
463 puts("\n");
464 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
465 m = 0;
466 printf("%3d (0x%02x) ", k, k);
467 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
468 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
469 p_8 = (u8 *) &spd[i][j];
470 if (p_8[k]) {
471 printf("0x%02x ", p_8[k]);
472 m++;
473 } else
474 puts(" ");
475 }
476 }
477 if (m)
478 puts("\n");
479 else
480 puts("\r");
481 }
482
483 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
484 switch (i) {
485 case 0:
York Sun5614e712013-09-30 09:22:09 -0700486 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700487 break;
York Sun5614e712013-09-30 09:22:09 -0700488#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
York Sunebbe11d2010-09-28 15:20:33 -0700489 case 1:
York Sun5614e712013-09-30 09:22:09 -0700490 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700491 break;
492#endif
York Sun5614e712013-09-30 09:22:09 -0700493#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
York Suna4c66502012-08-17 08:22:39 +0000494 case 2:
York Sun5614e712013-09-30 09:22:09 -0700495 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000496 break;
497#endif
York Sun5614e712013-09-30 09:22:09 -0700498#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
York Suna4c66502012-08-17 08:22:39 +0000499 case 3:
York Sun5614e712013-09-30 09:22:09 -0700500 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000501 break;
502#endif
York Sunebbe11d2010-09-28 15:20:33 -0700503 default:
504 printf("%s unexpected controller number = %u\n",
505 __func__, i);
506 return;
507 }
508 }
509 printf("DDR registers dump for all controllers "
510 "(zero vaule is omitted)...\n");
511 puts("Offset (hex) ");
512 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
513 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
514 puts("\n");
York Sun9a17eb52013-11-18 10:29:32 -0800515 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
York Sunebbe11d2010-09-28 15:20:33 -0700516 m = 0;
517 printf("%6d (0x%04x)", k * 4, k * 4);
518 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
519 p_32 = (u32 *) ddr[i];
520 if (p_32[k]) {
521 printf(" 0x%08x", p_32[k]);
522 m++;
523 } else
524 puts(" ");
525 }
526 if (m)
527 puts("\n");
528 else
529 puts("\r");
530 }
531 puts("\n");
532}
533
534/* invalid the TLBs for DDR and setup new ones to cover p_addr */
535static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
536{
537 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
538 unsigned long epn;
539 u32 tsize, valid, ptr;
York Sunebbe11d2010-09-28 15:20:33 -0700540 int ddr_esel;
541
Becky Bruce9cdfe282011-07-18 18:49:15 -0500542 clear_ddr_tlbs_phys(p_addr, size>>20);
York Sunebbe11d2010-09-28 15:20:33 -0700543
544 /* Setup new tlb to cover the physical address */
545 setup_ddr_tlbs_phys(p_addr, size>>20);
546
547 ptr = vstart;
548 ddr_esel = find_tlb_idx((void *)ptr, 1);
549 if (ddr_esel != -1) {
550 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
551 } else {
552 printf("TLB error in function %s\n", __func__);
553 return -1;
554 }
555
556 return 0;
557}
558
559/*
560 * slide the testing window up to test another area
561 * for 32_bit system, the maximum testable memory is limited to
562 * CONFIG_MAX_MEM_MAPPED
563 */
564int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
565{
566 phys_addr_t test_cap, p_addr;
567 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
568
569#if !defined(CONFIG_PHYS_64BIT) || \
570 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
571 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
572 test_cap = p_size;
573#else
574 test_cap = gd->ram_size;
575#endif
576 p_addr = (*vstart) + (*size) + (*phys_offset);
577 if (p_addr < test_cap - 1) {
578 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
579 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
580 return -1;
581 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
582 *size = (u32) p_size;
583 printf("Testing 0x%08llx - 0x%08llx\n",
584 (u64)(*vstart) + (*phys_offset),
585 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
586 } else
587 return 1;
588
589 return 0;
590}
591
592/* initialization for testing area */
593int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
594{
595 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
596
597 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
598 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
599 *phys_offset = 0;
600
601#if !defined(CONFIG_PHYS_64BIT) || \
602 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
603 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
604 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
605 puts("Cannot test more than ");
606 print_size(CONFIG_MAX_MEM_MAPPED,
607 " without proper 36BIT support.\n");
608 }
609#endif
610 printf("Testing 0x%08llx - 0x%08llx\n",
611 (u64)(*vstart) + (*phys_offset),
612 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
613
614 return 0;
615}
616
617/* invalid TLBs for DDR and remap as normal after testing */
618int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
619{
620 unsigned long epn;
621 u32 tsize, valid, ptr;
622 phys_addr_t rpn = 0;
623 int ddr_esel;
624
625 /* disable the TLBs for this testing */
626 ptr = *vstart;
627
628 while (ptr < (*vstart) + (*size)) {
629 ddr_esel = find_tlb_idx((void *)ptr, 1);
630 if (ddr_esel != -1) {
631 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
632 disable_tlb(ddr_esel);
633 }
634 ptr += TSIZE_TO_BYTES(tsize);
635 }
636
637 puts("Remap DDR ");
638 setup_ddr_tlbs(gd->ram_size>>20);
639 puts("\n");
640
641 return 0;
642}
643
644void arch_memory_failure_handle(void)
645{
646 dump_spd_ddr_reg();
647}
648#endif