wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 2 | * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 4 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * (C) Copyright 2000 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 12 | #include <config.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 13 | #include <common.h> |
| 14 | #include <watchdog.h> |
| 15 | #include <command.h> |
Andy Fleming | 80522dc | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 16 | #include <fsl_esdhc.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 17 | #include <asm/cache.h> |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 18 | #include <asm/io.h> |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 19 | #include <asm/mmu.h> |
York Sun | 0b66513 | 2013-10-22 12:39:02 -0700 | [diff] [blame] | 20 | #include <fsl_ifc.h> |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 21 | #include <asm/fsl_law.h> |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 22 | #include <asm/fsl_lbc.h> |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 23 | #include <post.h> |
| 24 | #include <asm/processor.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 25 | #include <fsl_ddr_sdram.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 26 | |
James Yang | 591933c | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Ira W. Snyder | c18de0d | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 29 | /* |
| 30 | * Default board reset function |
| 31 | */ |
| 32 | static void |
| 33 | __board_reset(void) |
| 34 | { |
| 35 | /* Do nothing */ |
| 36 | } |
| 37 | void board_reset(void) __attribute__((weak, alias("__board_reset"))); |
| 38 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 39 | int checkcpu (void) |
| 40 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 41 | sys_info_t sysinfo; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 42 | uint pvr, svr; |
| 43 | uint ver; |
| 44 | uint major, minor; |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 45 | struct cpu_type *cpu; |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 46 | char buf1[32], buf2[32]; |
York Sun | f165bc3 | 2013-06-25 11:37:43 -0700 | [diff] [blame] | 47 | #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) |
| 48 | ccsr_gur_t __iomem *gur = |
| 49 | (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 50 | #endif |
York Sun | 98ffa19 | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 51 | |
| 52 | /* |
| 53 | * Cornet platforms use ddr sync bit in RCW to indicate sync vs async |
| 54 | * mode. Previous platform use ddr ratio to do the same. This |
| 55 | * information is only for display here. |
| 56 | */ |
| 57 | #ifdef CONFIG_FSL_CORENET |
| 58 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
| 59 | u32 ddr_sync = 0; /* only async mode is supported */ |
| 60 | #else |
| 61 | u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) |
| 62 | >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; |
| 63 | #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ |
| 64 | #else /* CONFIG_FSL_CORENET */ |
Srikanth Srinivasan | ab48ca1 | 2010-02-10 17:32:43 +0800 | [diff] [blame] | 65 | #ifdef CONFIG_DDR_CLK_FREQ |
| 66 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
| 67 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; |
| 68 | #else |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 69 | u32 ddr_ratio = 0; |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 70 | #endif /* CONFIG_DDR_CLK_FREQ */ |
York Sun | 98ffa19 | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 71 | #endif /* CONFIG_FSL_CORENET */ |
| 72 | |
Timur Tabi | fbb9ecf | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 73 | unsigned int i, core, nr_cores = cpu_numcores(); |
| 74 | u32 mask = cpu_mask(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 75 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 76 | svr = get_svr(); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 77 | major = SVR_MAJ(svr); |
| 78 | minor = SVR_MIN(svr); |
| 79 | |
Shengzhou Liu | 5122dfa | 2014-04-25 16:31:22 +0800 | [diff] [blame^] | 80 | #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
| 81 | if (SVR_SOC_VER(svr) == SVR_T4080) { |
| 82 | ccsr_rcpm_t *rcpm = |
| 83 | (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); |
| 84 | |
| 85 | setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || |
| 86 | FSL_CORENET_DEVDISR2_DTSEC1_9); |
| 87 | setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); |
| 88 | setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); |
| 89 | |
| 90 | /* It needs SW to disable core4~7 as HW design sake on T4080 */ |
| 91 | for (i = 4; i < 8; i++) |
| 92 | cpu_disable(i); |
| 93 | |
| 94 | /* request core4~7 into PH20 state, prior to entering PCL10 |
| 95 | * state, all cores in cluster should be placed in PH20 state. |
| 96 | */ |
| 97 | setbits_be32(&rcpm->pcph20setr, 0xf0); |
| 98 | |
| 99 | /* put the 2nd cluster into PCL10 state */ |
| 100 | setbits_be32(&rcpm->clpcl10setr, 1 << 1); |
| 101 | } |
| 102 | #endif |
| 103 | |
Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 104 | if (cpu_numcores() > 1) { |
Poonam Aggrwal | 21170c8 | 2009-09-03 19:42:40 +0530 | [diff] [blame] | 105 | #ifndef CONFIG_MP |
| 106 | puts("Unicore software on multiprocessor system!!\n" |
| 107 | "To enable mutlticore build define CONFIG_MP\n"); |
| 108 | #endif |
Kim Phillips | 680c613 | 2010-08-09 18:39:57 -0500 | [diff] [blame] | 109 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); |
Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 110 | printf("CPU%d: ", pic->whoami); |
| 111 | } else { |
| 112 | puts("CPU: "); |
| 113 | } |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 114 | |
Simon Glass | 67ac13b | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 115 | cpu = gd->arch.cpu; |
Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 116 | |
Poonam Aggrwal | 58442dc | 2009-09-02 13:35:21 +0530 | [diff] [blame] | 117 | puts(cpu->name); |
| 118 | if (IS_E_PROCESSOR(svr)) |
| 119 | puts("E"); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 120 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 121 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 122 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 123 | pvr = get_pvr(); |
| 124 | ver = PVR_VER(pvr); |
| 125 | major = PVR_MAJ(pvr); |
| 126 | minor = PVR_MIN(pvr); |
| 127 | |
| 128 | printf("Core: "); |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 129 | switch(ver) { |
| 130 | case PVR_VER_E500_V1: |
| 131 | case PVR_VER_E500_V2: |
Fabio Estevam | 6770c5e | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 132 | puts("e500"); |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 133 | break; |
| 134 | case PVR_VER_E500MC: |
Fabio Estevam | 6770c5e | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 135 | puts("e500mc"); |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 136 | break; |
| 137 | case PVR_VER_E5500: |
Fabio Estevam | 6770c5e | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 138 | puts("e5500"); |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 139 | break; |
Kumar Gala | 5b6b85a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 140 | case PVR_VER_E6500: |
Fabio Estevam | 6770c5e | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 141 | puts("e6500"); |
Kumar Gala | 5b6b85a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 142 | break; |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 143 | default: |
Kumar Gala | 2a3a96c | 2009-10-21 13:23:54 -0500 | [diff] [blame] | 144 | puts("Unknown"); |
Kumar Gala | 8992738 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 145 | break; |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 146 | } |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 147 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 148 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 149 | |
York Sun | 2f1712b | 2012-10-08 07:44:10 +0000 | [diff] [blame] | 150 | if (nr_cores > CONFIG_MAX_CPUS) { |
| 151 | panic("\nUnexpected number of cores: %d, max is %d\n", |
| 152 | nr_cores, CONFIG_MAX_CPUS); |
| 153 | } |
| 154 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 155 | get_sys_info(&sysinfo); |
| 156 | |
vijay rai | 0c12a15 | 2014-04-15 11:34:12 +0530 | [diff] [blame] | 157 | #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
| 158 | if (sysinfo.diff_sysclk == 1) |
| 159 | puts("Single Source Clock Configuration\n"); |
| 160 | #endif |
| 161 | |
Kumar Gala | b29dee3 | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 162 | puts("Clock Configuration:"); |
Timur Tabi | fbb9ecf | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 163 | for_each_cpu(i, core, nr_cores, mask) { |
Wolfgang Denk | 1bba30e | 2009-02-19 00:41:08 +0100 | [diff] [blame] | 164 | if (!(i & 3)) |
| 165 | printf ("\n "); |
Timur Tabi | fbb9ecf | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 166 | printf("CPU%d:%-4s MHz, ", core, |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 167 | strmhz(buf1, sysinfo.freq_processor[core])); |
Kumar Gala | b29dee3 | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 168 | } |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 169 | printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); |
| 170 | printf("\n"); |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 171 | |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 172 | #ifdef CONFIG_FSL_CORENET |
| 173 | if (ddr_sync == 1) { |
| 174 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 175 | "(Synchronous), ", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 176 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 177 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 178 | } else { |
| 179 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 180 | "(Asynchronous), ", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 181 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 182 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 183 | } |
| 184 | #else |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 185 | switch (ddr_ratio) { |
| 186 | case 0x0: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 187 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 188 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 189 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 190 | break; |
| 191 | case 0x7: |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 192 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 193 | "(Synchronous), ", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 194 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 195 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 196 | break; |
| 197 | default: |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 198 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 199 | "(Asynchronous), ", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 200 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 201 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 202 | break; |
| 203 | } |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 204 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 205 | |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 206 | #if defined(CONFIG_FSL_LBC) |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 207 | if (sysinfo.freq_localbus > LCRR_CLKDIV) { |
| 208 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 209 | } else { |
Trent Piepho | ada591d | 2008-12-03 15:16:37 -0800 | [diff] [blame] | 210 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 211 | sysinfo.freq_localbus); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 212 | } |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 213 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 214 | |
Kumar Gala | 800c73c | 2012-10-08 07:44:06 +0000 | [diff] [blame] | 215 | #if defined(CONFIG_FSL_IFC) |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 216 | printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); |
Kumar Gala | 800c73c | 2012-10-08 07:44:06 +0000 | [diff] [blame] | 217 | #endif |
| 218 | |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 219 | #ifdef CONFIG_CPM2 |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 220 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 221 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 222 | |
Haiying Wang | b3d7f20 | 2009-05-20 12:30:29 -0400 | [diff] [blame] | 223 | #ifdef CONFIG_QE |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 224 | printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); |
Haiying Wang | b3d7f20 | 2009-05-20 12:30:29 -0400 | [diff] [blame] | 225 | #endif |
| 226 | |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 227 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 228 | for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { |
Emil Medve | 7eda1f8 | 2010-06-17 00:08:29 -0500 | [diff] [blame] | 229 | printf(" FMAN%d: %s MHz\n", i + 1, |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 230 | strmhz(buf1, sysinfo.freq_fman[i])); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 231 | } |
| 232 | #endif |
| 233 | |
Haiying Wang | 990e1a8 | 2012-10-11 07:13:39 +0000 | [diff] [blame] | 234 | #ifdef CONFIG_SYS_DPAA_QBMAN |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 235 | printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); |
Haiying Wang | 990e1a8 | 2012-10-11 07:13:39 +0000 | [diff] [blame] | 236 | #endif |
| 237 | |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 238 | #ifdef CONFIG_SYS_DPAA_PME |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 239 | printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); |
Kumar Gala | 39aaca1 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 240 | #endif |
| 241 | |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 242 | puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 243 | |
York Sun | f165bc3 | 2013-06-25 11:37:43 -0700 | [diff] [blame] | 244 | #ifdef CONFIG_FSL_CORENET |
| 245 | /* Display the RCW, so that no one gets confused as to what RCW |
| 246 | * we're actually using for this boot. |
| 247 | */ |
| 248 | puts("Reset Configuration Word (RCW):"); |
| 249 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { |
| 250 | u32 rcw = in_be32(&gur->rcwsr[i]); |
| 251 | |
| 252 | if ((i % 4) == 0) |
| 253 | printf("\n %08x:", i * 4); |
| 254 | printf(" %08x", rcw); |
| 255 | } |
| 256 | puts("\n"); |
| 257 | #endif |
| 258 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | |
| 263 | /* ------------------------------------------------------------------------- */ |
| 264 | |
Mike Frysinger | 882b7d7 | 2010-10-20 03:41:17 -0400 | [diff] [blame] | 265 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 266 | { |
Kumar Gala | c348322 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 267 | /* Everything after the first generation of PQ3 parts has RSTCR */ |
| 268 | #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ |
| 269 | defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 270 | unsigned long val, msr; |
| 271 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 272 | /* |
| 273 | * Initiate hard reset in debug control register DBCR0 |
Kumar Gala | c348322 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 274 | * Make sure MSR[DE] = 1. This only resets the core. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 275 | */ |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 276 | msr = mfmsr (); |
| 277 | msr |= MSR_DE; |
| 278 | mtmsr (msr); |
urwithsughosh@gmail.com | df90968 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 279 | |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 280 | val = mfspr(DBCR0); |
| 281 | val |= 0x70000000; |
| 282 | mtspr(DBCR0,val); |
Kumar Gala | c348322 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 283 | #else |
| 284 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Ira W. Snyder | c18de0d | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 285 | |
| 286 | /* Attempt board-specific reset */ |
| 287 | board_reset(); |
| 288 | |
| 289 | /* Next try asserting HRESET_REQ */ |
| 290 | out_be32(&gur->rstcr, 0x2); |
Kumar Gala | c348322 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 291 | udelay(100); |
| 292 | #endif |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 293 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 294 | return 1; |
| 295 | } |
| 296 | |
| 297 | |
| 298 | /* |
| 299 | * Get timebase clock frequency |
| 300 | */ |
Kumar Gala | 66412c6 | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 301 | #ifndef CONFIG_SYS_FSL_TBCLK_DIV |
| 302 | #define CONFIG_SYS_FSL_TBCLK_DIV 8 |
| 303 | #endif |
Alexander Graf | fa08d39 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 304 | __weak unsigned long get_tbclk (void) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 305 | { |
Kumar Gala | 66412c6 | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 306 | unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; |
| 307 | |
| 308 | return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | |
| 312 | #if defined(CONFIG_WATCHDOG) |
| 313 | void |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 314 | reset_85xx_watchdog(void) |
| 315 | { |
| 316 | /* |
| 317 | * Clear TSR(WIS) bit by writing 1 |
| 318 | */ |
Mark Marshall | 320d53d | 2012-09-09 23:06:03 +0000 | [diff] [blame] | 319 | mtspr(SPRN_TSR, TSR_WIS); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 320 | } |
Horst Kronstorfer | df616ca | 2013-03-13 10:14:05 +0000 | [diff] [blame] | 321 | |
| 322 | void |
| 323 | watchdog_reset(void) |
| 324 | { |
| 325 | int re_enable = disable_interrupts(); |
| 326 | |
| 327 | reset_85xx_watchdog(); |
| 328 | if (re_enable) |
| 329 | enable_interrupts(); |
| 330 | } |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 331 | #endif /* CONFIG_WATCHDOG */ |
| 332 | |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 333 | /* |
Andy Fleming | 80522dc | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 334 | * Initializes on-chip MMC controllers. |
| 335 | * to override, implement board_mmc_init() |
| 336 | */ |
| 337 | int cpu_mmc_init(bd_t *bis) |
| 338 | { |
| 339 | #ifdef CONFIG_FSL_ESDHC |
| 340 | return fsl_esdhc_mmc_init(bis); |
| 341 | #else |
| 342 | return 0; |
| 343 | #endif |
| 344 | } |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 345 | |
| 346 | /* |
| 347 | * Print out the state of various machine registers. |
Dipen Dudhat | d789b5f | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 348 | * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing |
| 349 | * parameters for IFC and TLBs |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 350 | */ |
| 351 | void mpc85xx_reginfo(void) |
| 352 | { |
| 353 | print_tlbcam(); |
| 354 | print_laws(); |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 355 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 356 | print_lbc_regs(); |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 357 | #endif |
Dipen Dudhat | d789b5f | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 358 | #ifdef CONFIG_FSL_IFC |
| 359 | print_ifc_regs(); |
| 360 | #endif |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 361 | |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 362 | } |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 363 | |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 364 | /* Common ddr init for non-corenet fsl 85xx platforms */ |
| 365 | #ifndef CONFIG_FSL_CORENET |
Scott Wood | c97cd1b | 2012-09-20 19:02:18 -0500 | [diff] [blame] | 366 | #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ |
| 367 | !defined(CONFIG_SYS_INIT_L2_ADDR) |
Zhao Chenhui | c1fc2d4 | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 368 | phys_size_t initdram(int board_type) |
| 369 | { |
Alexander Graf | fa08d39 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 370 | #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ |
| 371 | defined(CONFIG_QEMU_E500) |
Zhao Chenhui | c1fc2d4 | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 372 | return fsl_ddr_sdram_size(); |
| 373 | #else |
Mingkai Hu | 76d354f | 2013-04-12 15:56:28 +0800 | [diff] [blame] | 374 | return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Zhao Chenhui | c1fc2d4 | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 375 | #endif |
| 376 | } |
| 377 | #else /* CONFIG_SYS_RAMBOOT */ |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 378 | phys_size_t initdram(int board_type) |
| 379 | { |
| 380 | phys_size_t dram_size = 0; |
| 381 | |
Becky Bruce | 810c442 | 2010-12-17 17:17:58 -0600 | [diff] [blame] | 382 | #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 383 | { |
| 384 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 385 | unsigned int x = 10; |
| 386 | unsigned int i; |
| 387 | |
| 388 | /* |
| 389 | * Work around to stabilize DDR DLL |
| 390 | */ |
| 391 | out_be32(&gur->ddrdllcr, 0x81000000); |
| 392 | asm("sync;isync;msync"); |
| 393 | udelay(200); |
| 394 | while (in_be32(&gur->ddrdllcr) != 0x81000100) { |
| 395 | setbits_be32(&gur->devdisr, 0x00010000); |
| 396 | for (i = 0; i < x; i++) |
| 397 | ; |
| 398 | clrbits_be32(&gur->devdisr, 0x00010000); |
| 399 | x++; |
| 400 | } |
| 401 | } |
| 402 | #endif |
| 403 | |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 404 | #if defined(CONFIG_SPD_EEPROM) || \ |
| 405 | defined(CONFIG_DDR_SPD) || \ |
| 406 | defined(CONFIG_SYS_DDR_RAW_TIMING) |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 407 | dram_size = fsl_ddr_sdram(); |
| 408 | #else |
| 409 | dram_size = fixed_sdram(); |
| 410 | #endif |
| 411 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 412 | dram_size *= 0x100000; |
| 413 | |
| 414 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 415 | /* |
| 416 | * Initialize and enable DDR ECC. |
| 417 | */ |
| 418 | ddr_enable_ecc(dram_size); |
| 419 | #endif |
| 420 | |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 421 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 422 | /* Some boards also have sdram on the lbc */ |
Becky Bruce | 70961ba | 2010-12-17 17:17:57 -0600 | [diff] [blame] | 423 | lbc_sdram_init(); |
Dipen Dudhat | beba93e | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 424 | #endif |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 425 | |
Wolfgang Denk | 21cd581 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 426 | debug("DDR: "); |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 427 | return dram_size; |
| 428 | } |
Zhao Chenhui | c1fc2d4 | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 429 | #endif /* CONFIG_SYS_RAMBOOT */ |
Becky Bruce | 38dba0c | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 430 | #endif |
| 431 | |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 432 | #if CONFIG_POST & CONFIG_SYS_POST_MEMORY |
| 433 | |
| 434 | /* Board-specific functions defined in each board's ddr.c */ |
| 435 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
| 436 | unsigned int ctrl_num); |
| 437 | void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, |
| 438 | phys_addr_t *rpn); |
| 439 | unsigned int |
| 440 | setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 441 | |
Becky Bruce | 9cdfe28 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 442 | void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 443 | |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 444 | static void dump_spd_ddr_reg(void) |
| 445 | { |
| 446 | int i, j, k, m; |
| 447 | u8 *p_8; |
| 448 | u32 *p_32; |
York Sun | 9a17eb5 | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 449 | struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 450 | generic_spd_eeprom_t |
| 451 | spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; |
| 452 | |
| 453 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) |
| 454 | fsl_ddr_get_spd(spd[i], i); |
| 455 | |
| 456 | puts("SPD data of all dimms (zero vaule is omitted)...\n"); |
| 457 | puts("Byte (hex) "); |
| 458 | k = 1; |
| 459 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 460 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) |
| 461 | printf("Dimm%d ", k++); |
| 462 | } |
| 463 | puts("\n"); |
| 464 | for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { |
| 465 | m = 0; |
| 466 | printf("%3d (0x%02x) ", k, k); |
| 467 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 468 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 469 | p_8 = (u8 *) &spd[i][j]; |
| 470 | if (p_8[k]) { |
| 471 | printf("0x%02x ", p_8[k]); |
| 472 | m++; |
| 473 | } else |
| 474 | puts(" "); |
| 475 | } |
| 476 | } |
| 477 | if (m) |
| 478 | puts("\n"); |
| 479 | else |
| 480 | puts("\r"); |
| 481 | } |
| 482 | |
| 483 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 484 | switch (i) { |
| 485 | case 0: |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 486 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 487 | break; |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 488 | #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 489 | case 1: |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 490 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 491 | break; |
| 492 | #endif |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 493 | #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 494 | case 2: |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 495 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 496 | break; |
| 497 | #endif |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 498 | #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 499 | case 3: |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 500 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 501 | break; |
| 502 | #endif |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 503 | default: |
| 504 | printf("%s unexpected controller number = %u\n", |
| 505 | __func__, i); |
| 506 | return; |
| 507 | } |
| 508 | } |
| 509 | printf("DDR registers dump for all controllers " |
| 510 | "(zero vaule is omitted)...\n"); |
| 511 | puts("Offset (hex) "); |
| 512 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) |
| 513 | printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); |
| 514 | puts("\n"); |
York Sun | 9a17eb5 | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 515 | for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 516 | m = 0; |
| 517 | printf("%6d (0x%04x)", k * 4, k * 4); |
| 518 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 519 | p_32 = (u32 *) ddr[i]; |
| 520 | if (p_32[k]) { |
| 521 | printf(" 0x%08x", p_32[k]); |
| 522 | m++; |
| 523 | } else |
| 524 | puts(" "); |
| 525 | } |
| 526 | if (m) |
| 527 | puts("\n"); |
| 528 | else |
| 529 | puts("\r"); |
| 530 | } |
| 531 | puts("\n"); |
| 532 | } |
| 533 | |
| 534 | /* invalid the TLBs for DDR and setup new ones to cover p_addr */ |
| 535 | static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) |
| 536 | { |
| 537 | u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 538 | unsigned long epn; |
| 539 | u32 tsize, valid, ptr; |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 540 | int ddr_esel; |
| 541 | |
Becky Bruce | 9cdfe28 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 542 | clear_ddr_tlbs_phys(p_addr, size>>20); |
York Sun | ebbe11d | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 543 | |
| 544 | /* Setup new tlb to cover the physical address */ |
| 545 | setup_ddr_tlbs_phys(p_addr, size>>20); |
| 546 | |
| 547 | ptr = vstart; |
| 548 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 549 | if (ddr_esel != -1) { |
| 550 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); |
| 551 | } else { |
| 552 | printf("TLB error in function %s\n", __func__); |
| 553 | return -1; |
| 554 | } |
| 555 | |
| 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | /* |
| 560 | * slide the testing window up to test another area |
| 561 | * for 32_bit system, the maximum testable memory is limited to |
| 562 | * CONFIG_MAX_MEM_MAPPED |
| 563 | */ |
| 564 | int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 565 | { |
| 566 | phys_addr_t test_cap, p_addr; |
| 567 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 568 | |
| 569 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 570 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 571 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 572 | test_cap = p_size; |
| 573 | #else |
| 574 | test_cap = gd->ram_size; |
| 575 | #endif |
| 576 | p_addr = (*vstart) + (*size) + (*phys_offset); |
| 577 | if (p_addr < test_cap - 1) { |
| 578 | p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); |
| 579 | if (reset_tlb(p_addr, p_size, phys_offset) == -1) |
| 580 | return -1; |
| 581 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 582 | *size = (u32) p_size; |
| 583 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 584 | (u64)(*vstart) + (*phys_offset), |
| 585 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 586 | } else |
| 587 | return 1; |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | /* initialization for testing area */ |
| 593 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 594 | { |
| 595 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 596 | |
| 597 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 598 | *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ |
| 599 | *phys_offset = 0; |
| 600 | |
| 601 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 602 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 603 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 604 | if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { |
| 605 | puts("Cannot test more than "); |
| 606 | print_size(CONFIG_MAX_MEM_MAPPED, |
| 607 | " without proper 36BIT support.\n"); |
| 608 | } |
| 609 | #endif |
| 610 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 611 | (u64)(*vstart) + (*phys_offset), |
| 612 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | /* invalid TLBs for DDR and remap as normal after testing */ |
| 618 | int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 619 | { |
| 620 | unsigned long epn; |
| 621 | u32 tsize, valid, ptr; |
| 622 | phys_addr_t rpn = 0; |
| 623 | int ddr_esel; |
| 624 | |
| 625 | /* disable the TLBs for this testing */ |
| 626 | ptr = *vstart; |
| 627 | |
| 628 | while (ptr < (*vstart) + (*size)) { |
| 629 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 630 | if (ddr_esel != -1) { |
| 631 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); |
| 632 | disable_tlb(ddr_esel); |
| 633 | } |
| 634 | ptr += TSIZE_TO_BYTES(tsize); |
| 635 | } |
| 636 | |
| 637 | puts("Remap DDR "); |
| 638 | setup_ddr_tlbs(gd->ram_size>>20); |
| 639 | puts("\n"); |
| 640 | |
| 641 | return 0; |
| 642 | } |
| 643 | |
| 644 | void arch_memory_failure_handle(void) |
| 645 | { |
| 646 | dump_spd_ddr_reg(); |
| 647 | } |
| 648 | #endif |