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Simon Glass2444dae2015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner041cdb52016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutlaacf15002018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yanga381bcf2016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Cai451dcf52018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner041cdb52016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangdaeed1d2017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangdaeed1d2017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübner0a2be692017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan0680f1b2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübner0a2be692017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübner0a2be692017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich4bbb05b2017-10-10 16:21:17 +020031 select SPL_CLK
Philipp Tomsich4bbb05b2017-10-10 16:21:17 +020032 select SPL_REGMAP
33 select SPL_SYSCON
34 select SPL_RAM
35 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich4d9253f2017-10-10 16:21:15 +020036 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbf1133b2019-07-22 19:59:15 +080037 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner008a6102017-04-06 00:19:36 +020038 select BOARD_LATE_INIT
Kever Yang4eb50632019-07-22 19:59:18 +080039 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübner0a2be692017-02-18 19:46:36 +010040 help
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43 video interfaces, several memory options and video codec support.
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45 UART, SPI, I2C and PWMs.
46
Kever Yang168eef72017-06-23 17:17:52 +080047config ROCKCHIP_RK322X
48 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053049 select CPU_V7A
Kever Yang168eef72017-06-23 17:17:52 +080050 select SUPPORT_SPL
Kever Yangc34643e2019-04-02 20:41:24 +080051 select SUPPORT_TPL
Kever Yang168eef72017-06-23 17:17:52 +080052 select SPL
Kever Yangc34643e2019-04-02 20:41:24 +080053 select SPL_DM
54 select SPL_OF_LIBFDT
55 select TPL
56 select TPL_DM
57 select TPL_OF_LIBFDT
58 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
59 select TPL_NEEDS_SEPARATE_STACK if TPL
60 select SPL_DRIVERS_MISC_SUPPORT
61 imply SPL_SERIAL_SUPPORT
Kever Yang0cd65e42019-07-22 19:59:20 +080062 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangc34643e2019-04-02 20:41:24 +080063 imply TPL_SERIAL_SUPPORT
Kever Yang6ae28a32019-07-09 22:05:56 +080064 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangc34643e2019-04-02 20:41:24 +080065 select TPL_LIBCOMMON_SUPPORT
66 select TPL_LIBGENERIC_SUPPORT
Kever Yang168eef72017-06-23 17:17:52 +080067 help
68 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
69 including NEON and GPU, Mali-400 graphics, several DDR3 options
70 and video codec support. Peripherals include Gigabit Ethernet,
71 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
72
Simon Glass2444dae2015-08-30 16:55:38 -060073config ROCKCHIP_RK3288
74 bool "Support Rockchip RK3288"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053075 select CPU_V7A
Kever Yanga381bcf2016-07-19 21:16:59 +080076 select SUPPORT_SPL
77 select SPL
Kever Yangd18ca742019-07-02 11:43:05 +080078 select SUPPORT_TPL
Kever Yang60b13c82019-07-22 19:59:27 +080079 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangd18ca742019-07-02 11:43:05 +080080 imply TPL_CLK
81 imply TPL_DM
82 imply TPL_DRIVERS_MISC_SUPPORT
83 imply TPL_LIBCOMMON_SUPPORT
84 imply TPL_LIBGENERIC_SUPPORT
85 imply TPL_NEEDS_SEPARATE_TEXT_BASE
Kever Yang45290842019-07-02 11:43:06 +080086 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangd18ca742019-07-02 11:43:05 +080087 imply TPL_OF_CONTROL
88 imply TPL_OF_PLATDATA
89 imply TPL_RAM
90 imply TPL_REGMAP
Kever Yang3338f542019-07-09 22:05:57 +080091 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangd18ca742019-07-02 11:43:05 +080092 imply TPL_SERIAL_SUPPORT
93 imply TPL_SYSCON
Eddie Caic3d098e2017-12-15 08:17:13 +080094 imply USB_FUNCTION_ROCKUSB
95 imply CMD_ROCKUSB
Simon Glass2444dae2015-08-30 16:55:38 -060096 help
97 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
98 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
99 video interfaces supporting HDMI and eDP, several DDR3 options
100 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färberef904bf2016-11-02 18:03:01 +0100101 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2444dae2015-08-30 16:55:38 -0600102
Kever Yang85a3cfb2017-02-23 15:37:51 +0800103config ROCKCHIP_RK3328
104 bool "Support Rockchip RK3328"
105 select ARM64
Kever Yangc009aeb2019-06-09 00:27:15 +0300106 select SUPPORT_SPL
107 select SPL
Kever Yang9cc67042019-07-22 19:59:32 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangc009aeb2019-06-09 00:27:15 +0300109 imply SPL_SERIAL_SUPPORT
110 imply SPL_SEPARATE_BSS
111 select ENABLE_ARM_SOC_BOOT0_HOOK
112 select DEBUG_UART_BOARD_INIT
113 select SYS_NS16550
Kever Yang85a3cfb2017-02-23 15:37:51 +0800114 help
115 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
116 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
117 video interfaces supporting HDMI and eDP, several DDR3 options
118 and video codec support. Peripherals include Gigabit Ethernet,
119 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
120
Andreas Färber37a0c602017-05-15 17:51:18 +0800121config ROCKCHIP_RK3368
122 bool "Support Rockchip RK3368"
123 select ARM64
Philipp Tomsich50714572017-06-11 23:46:25 +0200124 select SUPPORT_SPL
125 select SUPPORT_TPL
Philipp Tomsich4cf43782017-07-28 20:03:07 +0200126 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
127 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang30d71092019-07-22 19:59:34 +0800128 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich50714572017-06-11 23:46:25 +0200129 imply SPL_SEPARATE_BSS
130 imply SPL_SERIAL_SUPPORT
131 imply TPL_SERIAL_SUPPORT
Kever Yang82560cb2019-07-09 22:05:58 +0800132 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber37a0c602017-05-15 17:51:18 +0800133 help
Philipp Tomsich9a8f0092017-06-10 00:47:53 +0200134 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
135 into a big and little cluster with 4 cores each) Cortex-A53 including
136 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
137 (for the little cluster), PowerVR G6110 based graphics, one video
138 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
139 video codec support.
140
141 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
142 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber37a0c602017-05-15 17:51:18 +0800143
Kever Yanga381bcf2016-07-19 21:16:59 +0800144config ROCKCHIP_RK3399
145 bool "Support Rockchip RK3399"
146 select ARM64
Kever Yang66e87cc2017-02-22 16:56:38 +0800147 select SUPPORT_SPL
Kever Yang6bbf5e12018-11-09 11:18:15 +0800148 select SUPPORT_TPL
Kever Yang66e87cc2017-02-22 16:56:38 +0800149 select SPL
Jagan Teki2666bd42019-05-08 11:11:43 +0530150 select SPL_ATF
151 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Tekiadde32d2019-06-21 00:25:03 +0530152 select SPL_BOARD_INIT if SPL
Jagan Teki2666bd42019-05-08 11:11:43 +0530153 select SPL_LOAD_FIT
154 select SPL_CLK if SPL
155 select SPL_PINCTRL if SPL
156 select SPL_RAM if SPL
157 select SPL_REGMAP if SPL
158 select SPL_SYSCON if SPL
Kever Yang6bbf5e12018-11-09 11:18:15 +0800159 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
160 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang66e87cc2017-02-22 16:56:38 +0800161 select SPL_SEPARATE_BSS
Philipp Tomsichc0508e42017-07-26 12:29:01 +0200162 select SPL_SERIAL_SUPPORT
163 select SPL_DRIVERS_MISC_SUPPORT
Jagan Teki2666bd42019-05-08 11:11:43 +0530164 select CLK
165 select FIT
166 select PINCTRL
167 select RAM
168 select REGMAP
169 select SYSCON
170 select DM_PMIC
171 select DM_REGULATOR_FIXED
Andy Yane3067792017-10-11 15:00:16 +0800172 select BOARD_LATE_INIT
Kever Yangb7abef22019-07-22 19:59:42 +0800173 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yang6bbf5e12018-11-09 11:18:15 +0800174 imply TPL_SERIAL_SUPPORT
175 imply TPL_LIBCOMMON_SUPPORT
176 imply TPL_LIBGENERIC_SUPPORT
177 imply TPL_SYS_MALLOC_SIMPLE
Kever Yang6bbf5e12018-11-09 11:18:15 +0800178 imply TPL_DRIVERS_MISC_SUPPORT
179 imply TPL_OF_CONTROL
180 imply TPL_DM
181 imply TPL_REGMAP
182 imply TPL_SYSCON
183 imply TPL_RAM
184 imply TPL_CLK
185 imply TPL_TINY_MEMSET
Kever Yang27381812019-07-09 22:06:01 +0800186 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yanga381bcf2016-07-19 21:16:59 +0800187 help
188 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
189 and quad-core Cortex-A53.
190 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
191 video interfaces supporting HDMI and eDP, several DDR3 options
192 and video codec support. Peripherals include Gigabit Ethernet,
193 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
194
Andy Yan2c1e11d2017-06-01 18:00:55 +0800195config ROCKCHIP_RV1108
196 bool "Support Rockchip RV1108"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530197 select CPU_V7A
Andy Yan2c1e11d2017-06-01 18:00:55 +0800198 help
199 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
200 and a DSP.
201
Heiko Stuebner5b5ca4c2018-10-08 13:01:56 +0200202config ROCKCHIP_USB_UART
203 bool "Route uart output to usb pins"
204 help
205 Rockchip SoCs have the ability to route the signals of the debug
206 uart through the d+ and d- pins of a specific usb phy to enable
207 some form of closed-case debugging. With this option supported
208 SoCs will enable this routing as a debug measure.
209
Philipp Tomsichee14d292017-06-29 11:21:15 +0200210config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuanb47ea792016-07-12 19:09:49 +0800211 bool "SPL returns to bootrom"
212 default y if ROCKCHIP_RK3036
Heiko Stübner1d845942017-02-18 19:46:25 +0100213 select ROCKCHIP_BROM_HELPER
Kever Yangbf1133b2019-07-22 19:59:15 +0800214 select SPL_BOOTROM_SUPPORT
Philipp Tomsichee14d292017-06-29 11:21:15 +0200215 depends on SPL
216 help
217 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
218 SPL will return to the boot rom, which will then load the U-Boot
219 binary to keep going on.
220
221config TPL_ROCKCHIP_BACK_TO_BROM
222 bool "TPL returns to bootrom"
Kever Yang6bbf5e12018-11-09 11:18:15 +0800223 default y
Philipp Tomsichee14d292017-06-29 11:21:15 +0200224 select ROCKCHIP_BROM_HELPER
Kever Yangbf1133b2019-07-22 19:59:15 +0800225 select TPL_BOOTROM_SUPPORT
Philipp Tomsichee14d292017-06-29 11:21:15 +0200226 depends on TPL
Xu Ziyuanb47ea792016-07-12 19:09:49 +0800227 help
228 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
229 SPL will return to the boot rom, which will then load the U-Boot
230 binary to keep going on.
231
Kever Yang54f17fa2019-07-22 20:02:01 +0800232config ROCKCHIP_COMMON_BOARD
233 bool "Rockchip common board file"
234 help
235 Rockchip SoCs have similar boot process, Common board file is mainly
236 in charge of common process of board_init() and board_late_init() for
237 U-Boot proper.
238
Kever Yang49105fb2019-07-22 19:59:12 +0800239config SPL_ROCKCHIP_COMMON_BOARD
240 bool "Rockchip SPL common board file"
241 depends on SPL
242 help
243 Rockchip SoCs have similar boot process, SPL is mainly in charge of
244 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
245 no TPL for the board.
246
Kever Yang18f85082019-07-09 22:05:55 +0800247config TPL_ROCKCHIP_COMMON_BOARD
248 bool ""
249 depends on TPL
250 help
251 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
252 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
253 common board is a basic TPL board init which can be shared for most
254 of SoCs to avoid copy-pase for different SoCs.
255
Andy Yane3067792017-10-11 15:00:16 +0800256config ROCKCHIP_BOOT_MODE_REG
257 hex "Rockchip boot mode flag register address"
Andy Yane3067792017-10-11 15:00:16 +0800258 help
Kever Yang15f09a12019-03-28 11:01:23 +0800259 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yane3067792017-10-11 15:00:16 +0800260 according to the value from this register.
261
Kever Yangfa1392a2017-04-20 17:03:46 +0800262config ROCKCHIP_SPL_RESERVE_IRAM
263 hex "Size of IRAM reserved in SPL"
Kever Yang8a8106f2017-12-18 15:13:19 +0800264 default 0
Kever Yangfa1392a2017-04-20 17:03:46 +0800265 help
266 SPL may need reserve memory for firmware loaded by SPL, whose load
267 address is in IRAM and may overlay with SPL text area if not
268 reserved.
269
Heiko Stübner1d845942017-02-18 19:46:25 +0100270config ROCKCHIP_BROM_HELPER
271 bool
272
Philipp Tomsichb377d222017-10-10 16:21:10 +0200273config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
274 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
275 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
276 help
277 Some Rockchip BROM variants (e.g. on the RK3188) load the
278 first stage in segments and enter multiple times. E.g. on
279 the RK3188, the first 1KB of the first stage are loaded
280 first and entered; after returning to the BROM, the
281 remainder of the first stage is loaded, but the BROM
282 re-enters at the same address/to the same code as previously.
283
284 This enables support code in the BOOT0 hook for the SPL stage
285 to allow multiple entries.
286
287config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
288 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
289 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
290 help
291 Some Rockchip BROM variants (e.g. on the RK3188) load the
292 first stage in segments and enter multiple times. E.g. on
293 the RK3188, the first 1KB of the first stage are loaded
294 first and entered; after returning to the BROM, the
295 remainder of the first stage is loaded, but the BROM
296 re-enters at the same address/to the same code as previously.
297
298 This enables support code in the BOOT0 hook for the TPL stage
299 to allow multiple entries.
300
Sandy Patterson230e0e02016-08-29 07:31:16 -0400301config SPL_MMC_SUPPORT
Philipp Tomsichee14d292017-06-29 11:21:15 +0200302 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Patterson230e0e02016-08-29 07:31:16 -0400303
huang linbe1d5e02015-11-17 14:20:27 +0800304source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangdaeed1d2017-11-28 16:04:16 +0800305source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübner0a2be692017-02-18 19:46:36 +0100306source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yangb24a8ec2017-06-23 17:17:54 +0800307source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner041cdb52016-07-16 00:17:15 +0200308source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yang85a3cfb2017-02-23 15:37:51 +0800309source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber37a0c602017-05-15 17:51:18 +0800310source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yanga381bcf2016-07-19 21:16:59 +0800311source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2c1e11d2017-06-01 18:00:55 +0800312source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2444dae2015-08-30 16:55:38 -0600313endif