blob: 9cb0d42eac7b02dfd71ab8a6aec195077710f033 [file] [log] [blame]
wdenk43d96162003-03-06 00:02:04 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Auerswald Innokom CPU board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/innokom.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenk43d96162003-03-06 00:02:04 +000033/*
wdenk43d96162003-03-06 00:02:04 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
wdenk43d96162003-03-06 00:02:04 +000038#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
39
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020042
43/* we will never enable dcache, because we have to setup MMU first */
44#define CONFIG_SYS_NO_DCACHE
45
wdenk43d96162003-03-06 00:02:04 +000046/*
47 * Hardware drivers
48 */
49
50/*
51 * select serial console configuration
52 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020053#define CONFIG_PXA_SERIAL
wdenk43d96162003-03-06 00:02:04 +000054#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
55
56/* allow to overwrite serial and ethaddr */
57#define CONFIG_ENV_OVERWRITE
58
59#define CONFIG_BAUDRATE 19200
wdenk06d01db2003-03-14 20:47:52 +000060#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
wdenk43d96162003-03-06 00:02:04 +000061
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050062
63/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
71
72/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050073 * Command line configuration.
74 */
75
76#define CONFIG_CMD_ASKENV
77#define CONFIG_CMD_BDI
78#define CONFIG_CMD_CACHE
79#define CONFIG_CMD_DHCP
80#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -050081#define CONFIG_CMD_SAVEENV
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050082#define CONFIG_CMD_FLASH
83#define CONFIG_CMD_I2C
84#define CONFIG_CMD_IMI
85#define CONFIG_CMD_LOADB
86#define CONFIG_CMD_MEMORY
87#define CONFIG_CMD_NET
88#define CONFIG_CMD_RUN
89
wdenk43d96162003-03-06 00:02:04 +000090
91#define CONFIG_BOOTDELAY 3
92/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
93#define CONFIG_BOOTARGS "console=ttyS0,19200"
94#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
95#define CONFIG_NETMASK 255.255.255.0
96#define CONFIG_IPADDR 192.168.1.56
97#define CONFIG_SERVERIP 192.168.1.2
98#define CONFIG_BOOTCOMMAND "bootm 0x40000"
99#define CONFIG_SHOW_BOOT_PROGRESS
100
101#define CONFIG_CMDLINE_TAG 1
102
wdenk43d96162003-03-06 00:02:04 +0000103/*
104 * Miscellaneous configurable options
105 */
106
107/*
wdenkf6e20fc2004-02-08 19:38:38 +0000108 * Size of malloc() pool
wdenk43d96162003-03-06 00:02:04 +0000109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MALLOC_LEN (256*1024)
111#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk43d96162003-03-06 00:02:04 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
114#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk43d96162003-03-06 00:02:04 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
121#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenk43d96162003-03-06 00:02:04 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
wdenk43d96162003-03-06 00:02:04 +0000124
Micha Kalfon94a33122009-02-11 19:50:11 +0200125#define CONFIG_SYS_HZ 1000
wdenk43d96162003-03-06 00:02:04 +0000126 /* RS: the oscillator is actually 3680130?? */
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
wdenk43d96162003-03-06 00:02:04 +0000129 /* 0101000001 */
130 /* ^^^^^ Memory Speed 99.53 MHz */
131 /* ^^ Run Mode Speed = 2x Mem Speed */
132 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
wdenk43d96162003-03-06 00:02:04 +0000135
wdenk8bde7f72003-06-27 21:31:46 +0000136 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk43d96162003-03-06 00:02:04 +0000138
139/*
140 * I2C bus
141 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200142#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_I2C_SPEED 50000
144#define CONFIG_SYS_I2C_SLAVE 0xfe
wdenk43d96162003-03-06 00:02:04 +0000145
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200146#define CONFIG_ENV_IS_IN_EEPROM 1
wdenk43d96162003-03-06 00:02:04 +0000147
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200148#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
149#define CONFIG_ENV_SIZE 1024 /* 1 KiB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
154#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
155#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
wdenk06d01db2003-03-14 20:47:52 +0000156
157/*
158 * SMSC91C111 Network Card
159 */
Ben Warren7194ab82009-10-04 22:37:03 -0700160#define CONFIG_NET_MULTI
161#define CONFIG_SMC91111 1
wdenk06d01db2003-03-14 20:47:52 +0000162#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
163#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
164#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
wdenkf39748a2004-06-09 13:37:52 +0000165#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
wdenk06d01db2003-03-14 20:47:52 +0000166#undef CONFIG_SHOW_ACTIVITY
167#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
wdenk43d96162003-03-06 00:02:04 +0000168
169/*
170 * Stack sizes
171 *
172 * The stack sizes are set up in start.S using the settings below
173 */
174#define CONFIG_STACKSIZE (128*1024) /* regular stack */
175#ifdef CONFIG_USE_IRQ
176#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
177#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
178#endif
179
180/*
181 * Physical Memory Map
182 */
183#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
184#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
185#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
186
187#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
188#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
191#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenk43d96162003-03-06 00:02:04 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk43d96162003-03-06 00:02:04 +0000194
wdenk06d01db2003-03-14 20:47:52 +0000195/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200196 * JFFS2 partitions
197 *
wdenk06d01db2003-03-14 20:47:52 +0000198 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200199/* development flash */
200#define CONFIG_MTD_INNOKOM_16MB 1
201#undef CONFIG_MTD_INNOKOM_64MB
wdenk06d01db2003-03-14 20:47:52 +0000202
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200203/* production flash */
204/*
205#define CONFIG_MTD_INNOKOM_64MB 1
206#undef CONFIG_MTD_INNOKOM_16MB
207*/
208
209/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100210#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200211#define CONFIG_JFFS2_DEV "nor0"
212#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
213#define CONFIG_JFFS2_PART_OFFSET 0x00000000
214
215/* mtdparts command line support */
216/* Note: fake mtd_id used, no linux mtd map file */
217/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100218#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200219#define MTDIDS_DEFAULT "nor0=innokom-0"
220*/
221
222/* development flash */
223/*
224#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
225*/
226
227/* production flash */
228/*
229#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
230*/
wdenk06d01db2003-03-14 20:47:52 +0000231
232/*
wdenk3e386912003-04-05 00:53:31 +0000233 * GPIO settings
wdenk06d01db2003-03-14 20:47:52 +0000234 *
235 * GP15 == nCS1 is 1
wdenk43d96162003-03-06 00:02:04 +0000236 * GP24 == SFRM is 1
237 * GP25 == TXD is 1
238 * GP33 == nCS5 is 1
239 * GP39 == FFTXD is 1
240 * GP41 == RTS is 1
241 * GP47 == TXD is 1
242 * GP49 == nPWE is 1
243 * GP62 == LED_B is 1
244 * GP63 == TDM_OE is 1
245 * GP78 == nCS2 is 1
246 * GP79 == nCS3 is 1
247 * GP80 == nCS4 is 1
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_GPSR0_VAL 0x03008000
250#define CONFIG_SYS_GPSR1_VAL 0xC0028282
251#define CONFIG_SYS_GPSR2_VAL 0x0001C000
wdenk43d96162003-03-06 00:02:04 +0000252
253/* GP02 == DON_RST is 0
254 * GP23 == SCLK is 0
255 * GP45 == USB_ACT is 0
256 * GP60 == PLLEN is 0
257 * GP61 == LED_A is 0
258 * GP73 == SWUPD_LED is 0
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_GPCR0_VAL 0x00800004
261#define CONFIG_SYS_GPCR1_VAL 0x30002000
262#define CONFIG_SYS_GPCR2_VAL 0x00000100
wdenk43d96162003-03-06 00:02:04 +0000263
264/* GP00 == DON_READY is input
265 * GP01 == DON_OK is input
266 * GP02 == DON_RST is output
267 * GP03 == RESET_IND is input
268 * GP07 == RES11 is input
269 * GP09 == RES12 is input
270 * GP11 == SWUPDATE is input
271 * GP14 == nPOWEROK is input
272 * GP15 == nCS1 is output
273 * GP17 == RES22 is input
274 * GP18 == RDY is input
275 * GP23 == SCLK is output
276 * GP24 == SFRM is output
277 * GP25 == TXD is output
278 * GP26 == RXD is input
279 * GP32 == RES21 is input
280 * GP33 == nCS5 is output
281 * GP34 == FFRXD is input
282 * GP35 == CTS is input
283 * GP39 == FFTXD is output
284 * GP41 == RTS is output
285 * GP42 == USB_OK is input
286 * GP45 == USB_ACT is output
287 * GP46 == RXD is input
288 * GP47 == TXD is output
289 * GP49 == nPWE is output
290 * GP58 == nCPUBUSINT is input
291 * GP59 == LANINT is input
292 * GP60 == PLLEN is output
293 * GP61 == LED_A is output
294 * GP62 == LED_B is output
295 * GP63 == TDM_OE is output
296 * GP64 == nDSPINT is input
297 * GP65 == STRAP0 is input
298 * GP67 == STRAP1 is input
299 * GP69 == STRAP2 is input
300 * GP70 == STRAP3 is input
301 * GP71 == STRAP4 is input
302 * GP73 == SWUPD_LED is output
303 * GP78 == nCS2 is output
304 * GP79 == nCS3 is output
305 * GP80 == nCS4 is output
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_GPDR0_VAL 0x03808004
308#define CONFIG_SYS_GPDR1_VAL 0xF002A282
309#define CONFIG_SYS_GPDR2_VAL 0x0001C200
wdenk43d96162003-03-06 00:02:04 +0000310
311/* GP15 == nCS1 is AF10
312 * GP18 == RDY is AF01
313 * GP23 == SCLK is AF10
314 * GP24 == SFRM is AF10
315 * GP25 == TXD is AF10
316 * GP26 == RXD is AF01
317 * GP33 == nCS5 is AF10
318 * GP34 == FFRXD is AF01
319 * GP35 == CTS is AF01
320 * GP39 == FFTXD is AF10
321 * GP41 == RTS is AF10
322 * GP46 == RXD is AF10
323 * GP47 == TXD is AF01
324 * GP49 == nPWE is AF10
325 * GP78 == nCS2 is AF10
326 * GP79 == nCS3 is AF10
327 * GP80 == nCS4 is AF10
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
330#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
331#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
332#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
333#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
334#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenk43d96162003-03-06 00:02:04 +0000335
wdenk06d01db2003-03-14 20:47:52 +0000336
wdenk43d96162003-03-06 00:02:04 +0000337/* FIXME: set GPIO_RER/FER */
338
339/* RDH = 1
340 * PH = 1
341 * VFS = 1
342 * BFS = 1
343 * SSS = 1
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PSSR_VAL 0x37
wdenk43d96162003-03-06 00:02:04 +0000346
347/*
348 * Memory settings
wdenk06d01db2003-03-14 20:47:52 +0000349 *
350 * This is the configuration for nCS0/1 -> flash banks
wdenk43d96162003-03-06 00:02:04 +0000351 * configuration for nCS1:
352 * [31] 0 - Slower Device
353 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
354 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
355 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
356 * [19] 1 - 16 Bit bus width
357 * [18:16] 000 - nonburst RAM or FLASH
358 * configuration for nCS0:
359 * [15] 0 - Slower Device
360 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
361 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
362 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
363 * [03] 1 - 16 Bit bus width
364 * [02:00] 000 - nonburst RAM or FLASH
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
wdenk43d96162003-03-06 00:02:04 +0000367
368/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
369 * configuration for nCS3: DSP
370 * [31] 0 - Slower Device
371 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
372 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
373 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
374 * [19] 1 - 16 Bit bus width
375 * [18:16] 100 - variable latency I/O
376 * configuration for nCS2: TDM-Switch
377 * [15] 0 - Slower Device
378 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
379 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
380 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
381 * [03] 1 - 16 Bit bus width
382 * [02:00] 100 - variable latency I/O
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
wdenk43d96162003-03-06 00:02:04 +0000385
386/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
387 *
388 * configuration for nCS5: LAN Controller
389 * [31] 0 - Slower Device
390 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
391 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
392 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
393 * [19] 1 - 16 Bit bus width
394 * [18:16] 100 - variable latency I/O
395 * configuration for nCS4: ExtBus
396 * [15] 0 - Slower Device
397 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
398 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
399 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
400 * [03] 1 - 16 Bit bus width
401 * [02:00] 100 - variable latency I/O
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
wdenk43d96162003-03-06 00:02:04 +0000404
405/* MDCNFG: SDRAM Configuration Register
406 *
407 * [31:29] 000 - reserved
408 * [28] 0 - no SA1111 compatiblity mode
409 * [27] 0 - latch return data with return clock
410 * [26] 0 - alternate addressing for pair 2/3
411 * [25:24] 00 - timings
412 * [23] 0 - internal banks in lower partition 2/3 (not used)
413 * [22:21] 00 - row address bits for partition 2/3 (not used)
414 * [20:19] 00 - column address bits for partition 2/3 (not used)
415 * [18] 0 - SDRAM partition 2/3 width is 32 bit
416 * [17] 0 - SDRAM partition 3 disabled
417 * [16] 0 - SDRAM partition 2 disabled
418 * [15:13] 000 - reserved
419 * [12] 1 - SA1111 compatiblity mode
420 * [11] 1 - latch return data with return clock
421 * [10] 0 - no alternate addressing for pair 0/1
wdenk06d01db2003-03-14 20:47:52 +0000422 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
wdenk43d96162003-03-06 00:02:04 +0000423 * [7] 1 - 4 internal banks in lower partition pair
424 * [06:05] 10 - 13 row address bits for partition 0/1
425 * [04:03] 01 - 9 column address bits for partition 0/1
426 * [02] 0 - SDRAM partition 0/1 width is 32 bit
427 * [01] 0 - disable SDRAM partition 1
428 * [00] 1 - enable SDRAM partition 0
wdenk43d96162003-03-06 00:02:04 +0000429 */
wdenk06d01db2003-03-14 20:47:52 +0000430/* use the configuration above but disable partition 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
wdenk43d96162003-03-06 00:02:04 +0000432
433/* MDREFR: SDRAM Refresh Control Register
434 *
435 * [32:26] 0 - reserved
436 * [25] 0 - K2FREE: not free running
437 * [24] 0 - K1FREE: not free running
wdenk3e386912003-04-05 00:53:31 +0000438 * [23] 1 - K0FREE: not free running
wdenk43d96162003-03-06 00:02:04 +0000439 * [22] 0 - SLFRSH: self refresh disabled
440 * [21] 0 - reserved
441 * [20] 0 - APD: no auto power down
442 * [19] 0 - K2DB2: SDCLK2 is MemClk
443 * [18] 0 - K2RUN: disable SDCLK2
444 * [17] 0 - K1DB2: SDCLK1 is MemClk
445 * [16] 1 - K1RUN: enable SDCLK1
446 * [15] 1 - E1PIN: SDRAM clock enable
447 * [14] 1 - K0DB2: SDCLK0 is MemClk
wdenk3e386912003-04-05 00:53:31 +0000448 * [13] 0 - K0RUN: disable SDCLK0
wdenk43d96162003-03-06 00:02:04 +0000449 * [12] 1 - E0PIN: disable SDCKE0
450 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
451 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MDREFR_VAL 0x0081D018
wdenk43d96162003-03-06 00:02:04 +0000453
454/* MDMRS: Mode Register Set Configuration Register
455 *
456 * [31] 0 - reserved
457 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
458 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
459 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
460 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
461 * [15] 0 - reserved
462 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
463 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
464 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
465 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
466 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_MDMRS_VAL 0x00020022
wdenk43d96162003-03-06 00:02:04 +0000468
469/*
470 * PCMCIA and CF Interfaces
471 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_MECR_VAL 0x00000000
473#define CONFIG_SYS_MCMEM0_VAL 0x00000000
474#define CONFIG_SYS_MCMEM1_VAL 0x00000000
475#define CONFIG_SYS_MCATT0_VAL 0x00000000
476#define CONFIG_SYS_MCATT1_VAL 0x00000000
477#define CONFIG_SYS_MCIO0_VAL 0x00000000
478#define CONFIG_SYS_MCIO1_VAL 0x00000000
wdenk43d96162003-03-06 00:02:04 +0000479
480/*
481#define CSB226_USER_LED0 0x00000008
482#define CSB226_USER_LED1 0x00000010
483#define CSB226_USER_LED2 0x00000020
484*/
485
486/*
487 * FLASH and environment organization
488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
490#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
wdenk43d96162003-03-06 00:02:04 +0000491
492/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
494#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk43d96162003-03-06 00:02:04 +0000495
wdenk43d96162003-03-06 00:02:04 +0000496#endif /* __CONFIG_H */