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Chander Kashyap0aee53b2012-02-05 23:01:47 +00001/*
Hatim RV540b5af2012-12-11 00:52:48 +00002 * Copyright (C) 2012 Samsung Electronics
Chander Kashyap0aee53b2012-02-05 23:01:47 +00003 *
Hatim RV540b5af2012-12-11 00:52:48 +00004 * Configuration settings for the SAMSUNG EXYNOS5250 board.
Chander Kashyap0aee53b2012-02-05 23:01:47 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* High Level Configuration Options */
29#define CONFIG_SAMSUNG /* in a SAMSUNG core */
30#define CONFIG_S5P /* S5P Family */
31#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
32#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
33
34#include <asm/arch/cpu.h> /* get chip and board defs */
35
Simon Glass068a1e42013-03-05 14:39:58 +000036#define CONFIG_SYS_GENERIC_BOARD
Chander Kashyap0aee53b2012-02-05 23:01:47 +000037#define CONFIG_ARCH_CPU_INIT
38#define CONFIG_DISPLAY_CPUINFO
39#define CONFIG_DISPLAY_BOARDINFO
40
Hatim RV540b5af2012-12-11 00:52:48 +000041/* Enable fdt support for Exynos5250 */
42#define CONFIG_ARCH_DEVICE_TREE exynos5250
43#define CONFIG_OF_CONTROL
44#define CONFIG_OF_SEPARATE
45
Simon Glass5b7dcf32013-06-11 11:14:51 -070046/* Allow tracing to be enabled */
47#define CONFIG_TRACE
48#define CONFIG_CMD_TRACE
49#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
50#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
51#define CONFIG_TRACE_EARLY
52#define CONFIG_TRACE_EARLY_ADDR 0x50000000
53
Chander Kashyap0aee53b2012-02-05 23:01:47 +000054/* Keep L2 Cache Disabled */
55#define CONFIG_SYS_DCACHE_OFF
56
Akshay Saraswat8e6ee292013-03-20 21:00:57 +000057/* Enable ACE acceleration for SHA1 and SHA256 */
58#define CONFIG_EXYNOS_ACE_SHA
Akshay Saraswat2c6346c2013-03-20 21:00:59 +000059#define CONFIG_SHA_HW_ACCEL
Akshay Saraswat8e6ee292013-03-20 21:00:57 +000060
Chander Kashyap0aee53b2012-02-05 23:01:47 +000061#define CONFIG_SYS_SDRAM_BASE 0x40000000
62#define CONFIG_SYS_TEXT_BASE 0x43E00000
63
64/* input clock of PLL: SMDK5250 has 24MHz input clock */
65#define CONFIG_SYS_CLK_FREQ 24000000
66
67#define CONFIG_SETUP_MEMORY_TAGS
68#define CONFIG_CMDLINE_TAG
69#define CONFIG_INITRD_TAG
70#define CONFIG_CMDLINE_EDITING
71
72/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
73#define MACH_TYPE_SMDK5250 3774
74#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
75
76/* Power Down Modes */
77#define S5P_CHECK_SLEEP 0x00000BAD
78#define S5P_CHECK_DIDLE 0xBAD00000
79#define S5P_CHECK_LPA 0xABAD0000
80
81/* Offset for inform registers */
82#define INFORM0_OFFSET 0x800
83#define INFORM1_OFFSET 0x804
84
85/* Size of malloc() pool */
Rajeshwari Shinde211e8432012-12-10 01:55:48 +000086#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
Chander Kashyap0aee53b2012-02-05 23:01:47 +000087
88/* select serial console configuration */
Rajeshwari Shinde41222c22012-07-03 20:03:00 +000089#define CONFIG_SERIAL3 /* use SERIAL 3 */
Chander Kashyap0aee53b2012-02-05 23:01:47 +000090#define CONFIG_BAUDRATE 115200
91#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
92
Hung-ying Tyaneb28fda2013-05-15 18:27:34 +080093/* Enable keyboard */
94#define CONFIG_CROS_EC /* CROS_EC protocol */
95#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
96#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
97#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
98#define CONFIG_CMD_CROS_EC
99#define CONFIG_KEYBOARD
100
Ajay Kumara2468de2013-01-10 21:06:11 +0000101/* Console configuration */
102#define CONFIG_CONSOLE_MUX
103#define CONFIG_SYS_CONSOLE_IS_IN_ENV
104#define EXYNOS_DEVICE_SETTINGS \
Hung-ying Tyaneb28fda2013-05-15 18:27:34 +0800105 "stdin=serial,cros-ec-keyb\0" \
Ajay Kumara2468de2013-01-10 21:06:11 +0000106 "stdout=serial,lcd\0" \
107 "stderr=serial,lcd\0"
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 EXYNOS_DEVICE_SETTINGS
111
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000112/* SD/MMC configuration */
113#define CONFIG_GENERIC_MMC
114#define CONFIG_MMC
Jaehoon Chung7d2d58b2012-04-23 02:36:29 +0000115#define CONFIG_SDHCI
116#define CONFIG_S5P_SDHCI
Amar752f4c42013-04-27 11:42:57 +0530117#define CONFIG_DWMMC
118#define CONFIG_EXYNOS_DWMMC
119#define CONFIG_SUPPORT_EMMC_BOOT
120
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000121
122#define CONFIG_BOARD_EARLY_INIT_F
123
124/* PWM */
125#define CONFIG_PWM
126
127/* allow to overwrite serial and ethaddr */
128#define CONFIG_ENV_OVERWRITE
129
130/* Command definition*/
131#include <config_cmd_default.h>
132
133#define CONFIG_CMD_PING
134#define CONFIG_CMD_ELF
135#define CONFIG_CMD_MMC
136#define CONFIG_CMD_EXT2
137#define CONFIG_CMD_FAT
Chander Kashyapbf936212012-02-09 01:26:19 +0000138#define CONFIG_CMD_NET
Akshay Saraswat2c6346c2013-03-20 21:00:59 +0000139#define CONFIG_CMD_HASH
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000140
141#define CONFIG_BOOTDELAY 3
142#define CONFIG_ZERO_BOOTDELAY_CHECK
143
Akshay Saraswatf7f85f72013-02-25 01:13:03 +0000144/* Thermal Management Unit */
145#define CONFIG_EXYNOS_TMU
Akshay Saraswat8afcfc22013-02-25 01:13:05 +0000146#define CONFIG_CMD_DTT
147#define CONFIG_TMU_CMD_DTT
Akshay Saraswatf7f85f72013-02-25 01:13:03 +0000148
Rajeshwari Shindea4dae632012-05-14 05:52:05 +0000149/* USB */
150#define CONFIG_CMD_USB
151#define CONFIG_USB_EHCI
152#define CONFIG_USB_EHCI_EXYNOS
153#define CONFIG_USB_STORAGE
154
Vivek Gautam70656c72013-01-28 00:39:59 +0000155/* USB boot mode */
156#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
157#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
158#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
159
Simon Glassc1af6082013-04-12 10:44:58 +0000160/* TPM */
161#define CONFIG_TPM
162#define CONFIG_CMD_TPM
Tom Wai-Hong Tam1b393db2013-04-12 11:04:37 +0000163#define CONFIG_TPM_TIS_I2C
164#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
165#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
Simon Glassc1af6082013-04-12 10:44:58 +0000166
Chander Kashyap81e35202012-02-05 23:01:48 +0000167/* MMC SPL */
168#define CONFIG_SPL
169#define COPY_BL2_FNPTR_ADDR 0x02020030
170
Rajeshwari Shinde78fbcc92012-07-03 20:02:53 +0000171/* specific .lds file */
172#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
173#define CONFIG_SPL_TEXT_BASE 0x02023400
Albert ARIBAUDeac579d2013-04-12 05:14:33 +0000174#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
Rajeshwari Shinde78fbcc92012-07-03 20:02:53 +0000175
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000176#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
177
178/* Miscellaneous configurable options */
179#define CONFIG_SYS_LONGHELP /* undef to save memory */
180#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000181#define CONFIG_SYS_PROMPT "SMDK5250 # "
182#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
183#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
184#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
185#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
186/* Boot Argument Buffer Size */
187#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
188/* memtest works on */
189#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
190#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
191#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
192
193#define CONFIG_SYS_HZ 1000
194
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000195#define CONFIG_RD_LVL
196
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000197#define CONFIG_NR_DRAM_BANKS 8
198#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
199#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
200#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
201#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
202#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
203#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
204#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
205#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
206#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
207#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
208#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
209#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
210#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
211#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
212#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
213#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
214#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
215
216#define CONFIG_SYS_MONITOR_BASE 0x00000000
217
218/* FLASH and environment organization */
219#define CONFIG_SYS_NO_FLASH
220#undef CONFIG_CMD_IMLS
221#define CONFIG_IDENT_STRING " for SMDK5250"
222
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000223#define CONFIG_SYS_MMC_ENV_DEV 0
224
225#define CONFIG_SECURE_BL1_ONLY
226
227/* Secure FW size configuration */
228#ifdef CONFIG_SECURE_BL1_ONLY
229#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
230#else
231#define CONFIG_SEC_FW_SIZE 0
232#endif
233
234/* Configuration of BL1, BL2, ENV Blocks on mmc */
235#define CONFIG_RES_BLOCK_SIZE (512)
236#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
237#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
238#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
239
240#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
241#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
242#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
243
Chander Kashyap81e35202012-02-05 23:01:48 +0000244/* U-boot copy size from boot Media to DRAM.*/
245#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
246#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
Rajeshwari Shinde7a533772012-11-02 01:15:38 +0000247
248#define OM_STAT (0x1f << 1)
249#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
250#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
251
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000252#define CONFIG_DOS_PARTITION
Amar752f4c42013-04-27 11:42:57 +0530253#define CONFIG_EFI_PARTITION
254#define CONFIG_CMD_PART
255#define CONFIG_PARTITION_UUIDS
256
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000257
258#define CONFIG_IRAM_STACK 0x02050000
259
260#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
261
Rajeshwari Shindec82b0502012-07-23 21:23:55 +0000262/* I2C */
263#define CONFIG_SYS_I2C_INIT_BOARD
264#define CONFIG_HARD_I2C
265#define CONFIG_CMD_I2C
266#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
267#define CONFIG_DRIVER_S3C24X0_I2C
268#define CONFIG_I2C_MULTI_BUS
269#define CONFIG_MAX_I2C_NUM 8
270#define CONFIG_SYS_I2C_SLAVE 0x0
Simon Glass23b479b2012-12-05 14:46:45 +0000271#define CONFIG_I2C_EDID
Rajeshwari Shindec82b0502012-07-23 21:23:55 +0000272
Rajeshwari Shinde0d146a52012-08-24 00:39:24 +0000273/* PMIC */
274#define CONFIG_PMIC
275#define CONFIG_PMIC_I2C
276#define CONFIG_PMIC_MAX77686
277
Hatim RV3a8a7002012-11-02 01:15:37 +0000278/* SPI */
279#define CONFIG_ENV_IS_IN_SPI_FLASH
280#define CONFIG_SPI_FLASH
281
282#ifdef CONFIG_SPI_FLASH
283#define CONFIG_EXYNOS_SPI
284#define CONFIG_CMD_SF
285#define CONFIG_CMD_SPI
286#define CONFIG_SPI_FLASH_WINBOND
Rajeshwari Shindec7c4fe02013-01-22 20:31:57 +0000287#define CONFIG_SPI_FLASH_GIGADEVICE
Hatim RV3a8a7002012-11-02 01:15:37 +0000288#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
289#define CONFIG_SF_DEFAULT_SPEED 50000000
290#define EXYNOS5_SPI_NUM_CONTROLLERS 5
291#endif
292
293#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
294#define CONFIG_ENV_SPI_MODE SPI_MODE_0
295#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
296#define CONFIG_ENV_SPI_BUS 1
297#define CONFIG_ENV_SPI_MAX_HZ 50000000
298#endif
299
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000300/* PMIC */
Rajeshwari Shinde211e8432012-12-10 01:55:48 +0000301#define CONFIG_POWER
302#define CONFIG_POWER_I2C
303#define CONFIG_POWER_MAX77686
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000304
305/* SPI */
306#define CONFIG_ENV_IS_IN_SPI_FLASH
307#define CONFIG_SPI_FLASH
308
Chander Kashyap061562c2012-09-05 00:38:21 +0000309#ifdef CONFIG_SPI_FLASH
310#define CONFIG_EXYNOS_SPI
311#define CONFIG_CMD_SF
312#define CONFIG_CMD_SPI
313#define CONFIG_SPI_FLASH_WINBOND
314#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000315#define CONFIG_SF_DEFAULT_SPEED 50000000
316#define EXYNOS5_SPI_NUM_CONTROLLERS 5
317#endif
318
319#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
Rajeshwari Shinde36364712012-10-25 19:49:30 +0000320#define CONFIG_ENV_SPI_MODE SPI_MODE_0
321#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
322#define CONFIG_ENV_SPI_BUS 1
323#define CONFIG_ENV_SPI_MAX_HZ 50000000
324#endif
325
326/* Ethernet Controllor Driver */
327#ifdef CONFIG_CMD_NET
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000328#define CONFIG_SMC911X
329#define CONFIG_SMC911X_BASE 0x5000000
330#define CONFIG_SMC911X_16_BIT
331#define CONFIG_ENV_SROM_BANK 1
332#endif /*CONFIG_CMD_NET*/
333
334/* Enable PXE Support */
335#ifdef CONFIG_CMD_NET
336#define CONFIG_CMD_PXE
337#define CONFIG_MENU
338#endif
339
340/* Sound */
341#define CONFIG_CMD_SOUND
342#ifdef CONFIG_CMD_SOUND
343#define CONFIG_SOUND
344#define CONFIG_I2S
Rajeshwari Shindecfa6df12013-02-14 19:46:16 +0000345#define CONFIG_SOUND_MAX98095
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000346#define CONFIG_SOUND_WM8994
347#endif
348
349/* Enable devicetree support */
350#define CONFIG_OF_LIBFDT
351
Simon Glass23b479b2012-12-05 14:46:45 +0000352/* SHA hashing */
353#define CONFIG_CMD_HASH
354#define CONFIG_HASH_VERIFY
355#define CONFIG_SHA1
356#define CONFIG_SHA256
357
Ajay Kumar9b572852013-01-08 20:42:26 +0000358/* Display */
359#define CONFIG_LCD
Ajay Kumar99e51622013-01-10 21:06:10 +0000360#ifdef CONFIG_LCD
Ajay Kumar9b572852013-01-08 20:42:26 +0000361#define CONFIG_EXYNOS_FB
362#define CONFIG_EXYNOS_DP
363#define LCD_XRES 2560
364#define LCD_YRES 1600
365#define LCD_BPP LCD_COLOR16
Ajay Kumar99e51622013-01-10 21:06:10 +0000366#endif
Ajay Kumar9b572852013-01-08 20:42:26 +0000367
Akshay Saraswat4f3bfa92013-03-28 04:32:15 +0000368/* Enable Time Command */
369#define CONFIG_CMD_TIME
370
Chander Kashyap0aee53b2012-02-05 23:01:47 +0000371#endif /* __CONFIG_H */