blob: fb77db33f1365c15132296e81d7ba9dd0dd1ebad [file] [log] [blame]
Chander Kashyape21185b2011-05-24 20:02:56 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 *
Chander Kashyap393cb362011-12-06 23:34:12 +00004 * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
Chander Kashyape21185b2011-05-24 20:02:56 +00005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Chander Kashyape21185b2011-05-24 20:02:56 +00007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Simon Glass1d551102014-10-07 22:01:49 -060012#include "exynos4-common.h"
13
14#undef CONFIG_BOARD_COMMON
Marek Vasute30824f2015-08-19 23:27:26 +020015#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
Simon Glass1d551102014-10-07 22:01:49 -060016#undef CONFIG_REVISION_TAG
Simon Glass1d551102014-10-07 22:01:49 -060017
Chander Kashyape21185b2011-05-24 20:02:56 +000018/* High Level Configuration Options */
Chander Kashyap393cb362011-12-06 23:34:12 +000019#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
Chander Kashyape21185b2011-05-24 20:02:56 +000020#define CONFIG_SMDKV310 1 /* working with SMDKV310*/
21
Chander Kashyapb3c5a492011-09-20 21:25:01 +000022/* Mach Type */
23#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
24
Chander Kashyape21185b2011-05-24 20:02:56 +000025#define CONFIG_SYS_SDRAM_BASE 0x40000000
26#define CONFIG_SYS_TEXT_BASE 0x43E00000
27
Chander Kashyape21185b2011-05-24 20:02:56 +000028/* Handling Sleep Mode*/
29#define S5P_CHECK_SLEEP 0x00000BAD
30#define S5P_CHECK_DIDLE 0xBAD00000
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053031#define S5P_CHECK_LPA 0xABAD0000
Chander Kashyape21185b2011-05-24 20:02:56 +000032
Chander Kashyape21185b2011-05-24 20:02:56 +000033/* select serial console configuration */
Chander Kashyape21185b2011-05-24 20:02:56 +000034#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
Chander Kashyap393cb362011-12-06 23:34:12 +000035#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
Chander Kashyape21185b2011-05-24 20:02:56 +000036
Chander Kashyape21185b2011-05-24 20:02:56 +000037/* allow to overwrite serial and ethaddr */
38#define CONFIG_ENV_OVERWRITE
39
Chander Kashyap5187d8d2011-09-20 21:25:03 +000040/* MMC SPL */
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053041#define CONFIG_SKIP_LOWLEVEL_INIT
Chander Kashyap9b3ab1c2011-09-20 21:25:04 +000042#define COPY_BL2_FNPTR_ADDR 0x00002488
Chander Kashyape21185b2011-05-24 20:02:56 +000043
Inderpal Singh8a000612013-04-04 23:09:21 +000044#define CONFIG_SPL_TEXT_BASE 0x02021410
45
Chander Kashyape21185b2011-05-24 20:02:56 +000046#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
47
48/* Miscellaneous configurable options */
Chander Kashyape21185b2011-05-24 20:02:56 +000049#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
Chander Kashyape21185b2011-05-24 20:02:56 +000050/* memtest works on */
51#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
52#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
53#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
54
Chander Kashyape21185b2011-05-24 20:02:56 +000055/* SMDKV310 has 4 bank of DRAM */
56#define CONFIG_NR_DRAM_BANKS 4
57#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
58#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
59#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
60#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
61#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
62#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
63#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
64#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
65#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
66
67/* FLASH and environment organization */
Chander Kashyape21185b2011-05-24 20:02:56 +000068
Chander Kashyape21185b2011-05-24 20:02:56 +000069#define CONFIG_CLK_1000_400_200
70
71/* MIU (Memory Interleaving Unit) */
72#define CONFIG_MIU_2BIT_INTERLEAVED
73
Chander Kashyape21185b2011-05-24 20:02:56 +000074#define CONFIG_SYS_MMC_ENV_DEV 0
75#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
76#define RESERVE_BLOCK_SIZE (512)
77#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
78#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
Chander Kashyape21185b2011-05-24 20:02:56 +000079
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053080#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
81
82#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
Chander Kashyape21185b2011-05-24 20:02:56 +000083
Bin Menga1875592016-02-05 19:30:11 -080084/* U-Boot copy size from boot Media to DRAM.*/
Chander Kashyape21185b2011-05-24 20:02:56 +000085#define COPY_BL2_SIZE 0x80000
86#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
87#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
88
89/* Ethernet Controllor Driver */
90#ifdef CONFIG_CMD_NET
Chander Kashyape21185b2011-05-24 20:02:56 +000091#define CONFIG_SMC911X
92#define CONFIG_SMC911X_BASE 0x5000000
93#define CONFIG_SMC911X_16_BIT
94#define CONFIG_ENV_SROM_BANK 1
95#endif /*CONFIG_CMD_NET*/
Thomas Abraham07407d92011-06-03 22:52:17 +000096
Chander Kashyape21185b2011-05-24 20:02:56 +000097#endif /* __CONFIG_H */